LM12454CIV [NSC]
12-Bit Sign Data Acquisition System with Self-Calibration; 12位注册数据采集系统具有自校准
| 型号： | LM12454CIV |
| 厂家： | 
National Semiconductor |
| 描述： | 12-Bit Sign Data Acquisition System with Self-Calibration |
| 文件： | 总43页 (文件大小：993K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1999
LM12454/LM12458/LM12H458
12-Bit + Sign Data Acquisition System with
Self-Calibration
General Description
Key Specifications
=
(fCLK 5 MHz; 8 MHz, H)
The LM12454, LM12458, and LM12H458 are highly inte-
grated Data Acquisition Systems. Operating on just 5V, they
combine a fully-differential self-calibrating (correcting linear-
ity and zero errors) 13-bit (12-bit + sign) analog-to-digital
converter (ADC) and sample-and-hold (S/H) with extensive
analog functions and digital functionality. Up to 32 consecu-
tive conversions, using two’s complement format, can be
stored in an internal 32-word (16-bit wide) FIFO data buffer.
An internal 8-word RAM can store the conversion sequence
for up to eight acquisitions through the LM12(H)458’s
eight-input multiplexer. The LM12454 has a four-channel
multiplexer, a differential multiplexer output, and a differential
S/H input. The LM12454 and LM12(H)458 can also operate
with 8-bit + sign resolution and in a supervisory “watchdog”
mode that compares an input signal against two program-
mable limits.
j
j
j
j
Resolution
12-bit + sign or 8-bit + sign
8.8 µs, 5.5 µs (H) (max)
4.2 µs, 2.6 µs (H) (max)
13-bit conversion time
9-bit conversion time
13-bit Through-put rate
88k samples/s (min),
140k samples/s (H) (min)
j
Comparison time
2.2 µs (max),
1.4 µs (H) (max)
(“watchdog” mode)
j
j
j
j
j
±
1 LSB (max)
ILE
+
VIN range
GND to VA
Power dissipation
Stand-by mode
Single supply
30 mW, 34 mW (H) (max)
50 µW (typ)
3V to 5.5V
Programmable acquisition times and conversion rates are
possible through the use of internal clock-driven timers. The
reference voltage input can be externally generated for ab-
solute or ratiometric operation or can be derived using the in-
ternal 2.5V bandgap reference.
Features
n Three operating modes: 12-bit + sign, 8-bit + sign, and
“watchdog”
n Single-ended or differential inputs
n Built-in Sample-and-Hold and 2.5V bandgap reference
n Instruction RAM and event sequencer
n 8-channel (LM12(H)458), 4-channel (LM12454)
multiplexer
All registers, RAM, and FIFO are directly addressable
through the high speed microprocessor interface to either an
8-bit or 16-bit databus. The LM12454 and LM12(H)458 in-
clude
a direct memory access (DMA) interface for
high-speed conversion data transfer.
n 32-word conversion FIFO
An evaluation/interface board is available. Order num-
ber LM12458EVAL.
n Programmable acquisition times and conversion rates
n Self-calibration and diagnostic mode
n 8- or 16-bit wide databus dmicroprocessor or DSP
interface
Additional applications information can be found in applica-
tions notes AN-906, AN-947 and AN-949.
Applications
n Data Logging
n Instrumentation
n Process Control
n Energy Management
n Inertial Guidance
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
AT® is a registered trademark of International Business Machines Corporation.
© 1999 National Semiconductor Corporation
DS011264
www.national.com
Ordering Information
Guaranteed
Clock Freq (min)
8 MHz
Guaranteed
Order
See NS
Package Number
V44A
Linearity Error (max)
Part Number
±
1.0 LSB
LM12H458CIV
LM12H458CIVF
LM12H458MEL/883
or 5962-9319502MYA
LM12454CIV
VGZ44A
EL44A
±
5 MHz
1.0 LSB
V44A
V44A
LM12458CIV
LM12458CIVF
VGZ44A
Connection Diagrams
DS011264-34
Order Number LM12458CIVF or LM12H458CIVF
See NS Package Number VGZ44A
DS011264-2
* Pin names in ( ) apply to the LM12454 and LM12H454.
Order Number LM12454CIV,
LM12458CIV or LM12H458CIV
See NS Package Number V44A
Order Number LM12H458MEL/883 or 5962-9319502MYA
See NS Package Number EL44A
www.national.com
2
Functional Diagrams
LM12454
DS011264-1
LM12(H)458
DS011264-21
3
www.national.com
See AN-450 “Surface Mounting Methods and Their Effect on
Product Reliability” for other methods of soldering surface
mount devices.
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings (Notes 1, 2)
Supply Voltage (VA+ and VD+)
Voltage at Input and Output Pins
except IN0–IN3 (LM12454)
and IN0–IN7 (LM12(H)458)
6.0V
Temperature Range
(Tmin ≤ TA ≤ Tmax
)
−0.3V to V+ + 0.3V
LM12454CIV/
LM12(H)458CIV
−40˚C ≤ TA ≤ 85˚C
−55˚C ≤ TA ≤ 125˚C
Voltage at Analog Inputs IN0–IN3 (LM12454)
LM12458MEL/883
Supply Voltage
and IN0–IN7 (LM12(H)458)
|VA+ − VD+|
GND − 5V to V+ + 5V
300 mV
VA+, VD+
3.0V to 5.5V
≤100 mV
±
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
5 mA
|VA+ − VD+|
±
20 mA
VIN+ Input Range
VIN− Input Range
VREF+ Input Voltage
VREF− Input Voltage
VREF+ − VREF−
GND ≤ VIN+ ≤ VA+
GND ≤ VIN− ≤ VA+
1V ≤ VREF+ ≤ VA+
0V ≤ VREF− ≤ VREF+ − 1V
1V ≤ VREF ≤ VA+
=
Power Dissipation (TA 25˚C)
V Package (Note 4)
Storage Temperature
Lead Temperature
875 mW
−65˚C to +150˚C
V Package, Infrared, 15 sec.
EL and W Packages,
Solder, 10 sec.
+300˚C
VREF Common Mode
Range (Note 16)
+
+
0.1 VA ≤ VREFCM ≤ 0.6 VA
+250˚C
1.5 kV
2.0 kV
ESD Susceptibility (Note 5)
LM12458MEL/883
Converter Characteristics (Notes 6, 7, 8, 9, 19)
=
=
=
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ VD+ 5V, VREF+ 5V, VREF− 0V,
=
=
=
12-bit + sign conversion mode, fCLK 8.0 MHz (LM12H458) or fCLK 5.0 MHz (LM12454/8), RS 25Ω, source impedance for
VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
=
=
=
=
otherwise specified. Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Symbol
ILE
Parameter
Conditions
Typical
Limits
Unit
(Note 10) (Note 11)
(Limit)
±
±
1
Positive and Negative Integral
Linearity Error
After Auto-Cal (Notes 12, 17)
1/2
LSB (max)
±
TUE
DNL
Total Unadjusted Error
Resolution with No Missing Codes
Differential Non-Linearity
Zero Error
After Auto-Cal (Note 12)
After Auto-Cal (Note 12)
After Auto-Cal
1
LSB
13
Bits (max)
LSB (max)
3
±
⁄
4
±
After Auto-Cal (Notes 13, 17)
LM12H458
1
±
±
±
1/2
1/2
1.5
LSB (max)
LSB (max)
±
Positive Full-Scale Error
Negative Full-Scale Error
After Auto-Cal (Notes 12, 17)
LM12(H)458MEL
2
±
2.5
±
±
After Auto-Cal (Notes 12, 17)
LM12(H)458MEL
1/2
2
LSB (max)
LSB (max)
LSB (max)
LSB (max)
Bits (max)
LSB (max)
LSB (max)
LSB (max)
±
2.5
3.5
±
±
DC Common Mode Error
(Note 14)
2
ILE
8-Bit + Sign and “Watchdog”
Mode Positive and Negative
Integral Linearity Error
(Note 12)
±
±
1/2
3/4
9
±
TUE
8-Bit + Sign and “Watchdog” Mode
Total Unadjusted Error
After Auto-Zero
1/2
8-Bit + Sign and “Watchdog” Mode
Resolution with No Missing Codes
8-Bit + Sign and “Watchdog” Mode
Differential Non-Linearity
±
±
±
DNL
3/4
1/2
1/2
8-Bit + Sign and “Watchdog” Mode
Zero Error
After Auto-Zero
8-Bit + Sign and “Watchdog” Positive
and Negative Full-Scale Error
www.national.com
4
Converter Characteristics (Notes 6, 7, 8, 9, 19) (Continued)
=
=
=
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ VD+ 5V, VREF+ 5V, VREF− 0V,
=
=
=
12-bit + sign conversion mode, fCLK 8.0 MHz (LM12H458) or fCLK 5.0 MHz (LM12454/8), RS 25Ω, source impedance for
VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
otherwise specified. Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
=
=
=
=
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Limit)
LSB
(Note 10) (Note 11)
±
8-Bit + Sign and “Watchdog” Mode
DC Common Mode Error
Multiplexer Channel-to-Channel
Matching
1/8
±
0.05
LSB
VIN+
Non-Inverting Input Range
GND
VA+
V (min)
V (max)
V (min)
V (max)
V (min)
V (max)
V (min)
V (max)
LSB (max)
LSB (max)
LSB
VIN−
Inverting Input Range
GND
VA+
+
VIN+ − VIN−
Differential Input Voltage Range
Common Mode Input Voltage Range
−VA
VA+
GND
VA+
=
=
±
±
±
1.75
PSS
Power Supply
Sensitivity
Zero Error
Full-Scale Error
Linearity Error
VA+ VD+ 5V 10%
0.2
0.4
0.2
=
=
±
±
2
VREF+ 4.5V, VREF− GND
±
(Note 15)
CREF
CIN
VREF+/VREF− Input Capacitance
Selected Multiplexer Channel Input
Capacitance
85
75
pF
pF
Converter AC Characteristics (Notes 6, 7, 8, 9, 19)
=
=
=
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ VD+ 5V, VREF+ 5V, VREF− 0V,
=
=
=
12-bit + sign conversion mode, fCLK 8.0 MHz (LM12H458) or fCLK 5.0 MHz (LM12454/8), RS 25Ω, source impedance for
VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
=
=
=
=
otherwise specified. Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Symbol
Parameter
Clock Duty Cycle
Conditions
Typical
(Note 10)
50
Limits
Unit
(Limit)
%
(Note 11)
40
60
% (min)
%
(max)
tC
Conversion Time
Acquisition Time
13-Bit Resolution,
44 (tCLK
)
)
44 (tCLK) + 50 ns
21 (tCLK) + 50 ns
9 (tCLK) + 50 ns
2 (tCLK) + 50 ns
(max)
(max)
(max)
(max)
Sequencer State S5 (Figure 15)
9-Bit Resolution,
21 (tCLK
Sequencer State S5 (Figure 15)
Sequencer State S7 (Figure 15)
Built-in minimum for 13-Bits
Built-in minimum for 9-Bits and
“Watchdog” mode
tA
9 (tCLK
)
2 (tCLK
)
tZ
Auto-Zero Time
Full Calibration Time
Throughput Rate
(Note 18)
Sequencer State S2 (Figure 15)
Sequencer State S2 (Figure 15)
76 (tCLK
)
76 (tCLK) + 50 ns
4944 (tCLK) + 50 ns
88
(max)
(max)
kHz
tCAL
4944 (tCLK
)
89
LM12H458
142
140
(min)
(max)
tWD
“Watchdog” Mode Comparison
Time
Sequencer States S6, S4,
and S5 (Figure 15)
11 (tCLK
)
11 (tCLK) + 50 ns
5
www.national.com
Converter AC Characteristics (Notes 6, 7, 8, 9, 19) (Continued)
=
=
=
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ VD+ 5V, VREF+ 5V, VREF− 0V,
=
=
=
12-bit + sign conversion mode, fCLK 8.0 MHz (LM12H458) or fCLK 5.0 MHz (LM12454/8), RS 25Ω, source impedance for
VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
otherwise specified. Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
=
=
=
=
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
=
±
DSNR
Differential Signal-to-Noise Ratio
VIN
5V
=
fIN 1 kHz
77.5
75.2
74.7
dB
dB
dB
=
fIN 20 kHz
=
fIN 40 kHz
=
VIN 5 Vp-p
SESNR
DSINAD
Single-Ended Signal-to-Noise
Ratio
=
fIN 1 kHz
69.8
69.2
66.6
dB
dB
dB
=
fIN 20 kHz
=
fIN 40 kHz
=
±
Differential Signal-to-Noise +
Distortion Ratio
VIN
5V
=
fIN 1 kHz
76.9
73.9
70.7
dB
dB
dB
=
fIN 20 kHz
=
fIN 40 kHz
=
VIN 5 Vp-p
SESINAD Single-Ended Signal-to-Noise +
Distortion Ratio
=
fIN 1 kHz
69.4
68.3
65.7
dB
dB
dB
=
fIN 20 kHz
=
fIN 40 kHz
=
±
DTHD
Differential Total Harmonic
Distortion
VIN
5V
=
fIN 1 kHz
−85.8
−79.9
−72.9
dB
dB
dB
=
fIN 20 kHz
=
fIN 40 kHz
=
VIN 5 Vp-p
SETHD
DENOB
Single-Ended Total Harmonic
Distortion
=
fIN 1 kHz
−80.3
−75.6
−72.8
dB
dB
dB
=
fIN 20 kHz
=
fIN 40 kHz
=
±
Differential Effective Number
of Bits
VIN
5V
=
fIN 1 kHz
12.6
12.2
12.1
Bits
Bits
Bits
=
fIN 20 kHz
=
fIN 40 kHz
=
VIN 5 Vp-p
SEENOB Single-Ended Effective Number
of Bits
=
fIN 1 kHz
11.3
11.2
10.8
Bits
Bits
Bits
=
fIN 20 kHz
=
fIN 40 kHz
=
±
DSFDR
Differential Spurious Free
Dynamic Range
VIN
5V
=
fIN 1 kHz
87.2
78.9
72.8
dB
dB
dB
=
fIN 20 kHz
=
fIN 40 kHz
=
VIN 5 VPP
Multiplexer Channel-to-Channel
Crosstalk
=
fIN 40 kHz
LM12454 MUXOUT Only
LM12(H)458 MUX
plus Converter
−76
−78
dB
dB
tPU
Power-Up Time
Wake-Up Time
10
10
ms
ms
tWU
www.national.com
6
DC Characteristics (Notes 6, 7, 8, 19)
=
=
=
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ VD+ 5V, VREF+ 5V, VREF− 0V,
=
=
fCLK 8.0 MHz (LM12H454/8) or fCLK 5.0 MHz (LM12458), and minimum acquisition time unless otherwise specified. Bold-
=
=
=
=
face limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
=
CS “1”
ID+
VD+ Supply Current
LM12454/8
LM12H458
0.55
0.55
1.0
1.2
mA (max)
mA (max)
=
IA+
VA+ Supply Current
CS “1”
LM12454/8
3.1
3.1
5.0
5.5
LM12H458
IST
Stand-By Supply Current (ID+ + IA+)
Multiplexer ON-Channel Leakage Current
Power-Down Mode Selected
Clock Stopped
8 MHz Clock
10
40
µA (max)
µA (max)
=
VA+ 5.5V
=
ON-Channel 5.5V
0.3
=
OFF-Channel 0V
0.1
0.1
µA (max)
µA (max)
LM12(H)458MEL
0.5
0.3
=
ON-Channel 0V
=
OFF-Channel 5.5V
LM12(H)458MEL
0.5
0.3
=
VA+ 5.5V
Multiplexer OFF-Channel Leakage Current
=
ON-Channel 5.5V
=
OFF-Channel 0V
0.1
0.1
µA (max)
µA (max)
LM12(H)458MEL
0.5
0.3
=
ON-Channel 0V
=
OFF-Channel 5.5V
LM12(H)458MEL
LM12454
0.5
RON
Multiplexer ON-Resistance
=
VIN 5V
800
850
760
1500
1500
1500
Ω(max)
Ω(max)
Ω(max)
=
VIN 2.5V
=
VIN 0V
Multiplexer Channel-to-Channel
RON matching
LM12454
=
±
±
±
±
±
±
VIN 5V
1.0%
1.0%
1.0%
3.0%
3.0%
3.0%
(max)
(max)
(max)
=
VIN 2.5V
=
VIN 0V
Internal Reference Characteristics (Notes 6, 7, 19)
=
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ VD+ 5V unless otherwise specified.
=
=
=
=
Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Symbol
Parameter
Conditions
Typical
(Note 10)
2.5
Limits
Unit
(Note 11)
(Limit)
V (max)
±
2.5 4%
VREFOUT Internal Reference Output Voltage
±
LM12(H)458MEL
2.5 6%
∆VREF/∆T Internal Reference Temperature
40
ppm/˚C
Coefficient
<
∆
REF/∆IL Internal Reference Load Regulation
Sourcing (0 IL ≤ +4 mA)
0.2
1.2
20
%/mA (max)
%/mA (max)
mV (max)
mA (max)
ppm/kHr
<
Sinking (−1 ≤ IIL 0 mA)
∆VREF
Line Regulation
4.5V ≤ VA+ ≤ 5.5V
3
=
ISC
Internal Reference Short Circuit Current
VREFOUT 0V
13
25
∆VREF/∆t Long Term Stability
200
7
www.national.com
Internal Reference Characteristics (Notes 6, 7, 19) (Continued)
=
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ VD+ 5V unless otherwise specified.
=
=
=
=
Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Symbol
Parameter
Conditions
Typical
(Note 10)
10
Limits
Unit
(Limit)
ms
(Note 11)
=
=
→
tSU
Internal Reference Start-Up Time
VA+ VD+ 0V 5V
=
CL 100 µF
Digital Characteristics (Notes 6, 7, 8, 19)
=
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ VD+ 5V, unless otherwise speci-
=
=
=
=
fied. Boldface limits apply for TA TJ TMIN to TMAX; all other limits TA TJ 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 11)
2.0
Unit
(Note 10)
(Limit)
=
=
VIN(1)
VIN(0)
IIN(1)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
VA+ VD+ 5.5V
V (min)
V (max)
µA (max)
=
=
VA+ VD+ 4.5V
0.8
=
VIN 5V
0.005
−0.005
6
1.0
LM12(H)458MEL
2.0
=
IIN(0)
Logical “0” Input Current
VIN 0V
−1.0
−2.0
µA (max)
pF
LM12(H)458MEL
CIN
D0–D15 Input Capacitance
Logical “1” Output Voltage
= =
VA+ VD+ 4.5V
VOUT(1)
=
IOUT −360 µA
2.4
4.25
0.4
V (min)
V (min)
V (max)
=
IOUT −10 µA
= =
VA+ VD+ 4.5V
VOUT(0)
Logical “0” Output Voltage
=
IOUT 1.6 mA
TRI-STATE® Output Leakage Current
−0.01
0.01
−3.0
3.0
µA (max)
µA (max)
=
VOUT 0V
IOUT
=
VOUT 5V
Digital Timing Characteristics (Notes 6, 7, 8, 19)
=
=
=
=
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ VD+ 5V, tr tf 3 ns, and CL
=
=
100 pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for TA TJ TMIN to TMAX; all
=
=
other limits TA TJ 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 11)
40
Unit
(See Figures 8, 9, 10)
(Note 10)
(Limit)
ns (min)
1, 3
CS or Address Valid to ALE Low
Set-Up Time
2, 4
CS or Address Valid to ALE Low
Hold Time
20
ns (min)
5
6
ALE Pulse Width
45
35
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
RD High to Next ALE High
ALE Low to RD Low
7
20
8
RD Pulse Width
100
100
20
9
RD High to Next RD or WR Low
ALE Low to WR Low
10
11
12
13
14
15
16
WR Pulse Width
60
WR High to Next ALE High
WR High to Next RD or WR Low
Data Valid to WR High Set-Up Time
Data Valid to WR High Hold Time
RD Low to Data Bus Out of TRI-STATE
75
140
40
30
40
10
70
www.national.com
8
Digital Timing Characteristics (Notes 6, 7, 8, 19) (Continued)
=
=
=
=
=
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ VD+ 5V, tr tf 3 ns, and CL
=
=
100 pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for TA TJ TMIN to TMAX; all
=
=
other limits TA TJ 25˚C.
Symbol
Parameter
Conditions
Typical
(Note 10)
30
Limits
(Note 11)
10
Unit
(See Figures 8, 9, 10)
(Limit)
=
17
RD High to TRI-STATE
RL 1 kΩ
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
ns (min)
ns (min)
110
10
18
RD Low to Data Valid (Access Time)
30
80
20
21
19
Address Valid or CS Low to RD Low
Address Valid or CS Low to WR Low
Address Invalid
20
20
10
from RD or WR High
22
23
INT High from RD Low
30
30
10
60
10
60
ns (min)
ns (max)
ns (min)
ns (max)
DMARQ Low from RD Low
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
<
>
(V + or V +)), the current at that pin should be limited to 5 mA.
Note 3: When the input voltage (V ) at any pin exceeds the power supply rails (V
IN
GND or V
IN
IN
A
D
The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current of 5 mA, to simultaneously exceed the power supply volt-
ages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
(maximum junction temperature), θ (package junction
Jmax
to ambient thermal resistance), and T (ambient temperature). The maximum allowable power dissipation at any temperature is PD
JA
− T )/θ or the num-
=
(T
A
max
Jmax
A
JA
=
ber given in the Absolute Maximum Ratings, whichever is lower. For this device, T
Jmax
150˚C, and the typical thermal resistance (θ ) of the LM12454 and
JA
=
LM12(H)458 in the V package, when board mounted, is 47˚C/W, in the W package, when board mounted, is 50˚C/W (θJ
5.8˚C/W), and in the EL package, when
C
=
board mounted, is 70˚C/W (θJ
3.5˚C/W).
C
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above V + or 5V below GND
A
will not damage the LM12454 or the LM12(H)458. However, errors in the A/D conversion can occur if these diodes are forward biased by more than 100 mV. As an
example, if V + is 4.5 V , full-scale input voltage must be ≤4.6 V
DC DC
to ensure accurate conversions.
A
DS011264-3
+
Note 7:
V + and V + must be connected together to the same power supply voltage and bypassed with separate capacitors at each V pin to assure conversion/
A D
comparison accuracy.
=
=
Note 8: Accuracy is guaranteed when operating at f
5 MHz for the LM12454/8 and f
8 MHz for the LM12H458.
CLK
CLK
Note 9: With the test condition for V
REF
(V
− V ) given as +5V, the 12-bit LSB is 1.22 mV and the 8-bit/“Watchdog” LSB is 19.53 mV.
REF+ REF−
=
Note 10: Typicals are at T
25˚C and represent most likely parametric norm.
A
Note 11: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error the straight line passes through negative full-scale and zero. (See Figure 6 Figure 7).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between −1 to 0 and 0 to +1 (see Figure 8).
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V. The measured value is referred to the resulting out-
put value when the inputs are driven with a 2.5V signal.
Note 15: Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed with V + and V + at the specified extremes.
A
D
Note 16:
V
(Reference Voltage Common Mode Range) is defined as (V
REF+
+ V )/2.
REF−
REFCM
9
www.national.com
Digital Timing Characteristics (Notes 6, 7, 8, 19) (Continued)
Note 17: The LM12(H)454/8’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result
±
in a repeatability uncertainty of 0.10 LSB.
Note 18: The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock cycles) and 5 (44
clock cycles) are used (see Figure 15). One additional clock cycle is used to read the conversion result stored in the FIFO, for a total of 56 clock cycles per con-
version. The Throughput Rate is f
CLK
(MHz)/N, where N is the number of clock cycles/conversion.
Note 19: A military RETS specification is available upon request.
Electrical Characteristics
DS011264-22
=
V
V
V
− V
IN−
REF
REF+
− V
REF−
=
V
IN
IN+
GND ≤ V
GND ≤ V
≤V +
A
≤V +
A
IN+
IN−
FIGURE 1. The General Case of Output Digital Code vs the Operating Input Voltage Range
www.national.com
10
Electrical Characteristics (Continued)
DS011264-23
=
V
V
− V
REF−
4.096V
REF+
=
V
− V
IN−
IN
IN+
GND ≤ V
GND ≤ V
≤V
A
≤V
A
+
+
IN+
IN−
=
FIGURE 2. Specific Case of Output Digital Code vs the Operating Input Voltage Range for VREF 4.096V
11
www.national.com
Electrical Characteristics (Continued)
DS011264-24
=
V
REF
V
− V
REF+ REF−
FIGURE 3. The General Case of the VREF Operating Range
www.national.com
12
Electrical Characteristics (Continued)
DS011264-25
=
=
V
V
V
− V
REF−
REF
REF+
5V
+
A
=
FIGURE 4. The Specific Case of the VREF Operating Range for VA+ 5V
DS011264-4
FIGURE 5. Transfer Characteristic
13
www.national.com
Electrical Characteristics (Continued)
DS011264-5
FIGURE 6. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles
DS011264-6
FIGURE 7. Simplified Error Curve vs Output Code after Auto-Calibration Cycle
DS011264-7
FIGURE 8. Offset or Zero Error Voltage
www.national.com
14
Typical Performance Characteristics (Note 9) The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. The performance for 8-bit + sign and “watchdog” modes is equal to or better than
shown.
Linearity Error Change
vs Clock Frequency
Linearity Error Change
vs Temperature
Linearity Error Change
vs Reference Voltage
DS011264-37
DS011264-40
DS011264-43
DS011264-38
DS011264-41
DS011264-44
DS011264-39
Linearity Error Change
vs Supply Voltage
Full-Scale Error Change
vs Clock Frequency
Full-Scale Error Change
vs Temperature
DS011264-42
Full-Scale Error Change
vs Reference Voltage
Full-Scale Error
vs Supply Voltage
Zero Error Change
vs Clock Frequency
DS011264-45
15
www.national.com
Typical Performance Characteristics (Note 9) The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. The performance for 8-bit + sign and “watchdog” modes is equal to or better than
shown. (Continued)
Zero Error Change
vs Temperature
Zero Error Change
vs Reference Voltage
Zero Error Change
vs Supply Voltage
DS011264-46
DS011264-47
DS011264-48
Analog Supply Current
vs Temperature
Digital Supply Current
vs Clock Frequency
Digital Supply Current
vs Temperature
DS011264-49
DS011264-50
DS011264-51
VREFOUT Load Regulation
VREFOUT Line Regulation
DS011264-53
DS011264-52
www.national.com
16
Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign
mode after auto-calibration unless otherwise specified.
Bipolar Signal-to-Noise Ratio
vs Input Frequency
Bipolar Signal-to-Noise
+ Distortion Ratio
vs Input Frequency
Bipolar Signal-to-Noise
+ Distortion Ratio
vs Input Signal Level
DS011264-54
DS011264-55
DS011264-56
Bipolar Spectral Response
with 1.028 kHz Sine Wave Input
Bipolar Spectral Response
with 10 kHz Sine Wave Input
Bipolar Spectral Response
with 20 kHz Sine Wave Input
DS011264-57
DS011264-58
DS011264-59
Bipolar Spectral Response
with 40 kHz Sine Wave Input
Bipolar Spurious Free
Dynamic Range
Unipolar Signal-to-Noise Ratio
vs Input Frequency
DS011264-60
DS011264-61
DS011264-62
17
www.national.com
Typical Dynamic Performance Characteristics The following curves apply for 12-bit + sign
mode after auto-calibration unless otherwise specified. (Continued)
Unipolar Signal-to-Noise
+ Distortion Ratio
vs Input Frequency
Unipolar Signal-to-Noise
+ Distortion Ratio
vs Input Signal Level
Unipolar Spectral Response
with 1.028 kHz Sine Wave Input
DS011264-65
DS011264-63
DS011264-64
Unipolar Spectral Response
with 10 kHz Sine Wave Input
Unipolar Spectral Response
with 20 kHz Sine Wave Input
Unipolar Spectral Response
with 40 kHz Sine Wave Input
DS011264-66
DS011264-67
DS011264-68
Test Circuits and Waveforms
DS011264-13
DS011264-12
DS011264-15
DS011264-14
FIGURE 9. TRI-STATE Test Circuits and Waveforms
www.national.com
18
=
=
=
=
=
Timing Diagrams VA+ VD+ +5V, tR tF 3 ns, CL 100 pF for the INT, DMARQ, D0–D15 outputs.
DS011264-16
FIGURE 10. Multiplexed Data Bus
1, 3: CS or Address valid to ALE low set-up time.
2, 4: CS or Address valid to ALE low hold time.
5: ALE pulse width
11: WR pulse width
12: WR high to next ALE high
13: WR high to next WR or RD low
14: Data valid to WR high set-up time
15: Data valid to WR high hold time
16: RD low to data bus out of TRI-STATE
17: RD high to TRI-STATE
6: RD high to next ALE high
7: ALE low to RD low
8: RD pulse width
9: RD high to next RD or WR low
10: ALE low to WR low
18: RD low to data valid (access time)
19
www.national.com
=
=
=
=
=
Timing Diagrams VA+ VD+ +5V, tR tF 3 ns, CL 100 pF for the INT, DMARQ, D0–D15
outputs. (Continued)
DS011264-17
=
FIGURE 11. Non-Multiplexed Data Bus (ALE 1)
8: RD pulse width
16: RD low to data bus out of TRI-STATE
9: RD high to next RD or WR low
11: WR pulse width
17: RD high to TRI-STATE
18: RD low to data valid (access time)
13: WR high to next WR or RD low
14: Data valid to WR high set-up time
15: Data valid to WR high hold time
19: Address invalid from RD or WR high (hold time)
20: CS low or address valid to RD low
21: CS low or address valid to WR low
=
=
=
=
=
VA+ VD+ +5V, tR tF 3 ns, CL 100 pF for the INT, DMARQ, D0–D15 outputs.
DS011264-18
FIGURE 12. Interrupt and DMARQ
22: INT high from RD low
23: DMARQ low from RD low
www.national.com
20
Pin Description
VA+ VD+ Analog and digital supply voltage pins. The
LM12(H)454/8’s supply voltage operating range
is +3.0V to +5.5V. Accuracy is guaranteed only if
VA+ and VD+ are connected to the same power
supply. Each pin should have a parallel combina-
tion of 10 µF (electrolytic or tantalum) and 0.1 µF
(ceramic) bypass capacitors connected between
it and ground.
nal S/H to hold the input signal. The next rising
clock edge either starts a conversion or makes a
comparison to a programmable limit depending
on which function is requested by a programming
instruction. This pin will be an output if “I/O Se-
lect” is set high. The SYNC output goes high
when a conversion or a comparison is started
and low when completed. (See Section 2.2). An
internal reset after power is first applied to the
LM12(H)454/8 automatically sets this pin as an
input.
D0–D15 The internal data input/output TRI-STATE buffers
are connected to these pins. These buffers are
designed to drive capacitive loads of 100 pF or
less. External buffers are necessary for driving
higher load capacitances. These pins allows the
user a means of instruction input and data out-
put. With a logic high applied to the BW pin, data
lines D8–D15 are placed in a high impedance
state and data lines D0–D7 are used for instruc-
tion input and data output when the
LM12(H)454/8 is connected to an 8-bit wide data
bus. A logic low on the BW pin allows the
LM12(H)454/8 to exchange information over a
16-bit wide data bus.
BW
INT
Bus Width input pin. This input allows the
LM12(H)454/8 to interface directly with either an
8- or 16-bit databus. A logic high sets the width to
8 bits and places D8–D15 in a high impedance
state. A logic low sets the width to 16 bits.
Active low interrupt output. This output is de-
signed to drive capacitive loads of 100 pF or less.
External buffers are necessary for driving higher
load capacitances. An interrupt signal is gener-
ated any time a non-masked interrupt condition
takes place. There are eight different conditions
that can cause an interrupt. Any interrupt is reset
by reading the Interrupt Status register. (See
Section 2.3.)
RD
WR
CS
Input for the active low READ bus control signal.
The data input/output TRI-STATE buffers, as se-
lected by the logic signal applied to the BW pin,
are enabled when RD and CS are both low. This
allows the LM12(H)454/8 to transmit information
onto the databus.
DMARQ Active high Direct Memory Access Request out-
put. This output is designed to drive capacitive
loads of 100 pF or less. External buffers are nec-
essary for driving higher load capacitances. It
goes high whenever the number of conversion
results in the conversion FIFO equals a program-
mable value stored in the Interrupt Enable regis-
ter. It returns to a logic low when the FIFO is
empty.
Input for the active low WRITE bus control signal.
The data input/output TRI-STATE buffers, as se-
lected by the logic signal applied to the BW pin,
are enabled when WR and CS are both low. This
allows the LM12(H)454/8 to receive information
from the databus.
Input for the active low Chip Select control signal.
A logic low should be applied to this pin only dur-
GND
LM12(H)454/8 ground connection. It should be
connected to a low resistance and inductance
analog ground return that connects directly to the
system power supply ground.
ing
a
READ or WRITE access to the
LM12(H)454/8. The internal clocking is halted
and conversion stops while Chip Select is low.
Conversion resumes when the Chip Select input
signal returns high.
IN0–IN7
(IN0–IN3
The eight (LM12(H)458) or four (LM12454)
analog inputs. A given channel is selected
LM12H454 through the instruction RAM. Any of the chan-
LM12454) nels can be configured as an independent
single-ended input. Any pair of channels,
whether adjacent or non-adjacent, can operate
as a fully differential pair.
ALE
Address Latch Enable input. It is used in systems
containing a multiplexed databus. When ALE is
asserted high, the LM12(H)454/8 accepts infor-
mation on the databus as a valid address. A
high-to-low transition will latch the address data
on A0–A4 while the CS is low. Any changes on
A0–A4 and CS while ALE is low will not affect the
S/H IN+
S/H IN−
The LM12454’s non-inverting and inverting in-
puts to the internal S/H.
MUXOUT+ The LM12454’s non-inverting and inverting out-
MUXOUT− puts from the internal multiplexer.
LM12(H)454/8. See Figure 10. When
non-multiplexed bus is used, ALE is continuously
asserted high. See Figure 11.
a
VREF−
The
negative
reference
input.
The
LM12(H)454/8 operate with 0V
≤
VREF−
≤
CLK
External clock input pin. The LM12(H)454/8 oper-
ates with an input clock frequency in the range of
0.05 MHz to 10.0 MHz.
V
REF+. This pin should be bypassed to ground
with a parallel combination of 10 µF and 0.1 µF
(ceramic) capacitors.
A0–A4
SYNC
The LM12(H)454/8’s address lines. They are
used to access all internal registers, Conversion
FIFO, and Instruction RAM.
VREF+
The
positive
reference
input.
The
LM12(H)454/8 operate with 0V ≤ VREF+ ≤ VA+.
This pin should be bypassed to ground with a
parallel combination of 10 µF and 0.1 µF (ce-
ramic) capacitors.
Synchronization input/output. When used as an
output, it is designed to drive capacitive loads of
100 pF or less. External buffers are necessary for
driving higher load capacitances. SYNC is an in-
put if the Configuration register’s “I/O Select” bit
is low. A rising edge on this pin causes the inter-
VREFOUT
The internal 2.5V bandgap’s output pin. This
pin should be bypassed to ground with a 100
µF capacitor.
21
www.national.com
Application Information
1.0 Functional Description
The LM12454 and LM12(H)458 are multi-functional Data Ac-
The analog input multiplexer can be configured for any com-
bination of single-ended or fully differential operation. Each
input is referenced to ground when a multiplexer channel op-
erates in the single-ended mode. Fully differential analog in-
put channels are formed by pairing any two channels to-
gether.
quisition Systems that include
a
fully differential
12-bit-plus-sign self-calibrating analog-to-digital converter
(ADC) with a two’s-complement output format, an 8-channel
(LM12(H)458) or a 4-channel (LM12454) analog multiplexer,
an internal 2.5V reference, a first-in-first-out (FIFO) register
that can store 32 conversion results, and an Instruction RAM
that can store as many as eight instructions to be sequen-
tially executed. The LM12454 also has a differential multi-
plexer output and a differential S/H input. All of this circuitry
operates on only a single +5V power supply.
The LM12454’s multiplexer outputs and S/H inputs (MUX-
OUT+, MUXOUT− and S/H IN+, S/H IN−) provide the option
for additional analog signal processing. Fixed-gain amplifi-
ers, programmable-gain amplifiers, filters, and other pro-
cessing circuits can operate on the signal applied to the se-
lected multiplexer channel(s). If external processing is not
used, connect MUXOUT+ to S/H IN+ and MUXOUT− to
S/H IN−.
The LM12(H)454/8 have three modes of operation:
12-bit + sign with correction
8-bit + sign without correction
The LM12(H)454/8’s internal S/H is designed to operate at
its minimum acquisition time (1.13 µs, 12 bits) when the
source impedance, RS, is ≤ 60Ω (fCLK ≤ 8 MHz). When 60Ω
8-bit + sign comparison mode (“watchdog” mode)
The fully differential 12-bit-plus-sign ADC uses a charge re-
distribution topology that includes calibration capabilities.
Charge re-distribution ADCs use a capacitor ladder in place
of a resistor ladder to form an internal DAC. The DAC is used
by a successive approximation register to generate interme-
diate voltages between the voltages applied to VREF− and
<
R
S ≤ 4.17 kΩ, the internal S/H’s acquisition time can be in-
=
creased to a maximum of 4.88 µs (12 bits, fCLK 8 MHz).
See Section 2.1 (Instruction RAM “00”) Bits 12–15 for more
information.
An internal 2.5V bandgap reference output is available at pin
44. This voltage can be used as the ADC reference for ratio-
metric conversion or as a virtual ground for front-end analog
conditioning circuits. The VREFOUT pin should be bypassed
to ground with a 100 µF capacitor.
V
REF+. These intermediate voltages are compared against
the sampled analog input voltage as each bit is generated.
The number of intermediate voltages and comparisons
equals the ADC’s resolution. The correction of each bit’s ac-
curacy is accomplished by calibrating the capacitor ladder
used in the ADC.
Microprocessor overhead is reduced through the use of the
internal conversion FIFO. Thirty-two consecutive conver-
sions can be completed and stored in the FIFO without any
microprocessor intervention. The microprocessor can, at any
time, interrogate the FIFO and retrieve its contents. It can
also wait for the LM12(H)454/8 to issue an interrupt when
the FIFO is full or after any number (≤32) of conversions
have been stored.
Two different calibration modes are available; one compen-
sates for offset voltage, or zero error, while the other corrects
both offset error and the ADC’s linearity error.
When correcting offset only, the offset error is measured
once and a correction coefficient is created. During the full
calibration, the offset error is measured eight times, aver-
aged, and a correction coefficient is created. After comple-
tion of either calibration mode, the offset correction coeffi-
cient is stored in an internal offset correction register.
Conversion sequencing, internal timer interval, multiplexer
configuration, and many other operations are programmed
and set in the Instruction RAM.
The LM12(H)454/8’s overall linearity correction is achieved
by correcting the internal DAC’s capacitor mismatch. Each
capacitor is compared eight times against all remaining
smaller value capacitors and any errors are averaged. A cor-
rection coefficient is then created and stored in one of the
thirteen internal linearity correction registers. An internal
state machine, using patterns stored in an internal 16 x 8-bit
ROM, executes each calibration algorithm.
A diagnostic mode is available that allows verification of the
LM12(H)458’s operation. The diagnostic mode is disabled in
the LM12454. This mode internally connects the voltages
present at the VREFOUT, VREF+, VREF−, and GND pins to the
internal VIN+ and VIN− S/H inputs. This mode is activated by
setting the Diagnostic bit (Bit 11) in the Configuration register
to a “1”. More information concerning this mode of operation
can be found in Section 2.2.
Once calibrated, an internal arithmetic logic unit (ALU) uses
the offset correction coefficient and the 13 linearity correction
coefficients to reduce the conversion’s offset error and lin-
earity error, in the background, during the 12-bit + sign con-
version. The 8-bit + sign conversion and comparison modes
use only the offset coefficient. The 8-bit + sign mode per-
forms a conversion in less than half the time used by the
12-bit + sign conversion mode.
2.0 Internal User-Programmable
Registers
INSTRUCTION RAM
The instruction RAM holds up to eight sequentially execut-
able instructions. Each 48-bit long instruction is divided into
three 16-bit sections. READ and WRITE operations can be
issued to each 16-bit section using the instruction’s address
and the 2-bit “RAM pointer” in the Configuration register. The
eight instructions are located at addresses 0000 through
The LM12(H)454/8’s “watchdog” mode is used to monitor a
single-ended or differential signal’s amplitude. Each
sampled signal has two limits. An interrupt can be generated
if the input signal is above or below either of the two limits.
This allows interrupts to be generated when analog voltage
inputs are “inside the window” or, alternatively, “outside the
window”. After a “watchdog” mode interrupt, the processor
can then request a conversion on the input signal and read
the signal’s magnitude.
=
0111 (A4–A1, BW 0) when using a 16-bit wide data bus or
=
at addresses 00000 through 01111 (A4–A0, BW 1) when
using an 8-bit wide data bus. They can be accessed and pro-
grammed in random order.
www.national.com
22
non-inverting mode and the other operating in the inverting
mode. A code of “000” selects ground as the inverting input
for single ended operation.
2.0 Internal User-Programmable
Registers (Continued)
Bit 8 is the SYNC bit. Setting Bit 8 to “1” causes the Se-
quencer to suspend operation at the end of the internal S/H’s
acquisition cycle and to wait until a rising edge appears at
the SYNC pin. When a rising edge appears, the S/H ac-
quires the input signal magnitude and the ADC performs a
conversion on the clock’s next rising edge. When the SYNC
pin is used as an input, the Configuration register’s “I/O Se-
lect” bit (Bit 7) must be set to a “0”. With SYNC configured as
an input, it is possible to synchronize the start of a conver-
sion to an external event. This is useful in applications such
as digital signal processing (DSP) where the exact timing of
conversions is important.
Any Instruction RAM READ or WRITE can affect the se-
quencer’s operation:
The Sequencer should be stopped by setting the RESET
bit to a “1” or by resetting the START bit in the Configura-
tion Register and waiting for the current instruction to fin-
ish execution before any Instruction RAM READ or
WRITE is initiated.
A soft RESET should be issued by writing a “1” to the
Configuration Register’s RESET bit after any READ or
WRITE to the Instruction RAM.
The three sections in the Instruction RAM are selected by
the Configuration Register’s 2-bit “RAM Pointer”, bits D8 and
D9. The first 16-bit Instruction RAM section is selected with
the RAM Pointer equal to “00”. This section provides multi-
plexer channel selection, as well as resolution, acquisition
time, etc. The second 16-bit section holds “watchdog” limit
#1, its sign, and an indicator that shows that an interrupt can
be generated if the input signal is greater or less than the
programmed limit. The third 16-bit section holds “watchdog”
limit #2, its sign, and an indicator that shows that an interrupt
can be generated if the input signal is greater or less than the
programmed limit.
When the LM12(H)454/8 are used in the “watchdog” mode
with external synchronization, two rising edges on the SYNC
input are required to initiate two comparisons. The first rising
edge initiates the comparison of the selected analog input
signal with Limit #1 (found in Instruction RAM “01”) and the
second rising edge initiates the comparison of the same ana-
log input signal with Limit #2 (found in Instruction RAM “10”).
Bit 9 is the TIMER bit. When Bit 9 is set to “1”, the Se-
quencer will halt until the internal 16-bit Timer counts down
to zero. During this time interval, no “watchdog” comparisons
or analog-to-digital conversions will be performed.
Bit 10 selects the ADC conversion resolution. Setting Bit 10
to “1” selects 8-bit + sign and when reset to “0” selects 12-bit
+ sign.
Instruction RAM “00”
Bit 0 is the LOOP bit. It indicates the last instruction to be ex-
ecuted in any instruction sequence when it is set to a “1”.
The next instruction to be executed will be instruction 0.
Bit 11 is the “watchdog” comparison mode enable bit. When
operating in the “watchdog” comparison mode, the selected
analog input signal is compared with the programmable val-
ues stored in Limit #1 and Limit #2 (see Instruction RAM “01”
and Instruction RAM “10”). Setting Bit 11 to “1” causes two
comparisons of the selected analog input signal with the two
stored limits. When Bit 11 is reset to “0”, an 8-bit + sign or
12-bit + sign (depending on the state of Bit 10 of Instruction
RAM “00”) conversion of the input signal can take place.
Bit 1 is the PAUSE bit. This controls the Sequencer’s opera-
tion. When the PAUSE bit is set (“1”), the Sequencer will stop
after reading the current instruction and before executing it,
and the start bit in the Configuration register is automatically
reset to a “0”. Setting the PAUSE also causes an interrupt to
be issued. The Sequencer is restarted by placing a “1” in the
Configuration register’s Bit 0 (Start bit).
After the Instruction RAM has been programmed and the
RESET bit is set to “1”, the Sequencer retrieves Instruction
000, decodes it, and waits for a “1” to be placed in the Con-
figuration’s START bit. The START bit value of “0” “over-
rides” the action of Instruction 000’s PAUSE bit when the Se-
quencer is started. Once started, the Sequencer executes
Instruction 000 and retrieves, decodes, and executes each
of the remaining instructions. No PAUSE Interrupt (INT 5) is
generated the first time the Sequencer executes Instruction
000 having a PAUSE bit set to “1”. When the Sequencer en-
counters a LOOP bit or completes all eight instructions, In-
struction 000 is retrieved and decoded. A set PAUSE bit in
Instruction 000 now halts the Sequencer before the instruc-
tion is executed.
Bits 2–4 select which of the eight input channels (“000” to
“111” for IN0–IN7) will be configured as non-inverting inputs
to the LM12(H)458’s ADC. (See Page 27, Table 1.) They se-
lect which of the four input channels (“000” to “011” for
IN0–IN4) will be configured as non-inverting inputs to the
LM12454’s ADC. (See Page 27, Table 2.)
Bits 5–7 select which of the seven input channels (“001” to
“111” for IN1 to IN7) will be configured as inverting inputs to
the LM12(H)458’s ADC. (See Page 27, Table 1.) They select
which of the three input channels (“001” to “011” for IN1–IN4)
will be configured as inverting inputs to the LM12454’s ADC.
(See Page 27, Table 2.) Fully differential operation is created
by selecting two multiplexer channels, one operating in the
23
www.national.com
2.0 Internal User-Programmable Registers (Continued)
2
bale
T
www.national.com
24
2.0 Internal User-Programmable Registers (Continued)
A4
A3
A2
0
A1
A0
Purpose
Type
D7
D6
D5
D4
D3
D2
D1
D0
0
0
R/W
VIN−
VIN+
(MUXOUT−) (Note 22)
(MUXOUT+) (Note 22)
0
to
1
0
Pause
Loop
Instruction
RAM
1
0
1
0
(RAM
Pointer
00)
0
R/W
R/W
R/W
R/W
R/W
Watch-
=
0
0
0
0
to
1
1
0
1
0
Acquisition Time
dog
8/12
Timer
Sync
1
0
1
0
0
to
1
Comparison Limit #1
Instruction
RAM
1
0
1
0
(RAM
Pointer
01)
0
=
> <
/
to
1
Don’t Care
Sign
1
0
1
0
0
to
1
Comparison Limit #2
Instruction
RAM
1
0
1
0
(RAM
Pointer
10)
0
=
> <
/
0
1
1
to
1
1
0
1
Don’t Care
Sign
Start
1
0
1
0
0
R/W
R/W
I/O
Sel
Auto
Chan
Stand-
by
Full
Cal
Auto-
Zero
Reset
Zeroec
Mask
INT5
Configuration
Register
0
0
0
DIAG
(Note
23)
=
Test
0
Don’t Care
RAM Pointer
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
R/W
R/W
R
INT7
INT6
INT4
INT3
INT2
INT1
INT0
Interrupt
Enable
Register
Number of Conversions in Conversion
FIFO to Generate INT2
Sequencer Address to
Generate INT1
INST7
INST6
INST5
INST4
INST3
INST2
INST1
INST0
Interrupt
Status
Register
R
Actual Number of Conversions Results
in Conversion FIFO
Address of Sequencer
Instruction
being Executed
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
R/W
R/W
R
Timer Preset: Low Byte
Timer Preset: High Byte
Conversion Data: LSBs
Sign
Timer
Register
Conversion
FIFO
R
Address or Sign
Conversion Data: MSBs
R
Limit #1 Status
Limit Status
Register
R
Limit #2 Status
=
=
FIGURE 14. LM12(H)454/8 Memory Map for 8-Bit Wide Databus (BW “1” and Test Bit “0”)
Note 22: LM12454 (Refer toTable 2).
Note 23: LM12(H)458 only. Must be set to “0” for the LM12454.
25
www.national.com
Bit 9 ’s state determines the limit condition that generates a
“watchdog” interrupt. A “1” causes a voltage greater than
limit #2 to generate an interrupt, while a “0” causes a voltage
less than limit #2 to generate an interrupt.
2.0 Internal User-Programmable
Registers (Continued)
Bits 12–15 are used to store the user-programmable acqui-
sition time. The Sequencer keeps the internal S/H in the ac-
quisition mode for a fixed number of clock cycles (nine clock
cycles, for 12-bit + sign conversions and two clock cycles for
8-bit + sign conversions or “watchdog” comparisons) plus a
variable number of clock cycles equal to twice the value
stored in Bits 12–15. Thus, the S/H’s acquisition time is (9 +
2D) clock cycles for 12-bit + sign conversions and (2 + 2D)
clock cycles for 8-bit + sign conversions or “watchdog” com-
parisons, where D is the value stored in Bits 12–15. The
minimum acquisition time compensates for the typical inter-
nal multiplexer series resistance of 2 kΩ, and any additional
delay created by Bits 12–15 compensates for source resis-
tances greater than 60Ω (100Ω). (For this acquisition time
discussion, numbers in ( ) are shown for the LM12(H)454/8
operating at 5 MHz.) The necessary acquisition time is deter-
mined by the source impedance at the multiplexer input. If
Bits 10–15 are not used.
2.2 CONFIGURATION REGISTER
=
The Configuration register, 1000 (A4–A1, BW 0) or 1000x
=
(A4–A0, BW 1) is a 16-bit control register with read/write
capability. It acts as the LM12454’s and LM12(H)458’s “con-
trol panel” holding global information as well as start/stop, re-
set, self-calibration, and stand-by commands.
Bit 0 is the START/STOP bit. Reading Bit 0 returns an indi-
cation of the Sequencer’s status. A “0” indicates that the Se-
quencer is stopped and waiting to execute the next instruc-
tion. A “1” shows that the Sequencer is running. Writing a “0”
halts the Sequencer when the current instruction has fin-
ished execution. The next instruction to be executed is
pointed to by the instruction pointer found in the status reg-
ister. A “1” restarts the Sequencer with the instruction cur-
rently pointed to by the instruction pointer. (See Bits 8–10 in
the Interrupt Status register.)
<
the source resistance (RS) 60Ω (100Ω) and the clock fre-
quency is 8 MHz, the value stored in bits 12–15 (D) can be
>
0000. If RS 60Ω (100Ω), the following equations determine
Bit 1 is the LM12(H)454/8’s system RESET bit. Writing a “1”
to Bit 1 stops the Sequencer (resetting the Configuration reg-
ister’s START/STOP bit), resets the Instruction pointer to
“000” (found in the Interrupt Status register), clears the Con-
version FIFO, and resets all interrupt flags. The RESET bit
will return to “0” after two clock cycles unless it is forced high
by writing a “1” into the Configuration register’s Standby bit.
A reset signal is internally generated when power is first ap-
plied to the part. No operation should be started until the RE-
SET bit is “0”.
the value that should be stored in bits 12–15.
=
D
D
0.45 x RS x fCLK
0.36 x RS x fCLK
for 12-bits + sign
=
for 8-bits + sign and “watchdog”
RS is in kΩ and fCLK is in MHz. Round the result to the next
higher integer value. If D is greater than 15, it is advisable to
lower the source impedance by using an analog buffer be-
tween the signal source and the LM12(H)458’s multiplexer
inputs. The value of D can also be used to compensate for
the settling or response time of external processing circuits
connected between the LM12454’s MUXOUT and S/H IN
pins.
Writing a “1” to Bit 2 initiates an auto-zero offset voltage cali-
bration. Unlike the eight-sample auto-zero calibration per-
formed during the full calibration procedure, Bit 2 initiates a
“short” auto-zero by sampling the offset once and creating a
correction coefficient (full calibration averages eight samples
of the converter offset voltage when creating a correction co-
efficient). If the Sequencer is running when Bit 2 is set to “1”,
an auto-zero starts immediately after the conclusion of the
currently running instruction. Bit 2 is reset automatically to a
“0” and an interrupt flag (Bit 3, in the Interrupt Status register)
is set at the end of the auto-zero (76 clock cycles). After
completion of an auto-zero calibration, the Sequencer
fetches the next instruction as pointed to by the Instruction
RAM’s pointer and resumes execution. If the Sequencer is
stopped, an auto-zero is performed immediately at the time
requested.
Instruction RAM “01”
The second Instruction RAM section is selected by placing a
“01” in Bits 8 and 9 of the Configuration register.
Bits 0–7 hold “watchdog” limit #1. When Bit 11 of Instruction
RAM “00” is set to a “1”, the LM12(H)454/8 performs a
“watchdog” comparison of the sampled analog input signal
with the limit #1 value first, followed by a comparison of the
same sampled analog input signal with the value found in
limit #2 (Instruction RAM “10”).
Bit 8 holds limit #1’s sign.
Writing a “1” to Bit 3 initiates a complete calibration process
that includes a “long” auto-zero offset voltage correction (this
calibration averages eight samples of the comparator offset
voltage when creating a correction coefficient) followed by
an ADC linearity calibration. This complete calibration is
started after the currently running instruction is completed if
the Sequencer is running when Bit 3 is set to “1”. Bit 3 is re-
set automatically to a “0” and an interrupt flag (Bit 4, in the In-
terrupt Status register) will be generated at the end of the
calibration procedure (4944 clock cycles). After completion
of a full auto-zero and linearity calibration, the Sequencer
fetches the next instruction as pointed to by the Instruction
RAM’s pointer and resumes execution. If the Sequencer is
stopped, a full calibration is performed immediately at the
time requested.
Bit 9’s state determines the limit condition that generates a
“watchdog” interrupt. A “1” causes a voltage greater than
limit #1 to generate an interrupt, while a “0” causes a voltage
less than limit #1 to generate an interrupt.
Bits 10–15 are not used.
Instruction RAM “10”
The third Instruction RAM section is selected by placing a
“10” in Bits 8 and 9 of the Configuration register.
Bits 0–7 hold “watchdog” limit #2. When Bit 11 of Instruction
RAM “00” is set to a “1”, the LM12(H)454/8 performs a
“watchdog” comparison of the sampled analog input signal
with the limit #1 value first (Instruction RAM “01”), followed
by a comparison of the same sampled analog input signal
with the value found in limit #2.
Bit 4 is the Standby bit. Writing a “1” to Bit 4 immediately
places the LM12(H)454/8 in Standby mode. Normal opera-
tion returns when Bit 4 is reset to a “0”. The Standby com-
Bit 8 holds limit #2’s sign.
www.national.com
26
they are not masked (by the Interrupt Enable register). The
Interrupt Status register is then read to determine which of
the eight interrupts has been issued.
2.0 Internal User-Programmable
Registers (Continued)
mand (“1”) disconnects the external clock from the internal
circuitry, decreases the LM12(H)454/8’s internal analog cir-
cuitry power supply current, and preserves all internal RAM
TABLE 1. LM12(H)458 Input Multiplexer
Channel Configuration Showing Normal
Mode and Diagnostic Mode
contents. After writing
a “0” to the Standby bit, the
LM12(H)454/8 returns to an operating state identical to that
caused by exercising the RESET bit. A Standby completion
interrupt is issued after a power-up completion delay that al-
lows the analog circuitry to settle. The Sequencer should be
restarted only after the Standby completion is issued. The In-
struction RAM can still be accessed through read and write
operations while the LM12(H)454/8 are in Standby Mode.
Channel
Selection
Data
Normal
Mode
Diagnostic
Mode
VIN+
VIN−
GND
IN1
IN2
IN3
IN4
IN5
IN6
IN7
VIN+
VIN−
GND
VREF−
IN2
000
001
010
011
100
101
110
111
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
VREFOUT
VREF+
IN2
Bit 5 is the Channel Address Mask. If Bit 5 is set to a “1”, Bits
13–15 in the conversion FIFO will be equal to the sign bit (Bit
12) of the conversion data. Resetting Bit 5 to a “0” causes
conversion data Bits 13 through 15 to hold the instruction
pointer value of the instruction to which the conversion data
belongs.
IN3
IN3
IN4
IN4
IN5
IN5
IN6
IN6
Bit 6 is used to select a “short” auto-zero correction for every
conversion. The Sequencer automatically inserts an
auto-zero before every conversion or “watchdog” compari-
son if Bit 6 is set to “1”. No automatic correction will be per-
formed if Bit 6 is reset to “0”.
IN7
IN7
TABLE 2. LM12454 Input Multiplexer
Channel Configuration
The LM12(H)454/8’s offset voltage, after calibration, has a
typical drift of 0.1 LSB over a temperature range of −40˚C to
+85˚C. This small drift is less than the variability of the
change in offset that can occur when using the auto-zero
correction with each conversion. This variability is the result
of using only one sample of the offset voltage to create a cor-
rection value. This variability decreases when using the full
calibration mode because eight samples of the offset voltage
are taken, averaged, and used to create a correction value.
Channel
Selection
Data
000
MUX+
MUX−
IN0
IN1
GND
IN1
001
010
IN2
IN2
011
IN3
IN3
1XX
OPEN
OPEN
Bit 7 is used to program the SYNC pin (29) to operate as ei-
ther an input or an output. The SYNC pin becomes an output
when Bit 7 is a “1” and an input when Bit 7 is a “0”. With
SYNC programmed as an input, the rising edge of any logic
signal applied to pin 29 will start a conversion or “watchdog”
comparison. Programmed as an output, the logic level at pin
29 will go high at the start of a conversion or “watchdog”
comparison and remain high until either have finished. See
Instruction RAM “00”, Bit 8.
=
The Interrupt Status register, 1010 (A4–A1, BW
0) or
=
1010x (A4–A0, BW 1) must be cleared by reading it after
writing to the Interrupt Enable register. This removes any
spurious interrupts on the INT pin generated during an Inter-
rupt Enable register access.
Interrupt 0 is generated whenever the analog input voltage
on a selected multiplexer channel crosses a limit while the
LM12(H)454/8 are operating in the “watchdog” comparison
mode. Two sequential comparisons are made when the
LM12(H)454/8 are executing a “watchdog” instruction. De-
pending on the logic state of Bit 9 in the Instruction RAM’s
second and third sections, an interrupt will be generated ei-
ther when the input signal’s magnitude is greater than or less
than the programmable limits. (See the Instruction RAM, Bit
9 description.) The Limit Status register will indicate which
preprogrammed limit, #1 or #2 and which instruction was ex-
ecuting when the limit was crossed.
Bits 8 and 9 form the RAM Pointer that is used to select
each of a 48-bit instruction’s three 16-bit sections during
read or write actions. A “00” selects Instruction RAM section
one, “01” selects section two, and “10” selects section three.
Bit 10 activates the Test mode that is used only during pro-
duction testing. Leave this bit reset to “0”.
Bit 11 is the Diagnostic bit and is available only in the
LM12(H)458. It can be activated by setting it to a “1” (the Test
bit must be reset to a “0”). The Diagnostic mode, along with
a correctly chosen instruction, allows verification that the
LM12(H)458’s ADC is performing correctly. When activated,
the inverting and non-inverting inputs are connected as
shown in Table I. As an example, an instruction with “001” for
both VIN+ and VIN− while using the Diagnostic mode typically
results in a full-scale output.
Interrupt 1 is generated when the Sequencer reaches the
instruction counter value specified in the Interrupt Enable
register’s bits 8–10. This flag appears before the instruc-
tion’s execution.
Interrupt 2 is activated when the Conversion FIFO holds a
number of conversions equal to the programmable value
stored in the Interrupt Enable register’s Bits 11–15. This
value ranges from 0001 to 1111, representing 1 to 31 conver-
sions stored in the FIFO. A user-programmed value of 0000
has no meaning. See Section 3.0 for more FIFO information.
2.3 INTERRUPTS
The LM12454 and LM12(H)458 have eight possible inter-
rupts, all with the same priority. Any of these interrupts will
cause a hardware interrupt to appear on the INT pin (31) if
The completion of the short, single-sampled auto-zero cali-
bration generates Interrupt 3.
27
www.national.com
member that the Sequencer continues to operate even if an
Instruction interrupt (INT 1) is internally or externally gener-
ated. The only mechanisms that stop the Sequencer are an
instruction with the PAUSE bit set to “1” (halts before instruc-
tion execution), placing a “0” in the Configuration register’s
START bit, or placing a “1” in the Configuration register’s RE-
SET bit.
2.0 Internal User-Programmable
Registers (Continued)
The completion of
a
full auto-zero and linearity
self-calibration generates Interrupt 4.
Interrupt 5 is generated when the Sequencer encounters an
instruction that has its Pause bit (Bit 1 in Instruction RAM
“00”) set to “1”.
Bits 11–15 hold the number of conversions that must be
stored in the Conversion FIFO in order to generate an inter-
nal interrupt. This internal interrupt appears in Bit 2 of the In-
terrupt Status register. If Bit 2 of the Interrupt Enable register
is set to “1”, an external interrupt will appear at pin 31 (INT).
The LM12(H)454/8 issues Interrupt 6 whenever it senses
that its power supply voltage is dropping below 4V (typ). This
interrupt indicates the potential corruption of data returned
by the LM12(H)454/8.
Interrupt 7 is issued after a short delay (10 ms typ) while the
LM12(H)454/8 returns from Standby mode to active opera-
tion using the Configuration register’s Bit 4. This short delay
allows the internal analog circuitry to settle sufficiently, en-
suring accurate conversion results.
2.5 INTERRUPT STATUS REGISTER
This read-only register is located at address 1010 (A4–A1,
=
=
BW 0) or 1010x (A4–A0, BW 1). The corresponding flag
in the Interrupt Status register goes high (“1”) any time that
an interrupt condition takes place, whether an interrupt is en-
abled or disabled in the Interrupt Enable register. Any of the
active (“1”) Interrupt Status register flags are reset to “0”
whenever this register is read or a device reset is issued
(see Bit 1 in the Configuration Register).
2.4 INTERRUPT ENABLE REGISTER
The Interrupt Enable register at address location 1001
=
=
(A4–A1, BW
0) or 1001x (A4–A0, BW
1) has READ/
WRITE capability. An individual interrupt’s ability to produce
an external interrupt at pin 31 (INT) is accomplished by plac-
ing a “1” in the appropriate bit location. Any of the internal
interrupt-producing operations will set their corresponding
bits to “1” in the Interrupt Status register regardless of the
state of the associated bit in the Interrupt Enable register.
See Section 2.3 for more information about each of the eight
internal interrupts.
Bit 0 is set to “1” when a “watchdog” comparison limit inter-
rupt has taken place.
Bit 1 is set to “1” when the Sequencer has reached the ad-
dress stored in Bits 8–10 of the Interrupt Enable register.
Bit 2 is set to “1” when the Conversion FIFO’s limit, stored in
Bits 11–15 of the Interrupt Enable register, has been
reached.
Bit 3 is set to “1” when the single-sampled auto-zero has
been completed.
Bit 0 enables an external interrupt when an internal “watch-
dog” comparison limit interrupt has taken place.
Bit 4 is set to “1” when an auto-zero and full linearity
self-calibration has been completed.
Bit 1 enables an external interrupt when the Sequencer has
reached the address stored in Bits 8–10 of the Interrupt En-
able register.
Bit 5 is set to “1” when a Pause interrupt has been gener-
ated.
Bit 2 enables an external interrupt when the Conversion
FIFO’s limit, stored in Bits 11–15 of the Interrupt Enable reg-
ister, has been reached.
Bit 6 is set to “1” when a low-supply voltage condition
<
(VA
+
4V) has taken place.
Bit 3 enables an external interrupt when the single-sampled
Bit 7 is set to “1” when the LM12(H)454/8 return from
auto-zero calibration has been completed.
power-down to active mode.
Bit 4 enables an external interrupt when a full auto-zero and
Bits 8–10 hold the Sequencer’s actual instruction address
linearity self-calibration has been completed.
while it is running.
Bit 5 enables an external interrupt when an internal Pause
Bits 11–15 hold the actual number of conversions stored in
interrupt has been generated.
the Conversion FIFO while the Sequencer is running.
Bit 6 enables an external interrupt when a low power supply
2.6 LIMIT STATUS REGISTER
<
condition (VA+ 4V) has generated an internal interrupt.
The read-only register is located at address 1101 (A4–A1,
Bit 7 enables an external interrupt when the LM12(H)454/8
return from power-down to active mode.
=
=
BW 0) or 1101x (A4–A0, BW 1). This register is used in
tandem with the Limit #1 and Limit #2 registers in the Instruc-
tion RAM. Whenever a given instruction’s input voltage ex-
ceeds the limit set in its corresponding Limit register (#1 or
#2), a bit, corresponding to the instruction number, is set in
the Limit Status register. Any of the active (“1”) Limit Status
flags are reset to “0” whenever this register is read or a de-
vice reset is issued (see Bit 1 in the Configuration register).
This register holds the status of limits #1 and #2 for each of
the eight instructions.
Bits 8–10 form the storage location of the
user-programmable value against which the Sequencer’s
address is compared. When the Sequencer reaches an ad-
dress that is equal to the value stored in Bits 8–10, an inter-
nal interrupt is generated and appears in Bit 1 of the Interrupt
Status register. If Bit 1 of the Interrupt Enable register is set
to “1”, an external interrupt will appear at pin 31 (INT).
The value stored in bits 8–10 ranges from 000 to 111, repre-
senting 0 to 7 instructions stored in the Instruction RAM. Af-
ter the Instruction RAM has been programmed and the RE-
SET bit is set to “1”, the Sequencer is started by placing a “1”
in the Configuration register’s START bit. Setting the INT 1
trigger value to 000 does not generate an INT 1 the first
time the Sequencer retrieves and decodes Instruction 000.
The Sequencer generates INT 1 (by placing a “1” in the In-
terrupt Status register’s Bit 1) the second time and after the
Sequencer encounters Instruction 000. It is important to re-
Bits 0–7 show the Limit #1 status. Each bit will be set high
(“1”) when the corresponding instruction’s input voltage ex-
ceeds the threshold stored in the instruction’s Limit #1 regis-
ter. When, for example, instruction 3 is a “watchdog” opera-
tion (Bit 11 is set high) and the input for instruction 3 meets
the magnitude and/or polarity data stored in instruction 3’s
Limit #1 register, Bit 3 in the Limit Status register will be set
to a “1”.
www.national.com
28
that generated the conversion and the resulting data. These
modes are selected according to the logic state of the Con-
figuration register’s Bit 5.
2.0 Internal User-Programmable
Registers (Continued)
The FIFO status should be read in the Interrupt Status regis-
ter (Bits 11–15) to determine the number of conversion re-
sults that are held in the FIFO before retrieving them. This
will help prevent conversion data corruption that may take
place if the number of reads are greater than the number of
conversion results contained in the FIFO. Trying to read the
FIFO when it is empty may corrupt new data being written
into the FIFO. Writing more than 32 conversion data into the
FIFO by the ADC results in loss of the first conversion data.
Therefore, to prevent data loss, it is recommended that the
LM12(H)454/8’s interrupt capability be used to inform the
system controller that the FIFO is full.
Bits 8–15 show the Limit #2 status. Each bit will be set high
(“1”) when the corresponding instruction’s input voltage ex-
ceeds the threshold stored in the instruction’s Limit #2 regis-
ter. When, for example, the input to instruction 6 meets the
value stored in instruction 6’s Limit #2 register, Bit 14 in the
Limit Status register will be set to a “1”.
2.7 TIMER
The LM12(H)454/8 have an on-board 16-bit timer that in-
cludes a 5-bit pre-scaler. It uses the clock signal applied to
pin 23 as its input. It can generate time intervals of 0 through
221 clock cycles in steps of 25. This time interval can be used
to delay the execution of instructions. It can also be used to
slow the conversion rate when converting slowly changing
signals. This can reduce the amount of redundant data
stored in the FIFO and retrieved by the controller.
=
The lower portion (A0 0) of the data word (Bits 0–7) should
=
be read first followed by a read of the upper portion (A0 1)
=
when using the 8-bit bus width (BW 1). Reading the upper
portion first causes the data to shift down, which results in
loss of the lower byte.
The user-defined timing value used by the Timer is stored in
the 16-bit READ/WRITE Timer register at location 1011
Bits 0–12 hold 12-bit + sign conversion data. Bits 0–3 will
be 1110 (LSB) when using 8-bit plus sign resolution.
=
=
(A4–A1, BW
0) or 1011x (A4–A0, BW
1) and is
pre-loaded automatically. Bits 0–7 hold the preset value’s
low byte and Bits 8–15 hold the high byte. The Timer is ac-
tivated by the Sequencer only if the current instruction’s Bit 9
Bits 13–15 hold either the instruction responsible for the as-
sociated conversion data or the sign bit. Either mode is se-
lected with Bit 5 in the Configuration register.
is set (“1”). If the equivalent decimal value “N” (0 ≤ N ≤ 216
−
Using the FIFO’s full depth is achieved as follows. Set the
value of the Interrupt Enable register’s Bits 11–15 to 11111
and the Interrupt Enable register’s Bit 2 to a “1”. This gener-
ates an external interrupt when the 31st conversion is stored
in the FIFO. This gives the host processor a chance to send
a “0” to the LM12(H)454/8’s Start bit (Configuration register)
and halt the ADC before it completes the 32nd conversion.
The Sequencer halts after the current (32) conversion is
completed. The conversion data is then transferred to the
FIFO and occupies the 32nd location. FIFO overflow is
avoided if the Sequencer is halted before the start of the
32nd conversion by placing a “0” in the Start bit (Configura-
tion register). It is important to remember that the Sequencer
continues to operate even if a FIFO interrupt (INT 2) is in-
ternally or externally generated. The only mechanisms
that stop the Sequencer are an instruction with the PAUSE
bit set to “1” (halts before instruction execution), placing a “0”
in the Configuration register’s START bit, or placing a “1” in
the Configuration register’s RESET bit.
1) is written inside the 16-bit Timer register and the Timer is
enabled by setting an instruction’s bit 9 to a “1”, the Se-
quencer will delay the same instruction’s execution by halt-
ing at state 3 (S3), as shown in Figure 15, for 32 x N + 2
clock cycles.
2.8 DMA
The DMA works in tandem with Interrupt 2. An active DMA
Request on pin 32 (DMARQ) requires that the FIFO interrupt
be enabled. The voltage on the DMARQ pin goes high when
the number of conversions in the FIFO equals the 5-bit value
stored in the Interrupt Enable register (bits 11–15). The volt-
age on the INT pin goes low at the same time as the voltage
on the DMARQ pin goes high. The voltage on the DMARQ
pin goes low when the FIFO is emptied. The Interrupt Status
register must be read to clear the FIFO interrupt flag in order
to enable the next DMA request.
DMA operation is optimized through the use of the 16-bit
databus connection (a logic “0” applied to the BW pin). Using
this bus width allows DMA controllers that have single ad-
dress Read/Write capability to easily unload the FIFO. Using
DMA on an 8-bit databus is more difficult. Two read opera-
tions (low byte, high byte) are needed to retrieve each con-
version result from the FIFO. Therefore, the DMA controller
must be able to repeatedly access two constant addresses
when transferring data from the LM12(H)454/8 to the host
system.
3.0 FIFO
The result of each conversion stored in an internal read-only
FIFO (First-In, First-Out) register. It is located at 1100
=
=
(A4–A1, BW 0) or 1100x (A4–A0, BW 1). This register
has 32 16-bit wide locations. Each location holds 13-bit data.
Bits 0–3 hold the four LSB’s in the 12 bits + sign mode or
“1110” in the 8 bits + sign mode. Bits 4–11 hold the eight
MSB’s and Bit 12 holds the sign bit. Bits 13–15 can hold ei-
ther the sign bit, extending the register’s two’s complement
data format to a full sixteen bits or the instruction address
29
www.national.com
4.0 Sequencer
The Sequencer uses a 3-bit counter (Instruction Pointer, or
IP, in Figure 9) to retrieve the programmable conversion in-
structions stored in the Instruction RAM. The 3-bit counter is
reset to 000 during chip reset or if the current executed in-
struction has its Loop bit (Bit 1 in any Instruction RAM “00”)
set high (“1”). It increments at the end of the currently ex-
ecuted instruction and points to the next instruction. It will
continue to increment up to 111 unless an instruction’s Loop
bit is set. If this bit is set, the counter resets to “000” and ex-
ecution begins again with the first instruction. If all instruc-
tions have their Loop bit reset to “0”, the Sequencer will ex-
ecute all eight instructions continuously. Therefore, it is
important to realize that if less than eight instructions are
programmed, the Loop bit on the last instruction must be set.
Leaving this bit reset to “0” allows the Sequencer to execute
“unprogrammed” instructions, the results of which may be
unpredictable.
State 3: Run the internal 16-bit Timer. The number of
clock cycles for this state varies according to the value
stored in the Timer register. The number of clock cycles is
found by using the expression below
32T + 2
where 0 ≤ T ≤ 216 −1.
State 7: Run the acquisition delay and read Limit #1’s
value if needed. The number of clock cycles for 12-bit + sign
mode varies according to
9 + 2D
where D is the user-programmable 4-bit value stored in bits
12–15 of Instruction RAM “00” and is limited to 0 ≤ D ≤ 15.
The number of clock cycles for 8-bit + sign or “watchdog”
mode varies according to
2 + 2D
where D is the user-programmable 4-bit value stored in bits
12–15 of Instruction RAM “00” and is limited to 0 ≤ D ≤ 15.
The Sequencer’s Instruction Pointer value is readable at any
time and is found in the Status register at Bits 8–10. The Se-
quencer can go through eight states during instruction ex-
ecution:
State 6: Perform first comparison. This state is 5 clock
cycles long.
State 4: Read Limit #2. This state is 1 clock cycle long.
State 0: The current instruction’s first 16 bits are read from
the Instruction RAM “00”. This state is one clock cycle long.
State 5: Perform a conversion or second comparison. This
state takes 44 clock cycles when using the 12-bit + sign
mode or 21 clock cycles when using the 8-bit + sign mode.
The “watchdog” mode takes 5 clock cycles.
State 1: Checks the state of the Calibration and Start bits.
This is the “rest” state whenever the Sequencer is stopped
using the reset, a Pause command, or the Start bit is reset
low (“0”). When the Start bit is set to a “1”, this state is one
clock cycle long.
State 2: Perform calibration. If bit 2 or bit 6 of the Configu-
ration register is set to a “1”, state 2 is 76 clock cycles long.
If the Configuration register’s bit 3 is set to a “1”, state 2 is
4944 clock cycles long.
www.national.com
30
4.0 Sequencer (Continued)
DS011264-19
=
FIGURE 15. Sequencer Logic Flow Chart (IP Instruction Pointer)
31
www.national.com
5.0 Analog Considerations
5.1 REFERENCE VOLTAGE
can be increased. As an example, operating with a 5 MHz
clock frequency and maximum acquisition time, the
LM12(H)454/8’s analog inputs can handle source imped-
ance as high as 6.67 kΩ. When operating at 8 MHz and
maximum acquisition time, the LM12H454/8’s analog inputs
can handle source impedance as high as 4.17 kΩ. Refer to
Section 2.1, Instruction RAM “00”, Bits 12–15 for further in-
formation.
The difference in the voltages applied to the VREF+ and
VREF− defines the analog input voltage span (the difference
between the voltages applied between two multiplexer inputs
or the voltage applied to one of the multiplexer inputs and
analog ground), over which 4095 positive and 4096 negative
codes exist. The voltage sources driving VREF+ or VREF−
must have very low output impedance and noise.
The ADC can be used in either ratiometric or absolute refer-
ence applications. In ratiometric systems, the analog input
voltage is proportional to the voltage used for the ADC’s ref-
erence voltage. When this voltage is the system power sup-
ply, the VREF+ pin is connected to VA+ and VREF− is con-
nected to GND. This technique relaxes the system reference
stability requirements because the analog input voltage and
the ADC reference voltage move together. This maintains
the same output code for given input conditions.
5.5 INPUT BYPASS CAPACITANCE
External capacitors (0.01 µF–0.1 µF) can be connected be-
tween the analog input pins, IN0–IN7, and analog ground to
filter any noise caused by inductive pickup associated with
long input leads. It will not degrade the conversion accuracy.
5.6 NOISE
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion er-
rors. Input filtering can be used to reduce the effects of the
noise sources.
For absolute accuracy, where the analog input voltage varies
between very specific voltage limits, a time and temperature
stable voltage source can be connected to the reference in-
puts. Typically, the reference voltage’s magnitude will require
an initial adjustment to null reference voltage induced
full-scale errors.
5.7 POWER SUPPLIES
Noise spikes on the VA+ and VD+ supply lines can cause
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. Low in-
ductance tantalum capacitors of 10 µF or greater paralleled
with 0.1 µF monolithic ceramic capacitors are recommended
for supply bypassing. Separate bypass capacitors should be
used for the VA+ and VD+ supplies and placed as close as
possible to these pins.
When using the LM12(H)454/8’s internal 2.5V bandgap ref-
erence, a parallel combination of a 100 µF capacitor and a
0.1 µF capacitor connected to the VREFOUT pin is recom-
mended for low noise operation. When left unconnected, the
reference remains stable without a bypass capacitor. How-
ever, ensure that stray capacitance at the VREFOUT pin re-
mains below 50 pF.
5.2 INPUT RANGE
The LM12(H)454/8’s fully differential ADC and reference
voltage inputs generate a two’s-complement output that is
found by using the equation below.
5.8 GROUNDING
The LM12(H)454/8’s nominal high resolution performance
can be maximized through proper grounding techniques.
These include the use of separate analog and digital ground
planes. The digital ground plane is placed under all compo-
nents that handle digital signals, while the analog ground
plane is placed under all analog signal handling circuitry. The
digital and analog ground planes are connected at only one
point, the power supply ground. This greatly reduces the oc-
currence of ground loops and noise.
Round up to the next integer value between −4096 to 4095
for 12-bit resolution and between −256 to 255 for 8-bit reso-
lution if the result of the above equation is not a whole num-
It is recommended that stray capacitance between the ana-
log inputs or outputs (LM12(H)454: IN0–IN3, MUXOUT+,
MUXOUT−, S/H IN+, S/H IN−; LM12(H)458: IN0–IN7,
=
=
=
ber. As an example, VREF+ 2.5V, VREF− 1V, VIN+ 1.5V
=
and VIN− GND. The 12-bit + sign output code is positive
V
REF+, and VREF−) be reduced by increasing the clearance
=
=
full-scale, or 0,1111,1111,1111. If VREF+ 5V, VREF− 1V,
(+1/16th inch) between the analog signal and reference pins
and the ground plane.
=
=
VIN+ 3V, and VIN− GND, the 12-bit + sign output code is
0,1100,0000,0000.
5.9 CLOCK SIGNAL LINE ISOLATION
5.3 INPUT CURRENT
The LM12(H)454/8’s performance is optimized by routing the
analog input/output and reference signal conductors (pins
34–44) as far as possible from the conductor that carries the
clock signal to pin 23. Ground traces parallel to the clock sig-
nal trace can be used on printed circuit boards to reduce
clock signal interference on the analog input/output pins.
A charging current flows into or out of (depending on the in-
put voltage polarity) the analog input pins, IN0–IN7 at the
start of the analog input acquisition time (tACQ). This cur-
rent’s peak value will depend on the actual input voltage ap-
plied.
5.4 INPUT SOURCE RESISTANCE
6.0 Application Circuits
<
For low impedance voltage sources ( 100Ω for 5 MHz op-
<
eration and 60Ω for 8 MHz operation), the input charging
PC EVALUATION/INTERFACE BOARD
current will decay, before the end of the S/H’s acquisition
time, to a value that will not introduce any conversion errors.
For higher source impedances, the S/H’s acquisition time
Figure 16 is the schematic of an evaluation/interface board
designed to interface the LM12(H)454 or LM12(H)458 with
an XT or AT® style computer. The board can be used to de-
www.national.com
32
TABLE 3. LM12(H)454/8 Evaluation/Interface
Board SW DIP-8 Switch Settings
6.0 Application Circuits (Continued)
velop both software and hardware. The board hardwires the
BW (Bus Width) pin to a logic high, selecting an 8-bit wide
databus. Therefore, it is designed for an 8-bit expansion slot
on the computer’s motherboard.
for Available I/O Memory Locations
Hexidecimal
I/O Memory
SW DIP-8
The circuit operates on a single +5V supply derived from the
computer’s +12V supply using an LM340 regulator. This
greatly attenuates noise that may be present on the comput-
er’s power supply lines. However, your application may only
need an LC filter.
Base Address
SW1
SW2
SW3
SW4
(SEL0) (SEL1) (SEL2) (SEL3)
100
120
140
160
180
1A0
1C0
300
340
280
2A0
ON
OFF
ON
ON
ON
ON
ON
ON
ON
Figure 16 also shows the recommended supply (VA+ and
VD+) and reference input (VREF+ and VREF−) bypassing. The
digital and analog supply pins can be connected together to
the same supply voltage. However, they need separate, mul-
tiple bypass capacitors. Multiple capacitors on the supply
pins and the reference inputs ensures a low impedance by-
pass path over a wide frequency range.
OFF
OFF
ON
ON
ON
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
ON
ON
OFF
OFF
ON
ON
OFF
ON
ON
All digital interface control signals (IOR, IOW, and AEN),
data lines (DB0–DB7), address lines (A0–A9), and IRQ (in-
terrupt request) lines (IRQ2, IRQ3, and IRQ5) connections
are made through the motherboard slot connector. All analog
signals applied to, or received by, the input multiplexer
(IN0–IN7 for the LM12(H)458 and IN0–IN3, MUXOUT+,
MUXOUT−, S/H IN+ and S/H IN− for the LM12(H)454),
OFF
OFF
OFF
OFF
ON
ON
ON
OFF
ON
The board allows the use of one of three Interrupt Request
(IRQ) lines IRQ2, IRQ3, and IRQ5. The individual IRQ line
can be selected using switches 5, 6, and 7 of SW DIP-8.
When using any of these three IRQs, the user needs to en-
sure that there are no conflicts between the evaluation board
and any other boards attached to the computer’s mother-
board.
V
REF+, VREF−, VREFOUT, and the SYNC signal input/ output
are applied through a DB-37 connector on the rear side of
the board. Figure 16 shows that there are numerous analog
ground connections available on the DB-37 connector.
The voltage applied to VREF− and VREF+ is selected using
two jumpers, JP1 and JP2. JP1 selects between the voltage
applied to the DB-37’s pin 24 or GND and applies it to the
LM12(H)454/8’s VREF− input. JP2 selects between the
LM12(H)454/8’s internal reference output, VREFOUT, and the
voltage applied to the DB-37’s pin 22 and applies it to the
LM12(H)454/8’s VREF+ input.
Switches 1–4, along with address lines A5–A9 are used as
inputs to GAL16V8 Programmable Gate Array (U2). This de-
vice forms the interface between the computer’s control and
address lines and generates the control signals used by the
LM12(H)454/8 for CS, WR, and RD. It also generates the
signal that controls the data buffers. Several address ranges
within the computer’s I/O memory map are available. Refer
to Table III for the switch settings that gives the desired I/O
memory address range. Selection of an address range must
be done so that there are no conflicts between the evaluation
board and any other boards attached to the computer’s
motherboard. The GAL equations are shown in Figure 18.
The GAL functional block diagram is shown in Figure 19.
Figures 20, 21, 22, 23 show the layout of each layer in the
3-layer evaluation/interface board plus the silk-screen layout
showing parts placement. Figure 21 is the top or component
side, Figure 22 is the middle or ground plane layer, Figure 23
is the circuit side, and Figure 20 is the parts layout.
33
www.national.com
6.0 Application Circuits (Continued)
DS011264-26
Note: The layout utilizes a split ground plane. The analog ground plane is placed under all analog signals and U5 pins 1, 34–44. The remaining signals and
pins are placed over the digital ground. The single point ground connection is at U6, pin 2, and this is connected to the motherboard pin B1.
FIGURE 16. Schematic for the LM12(H)454/8 Evaluation Interface
Board for XT and AT Style Computers, Order Number LM12458EVAL
www.national.com
34
6.0 Application Circuits (Continued)
Parts List:
Y1
D1
L1
HC49U, 8 MHz crystal
1N4002
33 µH
P1
R1
R2
RN1
DB37F; parallel connector
1
10 MΩ, 5%,
⁄4W
1
2 kΩ, 5%,
⁄4W
1
10 kΩ, 6 resistor SIP, 5%,
⁄8W
JP1, JP2 HX3, 3-pin jumper
S1 SW DIP-8; 8 SPST switches
C1–3, C6, C9–11,
C19, C22
C4
0.1 µF, 50V, monolithic ceramic
68 pF, 50V, ceramic disk
15 pF, 50V, ceramic disk
100 µF, 25V, electrolytic
C5
C7, C21
C8, C12, C20 10 µF, 35V, electrolytic
C13, C16
C14, C18
C15, C17
U1
0.01 µF, 50V, monolithic ceramic
1 µF, 35V, tantalum
100 µF, 50V, ceramic disk
MM74HCT244N
U2
GAL16V8-20LNC
U3
MM74HCT245N
U4
MM74HCU04N
U5
LM12(H)458CIV or LM12454CIV
LM340AT-5.0
U6
SK1
44-pin PLCC socket
LM12(H)458/4 Rev. D PC Board
A1
FIGURE 17. Parts List for the LM12(H)454/8 Evaluation Interface
Board for XT and AT Style Computers, Order Number LM12458EVAL
35
www.national.com
6.0 Application Circuits (Continued)
DS011264-32
FIGURE 18. Logic Equations Used to Program the GAL16V8
www.national.com
36
6.0 Application Circuits (Continued)
DS011264-27
FIGURE 19. GAL Functional Block Diagram
DS011264-31
FIGURE 20. Silk-Screen Layout Showing Parts Placement on the LM12(H)454/8 Evaluation/Interface Board
37
www.national.com
6.0 Application Circuits (Continued)
DS011264-28
FIGURE 21. LM12(H)454/8 Evaluation/Interface Board Component-Side Layout Positive
www.national.com
38
6.0 Application Circuits (Continued)
DS011264-29
FIGURE 22. LM12(H)454/8 Evaluation/Interface Board Ground-Plane Layout Negative
39
www.national.com
6.0 Application Circuits (Continued)
DS011264-30
FIGURE 23. LM12(H)454/8 Evaluation/Interface Circuit-Side Layout Positive
www.national.com
40
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number LM12458MEL/883 or 5962-9319501MYA,
LM12H458MEL/883 or 5962-9319502MYA
NS Package Number EL44A
41
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number LM12454CIV, LM12458CIV or LM12H458CIV
NS Package Number V44A
Order Number LM12H458CIVF or LM12458CIVF
NS Package Number VGZ44A
www.national.com
42
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
©2020 ICPDF网 联系我们和版权申明