LM139AE/883 [NSC]
Low Power Low Offset Voltage Quad Comparators; 低功耗低失调电压QUAD比较仪
| 型号： | LM139AE/883 |
| 厂家： | 
National Semiconductor |
| 描述： | Low Power Low Offset Voltage Quad Comparators |
| 文件： | 总24页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 15, 2010
LM139AQML
LM139QML
Low Power Low Offset Voltage Quad Comparators
General Description
Features
The LM139 series consists of four independent precision volt-
age comparators with an offset voltage specification as low
as 2 mV max for all four comparators. These were designed
specifically to operate from a single power supply over a wide
range of voltages. Operation from split power supplies is also
possible and the low power supply current drain is indepen-
dent of the magnitude of the power supply voltage. These
comparators also have a unique characteristic in that the input
common-mode voltage range includes ground, even though
operated from a single power supply voltage.
Available with Radiation Guarantee
■
Total Ionizing Dose
ELDRS Free
Wide supply voltage range
LM139/139A Series
Very low supply current drain (0.8 mA) — independent of
supply voltage
100 krad(Si)
100 krad(Si)
—
—
■
■
■
2 to 36 VDC or ±1 to ±18 VDC
Low input biasing current:
Low input offset current:
Offset voltage:
Input common-mode voltage range includes GND
Differential input voltage range equal to the power supply
voltage
25 nA
±5 nA
±1 mV
■
■
■
■
■
Application areas include limit comparators, simple analog to
digital converters; pulse, squarewave and time delay gener-
ators; wide range VCO; MOS clock timers; multivibrators and
high voltage digital logic gates. The LM139 series was de-
signed to directly interface with TTL and CMOS. When oper-
ated from both plus and minus power supplies, they will
directly interface with MOS logic— where the low power drain
of the LM139/LM139A is a distinct advantage over standard
comparators.
Low output saturation voltage:
Output voltage compatible with TTL, DTL, ECL, MOS and
CMOS logic systems
250 mV at 4 mA
■
■
Advantages
High precision comparators
■
■
■
■
■
■
Reduced VOS drift over temperature
Eliminates need for dual supplies
Allows sensing near GND
Compatible with all forms of logic
Power drain suitable for battery operation
Ordering Information
NS Part Number
LM139E/883
SMD Part Number
NS Package Number Package Description
E20A
J14A
20 terminal Leadless Chip Carrier
LM139J/883
14LD CERDIP
LM139AW-SMD
LM139AWG-SMD
LM139AE/883
LM139AJ/883
5962–8773901DA
5962–8773901XA
W14B
WG14A
E20A
14LD CERPACK
14LD Ceramic SOIC
20 terminal Leadless Chip Carrier
14LD CERDIP
J14A
5962R9673801VCA
100 krad(Si)
LM139AJRQMLV (Note 11)
J14A
J14A
14LD CERDIP
14LD CERDIP
LM139AJRLQMLV (Note 15)
ELDRS Free
5962R9673802VCA
100 krad(Si)
LM139AW-QMLV
LM139AW/883
5962–9673801VDA
W14B
W14B
14LD CERPACK
14LD CERPACK
LM139AWG-QMLV
LM139AWG/883
5962–9673801VXA
WG14A
WG14A
14LD Ceramic SOIC
14LD Ceramic SOIC
5962R9673801VXA
100 krad(Si)
LM139AWGRQMLV (Note 11)
WG14A
WG14A
W14B
14LD Ceramic SOIC
14LD Ceramic SOIC
14LD CERPACK
LM139AWGRLQMLV (Note 15)
ELDRS Free
5962R9673802VXA
100 krad(Si)
5962R9673801VDA
100 krad(Si)
LM139AWRQMLV (Note 11)
© 2010 National Semiconductor Corporation
201221
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NS Part Number
SMD Part Number
NS Package Number Package Description
LM139AWRLQMLV (Note 15)
ELDRS Free
5962R9673802VDA
100 krad(Si)
W14B
(Note 1)
(Note 1)
14LD CERPACK
Bare Die
LM139 MDE (Note 15)
ELDRS Free
5962R9673802V9A
100 krad(Si)
5962R9673801V9A
100 krad(Si)
LM139 MDR (Note 11)
Bare Die
Note 1: FOR ADDITIONAL DIE INFORMATION, PLEASE VISIT THE HI REL WEB SITE AT: www.national.com/analog/space/level_die
Connection Diagrams
Dual-In-Line Package
20122102
See NS Package NumberJ14A
20122127
See NS Package Number W14B, WG14A
20122144
See NS Package Number E20A
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2
Absolute Maximum Ratings (Note 2)
LM139 / LM139A
36 VDC or ±18 VDC
36 VDC
Supply Voltage, V+
Differential Input Voltage (Note 8)
Input Voltage
−0.3 VDC to +36 VDC
50 mA
Input Current (VIN < −0.3 VDC
)
(Note 4)
Power Dissipation
LCC
CERDIP
CERPACK
SOIC
Sink Current (approx) (Note 12)
Output Short-Circuit to GND, (Note 3)
Storage Temperature Range
(Note 5, Note 14)
1250 mW
1200 mW
680 mW
680 mW
20mA
Continuous
-65°C ≤ TA ≤ +150°C
+150°C
Maximum Junction Temperature (TJ)
Lead Temperature (Soldering, 10 seconds)
Operating Temperature Range
300°C
-55°C ≤ TA ≤ +125°C
Thermal Resistance
ꢀꢀθJA
LCC
LCC
CERDIP
CERDIP
(Still Air)
(500LF / Min Air flow)
(Still Air)
100°C/W
73°C/W
103°C/W
65°C/W
(500LF / Min Air flow)
CERPACK (Still Air)
CERPACK (500LF / Min Air flow)
183°C/W
120°C/W
183°C/W
120°C/W
SOIC
SOIC
(Still Air)
(500LF / Min Air flow)
ꢀꢀθJC
LCC
CERDIP
CERPACK
SOIC
28°C/W
23°C/W
23°C/W
23°C/W
Package Weight (typical)
LCC
CERDIP
CERPACK
SOIC
470mg
2,190mg
460mg
410mg
600V
ESD rating (Note 13)
Recommended Operating Conditions
Supply Voltage
5.0 VDC to +30 VDC
Ambient Operating Temperature Range
−55°C ≤ TA ≤ +125°C
3
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Quality Conformance Inspection
Mil-Std-883, Method 5005 — Group A
Subgroup
Description
Static tests at
Temp (°C)
+25
1
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
+25
5
+125
-55
6
7
+25
8A
8B
9
+125
-55
+25
10
11
+125
-55
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4
LM139 883 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified. +V = 5V, VCM = 0V
Symbol
Parameters
Conditions
Sub-
groups
Notes
Min
Max
Unit
ICC
Supply Current
RL = Infinity
2.0
2.0
5.0
9.0
5.0
9.0
5.0
9.0
mA
mA
mV
mV
mV
mV
mV
mV
dB
1, 2, 3
1, 2, 3
1
Supply Current
+V = 30V, RL = Infinity
+V = 30V
VIO
Input Offset Voltage
-5.0
-9.0
-5.0
-9.0
-5.0
-9.0
60
2, 3
1
+V = 30V, VCM = 28.5V
+V = 30V, VCM = 28.0V
2, 3
1
2, 3
1
CMRR
PSRR
± IBias
Common Mode Rejection Ratio +V = 30V, VCM = 0V to 28.5V
Power Supply Rejection Ratio
Input Bias Current
+V = 5V to 30V
VO = 1.5V
60
dB
1
(Note 6)
(Note 6)
-100
-300
-25
-1.0
-1.0
25
nA
1
nA
2, 3
1
IIO
Input Offset Current
VO = 1.5V
nA
-100
100
1.0
nA
2, 3
1, 2, 3
1
ICEX
ISink
VSat
Output Leakage Current
Output Sink Current
Saturation Voltage
+V = 30V, VO = 30V
VO = 1.5V
µA
6.0
mA
mV
mV
ISink = 4mA
400
700
1
2, 3
AV
Voltage Gain
+V = 15V, RL ≥ 15ΩK, VI = 1V to
50
0
V/mV
V
1
11V
VCM
Common Mode Voltage Range +V = 30V
V+ -
(1.5)
V+ -
(Note 9)
(Note 9)
(Note 10)
(Note 10)
1
0
V
2, 3
(2.0)
VDiff
Differential Input Voltage
+V = 30V, -V = 0V, +VI = 36V, -VI
500
500
nA
nA
1, 2, 3
1, 2, 3
= 0V
+V = 30V, -V = 0V, +VI = 0V, -VI =
36V
AC Parameters
The following conditions apply, unless otherwise specified. +V = 5V
Symbol
Parameters
Conditions
Sub-
groups
Notes
Min
Max
Unit
tRLH
Response Time
VOD = 5mV
VOD = 50mV
VOD = 5mV
VOD = 50mV
5.0
0.8
2.5
0.8
µS
µS
µS
µS
9
9
9
9
tRHL
Response Time
5
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LM139A SMD 5962–8773901 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified. +V = 5V, VCM = 0V
Symbol
Parameter
Conditions
Sub-
groups
Notes
Min
Max
Unit
ICC
Supply Current
+V = 30V, RL = Infinity
RL = Infinity
3.0
3.0
0.5
1.0
400
700
mA
mA
µA
1, 2, 3
1, 2, 3
1
ICEX
Output Leakage Current
Saturation Voltage
+V = 30V, -VI = 0V, +VI ≥ 1V, VO
= 30V
µA
2, 3
1
VSat
mV
mV
mA
mV
mV
mV
mV
mV
mV
nA
ISink ≤ 4mA, -VI = 1V, +VI = 0V
2, 3
1
ISink
VIO
Output Sink Current
Input Offset Voltage
6.0
-2.0
-4.0
-2.0
-4.0
-2.0
-4.0
-100
-300
-25
VO ≥ 1.5V, -VI = 1V, +VI = 0V
RS = 0Ω
2.0
4.0
2.0
4.0
2.0
4.0
-1.0
-1.0
25
1
2, 3
1
+V = 30V, RS = 0Ω
2, 3
1
+V = 30V, VCM = 28V, VO = 1.4V,
RS = 0Ω
2, 3
1
±IIB
IIO
Input Bias Current
VO = 1.5V
(Note 6)
(Note 6)
nA
2, 3
1
Input Offset Current
VO = 1.5V
nA
-100
70
100
nA
2, 3
1, 2, 3
PSRR
CMRR
Power Supply Rejection Ratio
+V = 5V to 30V
dB
Common Mode Rejection Ratio +V = 30V, VCM = 0V to 28V, RL
70
dB
1, 2, 3
≥ 15KΩ
AV
Voltage Gain
50
25
V/mV
V/mV
4
+V = 15V, RL ≥ 15KΩ, VO = 1V to
11V
5, 6
VCM
Common Mode Voltage Range +V = 30V
V+ -
(2.0)
V+ -
(Note 9)
(Note 9)
0
0
V
V
1, 2, 3
1, 2, 3
+V = 5V
(2.0)
AC Parameters
The following conditions apply, unless otherwise specified. +V = 5V
Symbol
Parameters
Conditions
Sub-
groups
Notes
Min
Max
Unit
tRLH
tRHL
Response Time
Response Time
VOD = 5mV, RL = 5.1KΩ
VOD = 5mV, RL = 5.1KΩ
5.0
2.5
µS
µS
9
9
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6
LM139A 883, QMLV & RH, SMD 5962–9673801 Electrical Characteristics
DC Parameters
(Note 11, Note 15)
The following conditions apply, unless otherwise specified. +V = 5V, VCM = 0V
Symbol
Parameters
Conditions
Sub-
groups
Notes
Min
Max
Unit
ICC
Supply Current
RL = Infinity
2.0
2.0
mA
mA
µA
1, 2, 3
1, 2, 3
1, 2, 3
1
+V = 30V, RL = Infinity
+V = 30V, VO = 30V
ISink = 4mA
ICEX
VSat
Output Leakage Current
Saturation Voltage
1.0
400
700
mV
mV
mA
mV
mV
mV
mV
2, 3
1
ISink
VIO
Output Sink Current
Input Offset Voltage
VO = 1.5V
+V = 30V
6.0
-2.0
-4.0
-2.0
-4.0
2.0
4.0
2.0
4.0
1
2, 3
1
2, 3
+V = 30V, VCM = 28.5V,
VO = 1.5V
-2.0
-4.0
2.0
4.0
mV
mV
1
+V = 30V, VCM = 28.0V,
VO = 1.5V
2, 3
± IBias
IIO
Input Bias Current
VO = 1.5V
(Note 6)
(Note 6)
-100
-300
-25
-1.0
-1.0
25
nA
nA
nA
nA
dB
dB
1
2, 3
1
Input Offset Current
VO = 1.5V
-100
60
100
2, 3
1
PSRR
CMRR
AV
Power Supply Rejection Ratio
+V = 5V to 30V
Common Mode Rejection Ratio +V = 30V, VCM = 0V to 28.5V
60
1
Voltage Gain
+V = 15V, RL ≥ 15KΩ, VO = 1V to
11V
50
0
V/mV
V
1
VCM
Common Mode Voltage Range +V = 30V
V+ -
(1.5)
V+ -
(Note 7,
Note 9)
1
(Note 7,
Note 9)
0
V
2, 3
(2.0)
VDiff
Differential Input Voltage
+V = 30V, -V =0V, +VI = 36V, -VI
(Note 10)
(Note 10)
500
500
nA
nA
1, 2, 3
1, 2, 3
= 0V
+V = 30V, -V = 0V, +VI = 0V, -VI =
36V
AC Parameters
(Note 11, Note 15)
The following conditions apply, unless otherwise specified. +V = 5V
Symbol
Parameters
Conditions
Sub-
groups
Notes
Min
Max
Unit
tRLH
Response Time
VOD = 5mV
VOD = 50mV
VOD = 5mV
VOD = 50mV
5.0
0.8
2.5
0.8
µS
µS
µS
µS
4
4
4
4
tRHL
Response Time
7
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DC Parameters Delta Values
The following conditions apply, unless otherwise specified. +V = 5V, VCM = 0V
Deltas required for S-Level, MLS (as specified on Internal Processing instructions (IPI)), and QMLV product at Group B, Subgroup
5.
Symbol
Parameters
Conditions
Sub-
groups
Notes
Min
Max
Unit
VIO
Input Offset Voltage
Input Bias Current
Input Offset Current
-1.0
-15
-10
1.0
15
mV
nA
nA
1
1
1
± IBias
IIO
VO = 1.5V
VO = 1.5V
(Note 6)
+10
DC/AC Parameters 50K Post Rad Limits +25°C (Note 11)
The following conditions apply, unless otherwise specified.
DC: +V = 5V, VCM = 0V
AC: +V = 5V
Symbol
Parameters
Conditions
Sub-
groups
Notes
Min
Max
Unit
VIO
Input Offset Voltage
+V = 5V, VCM = 0
+V = 30V, VCM = 0
-2.5
-2.5
2.5
2.5
mV
mV
1
1
+V = 30V, VCM = 28.5V,
VO = 1.5V
-2.5
2.5
mV
1
± IBias
tRLH
Input Bias Current
Response Time
VO = 1.5V
(Note 6)
-110
-1.0
0.9
nA
µS
1
4
VOD (Overdrive) = 50mV
DC/AC Parameters 100K Post Rad Limits +25°C (Note 11, Note 15)
The following conditions apply, unless otherwise specified.
DC: +V = 5V, VCM = 0V
AC: +V = 5V
Symbol
Parameters
Conditions
Sub-
groups
Notes
Min
Max
Unit
VIO
Input Offset Voltage
+V = 5V, VCM = 0
+V = 30V, VCM = 0
-4.0
-4.0
4.0
4.0
mV
mV
1
1
+V = 30V, VCM = 28.5V,
VO = 1.5V
-4.0
4.0
mV
1
± IBias
tRLH
Input Bias Current
Response Time
VO = 1.5V
(Note 6)
-110
-1.0
1.0
nA
µS
1
4
VOD (Overdrive) = 50mV
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8
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guaranteed specific performance limits. For guaranteed specifications and test conditions, see, the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 3: Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output
current is approximately 20 mA independent of the magnitude of V+.
Note 4: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP
transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action
on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrive) for the
time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again
returns to a value greater than −0.3 VDC (at 25°)C.
Note 5: The low bias dissipation and the ON-OFF characteristics of the outputs keeps the chip dissipation very small (PD ≤100mW), provided the output transistors
are allowed to saturate.
Note 6: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output
so no loading change exists on the reference or input lines.
Note 7: The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-
mode voltage range is V+ −1.5V for Subgroup 1, or V+ −2.0V for Subgroup 2 & 3. Either or both inputs can go to +30 VDC without damage, independent of the
magnitude of V+.
Note 8: Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the
comparator will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDCbelow the magnitude of the negative power
supply, if used) (at 25°C).
Note 9: Parameter guaranteed by VIO tests
Note 10: The value for VDiff is not data logged during Read and Record.
Note 11: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the “Post Radiation Limits” table.
These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters
are guaranteed only for the conditions as specified in Mil-Std-883, Method 1019, Condition A.
Note 12: SMD 5962–8773901 only
Note 13: Human Body model, 1.5 KΩ in series with 100 pF
Note 14: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (Package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax — TA) /
θ
JA or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 15: Low dose rate testing has been performed on a wafer-by-wafer basis, per test method 1019, condition D, MIL-STD-883, with no enhanced low dose
rate sensitivity (ELDRS) effect. Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics, except as listed in the “Post
Radiation Limits” table. Radiation end point limits for the noted parameters are guaranteed for only the conditions as specified in MIL-STD-883, Method 1019,
condition D.
9
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Typical Performance Characteristics LM139, LM139A
Supply Current
Input Current
20122134
20122135
Output Saturation Voltage
Response Time for Various Input Overdrives
—Negative Transition
20122136
20122137
Response Time for Various Input Overdrives
—Positive Transition
20122138
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Driving CMOS
Application Hints
The LM139 series are high gain, wide bandwidth devices
which, like most comparators, can easily oscillate if the output
lead is inadvertently allowed to capacitively couple to the in-
puts via stray capacitance. This shows up only during the
output voltage transition intervals as the comparator changes
states. Power supply bypassing is not required to solve this
problem. Standard PC board layout is helpful as it reduces
stray input-output coupling. Reducing this input resistors to <
10 kΩ reduces the feedback signal levels and finally, adding
even a small amount (1 to 10 mV) of positive feedback (hys-
teresis) causes such a rapid transition that oscillations due to
stray feedback are not possible. Simply socketing the IC and
attaching resistors to the pins will cause input-output oscilla-
tions during the small transition intervals unless hysteresis is
used. If the input signal is a pulse waveform, with relatively
fast rise and fall times, hysteresis is not required.
20122104
Driving TTL
All pins of any unused comparators should be tied to the neg-
ative supply.
The bias network of the LM139 series establishes a drain
current which is independent of the magnitude of the power
supply voltage over the range of from 2 VDC to 30 VDC
.
It is usually unnecessary to use a bypass capacitor across the
power supply line.
20122105
AND Gate
The differential input voltage may be larger than V+ without
damaging the device. Protection should be provided to pre-
vent the input voltages from going negative more than −0.3
VDC (at 25°C). An input clamp diode can be used as shown
in the applications section.
The output of the LM139 series is the uncommitted collector
of a grounded-emitter NPN output transistor. Many collectors
can be tied together to provide an output OR'ing function. An
output pull-up resistor can be connected to any available
power supply voltage within the permitted supply voltage
range and there is no restriction on this voltage due to the
magnitude of the voltage which is applied to the V+ terminal
of the LM139A package. The output can also be used as a
simple SPST switch to ground (when a pull-up resistor is not
used). The amount of current which the output device can sink
is limited by the drive available (which is independent of V+)
and the β of this device. When the maximum current limit is
reached (approximately 16 mA), the output transistor will
come out of saturation and the output voltage will rise very
rapidly. The output saturation voltage is limited by the ap-
proximately 60Ω RSAT of the output transistor. The low offset
voltage of the output transistor (1 mV) allows the output to
clamp essentially to ground level for small load currents.
20122108
OR Gate
Typical Applications
(V+ = 5.0 VDC
)
Basic Comparator
20122109
20122103
11
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Typical Applications
(V+= 15 VDC
)
One-Shot Multivibrator
20122110
Bi-Stable Multivibrator
20122111
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12
One-Shot Multivibrator with Input Lock Out
20122112
Pulse Generator
20122117
13
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Large Fan-In AND Gate
ORing the Outputs
20122113
20122115
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Time Delay Generator
20122114
Non-Inverting Comparator with Hysteresis
Inverting Comparator with Hysteresis
20122118
20122119
15
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Squarewave Oscillator
Basic Comparator
20122121
20122116
Limit Comparator
Comparing Input Voltages
of Opposite Polarity
20122120
20122124
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16
Output Strobing
Crystal Controlled Oscillator
20122122
* Or open-collector logic gate without pull-up resistor
20122125
17
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18
Transducer Amplifier
Zero Crossing Detector (Single Power Supply)
20122130
20122128
Split-Supply Applications
(V+ = +15 VDC and V− = −15 VDC
)
MOS Clock Driver
20122131
19
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Zero Crossing Detector
Comparator With a Negative Reference
20122132
20122133
Schematic Diagram
20122101
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Revision History
Date Released
Revision
Section
Changes
02/08/05
A
New Release to corporate format
3 MDS datasheets converted into one Corp.
datasheet format. MNLM139A-X-RH rev 4B0,
MDLM139A-X rev 0C1, MNLM139–X rev 1A1.
MDS datasheets will be archived.
06/28/06
B
Features, Ordering Information Table, Rad Added Available with Radiation Guarantee, Low
Hard Electrical Section and Notes
Dose NSID's to table 5962R9673802VCA
LM139AJRLQMLV, 5962R9673802VDA
LM139AWRLQMLV, 5962R9673802VXA
LM139AWGRLQMLV, and reference to Note 11
and 16. Note 16 to Rad Hard Electrical Heading.
Note 16 to Notes. Archive Revision A.
02/13/08
C
D
Features, Ordering Table, LM139A 883, Added TID & Eldrs reference, Note 11 - Condition
QMLV & RH, SMD 5962–9673801
Electrical Characteristics, Notes
A. Changed VCM parameter - pg 8, Title from Drift
Values to Delta Values - pg 9 & Note 16. Revision
B will be Archive .
10/15/2010
Data Sheet Title, Ordering Table,
Changed the data sheet title from LM139A/
LM139QML to LM139AQML/LM139QML,
removed EOL NSID's. Added Bare Die NSID's.
Revision C will be Archived
21
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Leadless Chip Carrier (E))
NS Package Number E20A
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