LM193JAN_技术文档

May 2005

LM193JAN

Low Power Low Offset Voltage Dual Comparators

General Description

Advantages

n High precision comparators

The LM193 series consists of two independent precision

voltage comparators with an offset voltage specification as

low as 2.0 mV max for two comparators which were de-

signed specifically to operate from a single power supply

over a wide range of voltages. Operation from split power

supplies is also possible and the low power supply current

drain is independent of the magnitude of the power supply

voltage. These comparators also have a unique characteris-

tic in that the input common-mode voltage range includes

ground, even though operated from a single power supply

voltage.

n Reduced V_OSdrift over temperature

n Eliminates need for dual supplies

n Allows sensing near ground

n Compatible with all forms of logic

n Power drain suitable for battery operation

Features

n Wide supply

— Voltage range:

— Single or dual supplies:

n Very low supply current drain (0.4 mA) — independent

of supply voltage

n Low input biasing current:

n Low input offset current:

n Maximum offset voltage

n Input common-mode voltage range includes ground

n Differential input voltage range equal to the power

supply voltage

5.0V_DCto 36V_DC

2.5V_DCto 18V_DC

Application areas include limit comparators, simple analog to

digital converters; pulse, squarewave and time delay gen-

erators; wide range VCO; MOS clock timers; multivibrators

and high voltage digital logic gates. The LM193 series was

designed to directly interface with TTL and CMOS. When

operated from both plus and minus power supplies, the

LM193 series will directly interface with MOS logic where

their low power drain is a distinct advantage over standard

comparators.

25 nA typ

3 nA typ

@

+5mV Max 25˚C

n Low output saturation voltage,:

250 mV at 4 mA typ

n Output voltage compatible with TTL, DTL, ECL, MOS

and CMOS logic systems

Ordering Information

NS Part Number

JAN Part Number

JM38510/11202BGA

JM38510/11202BPA

NS Package Number

Package Description

8LD T0-99 Metal Can

8LD CERDIP

JL193BGA

H08C

J08A

JL193BPA

Squarewave Oscillator

Non-Inverting Comparator with Hysteresis

20143209

20143238

DS201432

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Schematic and Connection Diagrams

20143202

Metal Can Package

20143203

Dual-In-Line Package

20143201

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2

Absolute Maximum Ratings (Note 1)

Supply Voltage, V⁺

Differential Input Voltage (Note 5)

Output Voltage

36V_DCor 18V_DC

36V

Input Voltage

−0.3V_DCto +36V_DC

50 mA

<

Input Current (V_IN−0.3V_DC) (Note 4)

Power Dissipation (Note 2),

CERDIP

@

400 mW T_A= 125˚C

@

Metal Can

330 mW T_A= 125˚C

Maximum Junction Temperature (T_Jmax

Output Short-Circuit to Ground (Note 3)

Operating Temperature Range

Storage Temperature Range

Thermal Resistance

θ_JA

175˚C

Continuous

−55˚C ≤ T_A≤ +125˚C

−65˚C ≤ T_A≤ +150˚C

Metal Can (Still Air)

174˚C/W

99˚C/W

146˚C/W

85˚C/W

Metal Can (500LF/Min Air flow)

CERDIP (Still Air)

CERDIP (500LF/Min Air flow)

θ_JC

Metal Can

44˚C/W

33˚C/W

260˚C

500V

CERDIP

Lead Temperature (Soldering, 10 seconds)

ESD Tolerance (Note 6)

Quality Conformance Inspection

Mil-Std-883, Method 5005 - Group A

Subgroup

Description

Static tests at

Temp˚C

25

1

2

Static tests at

125

-55

25

3

Static tests at

4

Dynamic tests at

Functional tests at

Switching tests at

Settling time at

5

125

-55

25

6

7

8A

8B

9

125

-55

25

10

11

12

13

14

125

-55

25

125

-55

3

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LM193 JAN Electrical Characteristics

DC Parameters

Sub-

groups

1

Symbol

Parameter

Conditions

Notes

Min Max

Unit

mV

nA

V_IO

Input Offset Voltage

+V_CC= 30V, -V_CC= 0V,

V_O= 15V

-5.0

-7.0

-5.0

-7.0

-5.0

-7.0

-5.0

-7.0

-25

-75

-25

-75

-25

-75

-25

-75

5.0

7.0

5.0

7.0

5.0

7.0

5.0

7.0

25

2, 3

1

+V_CC= 2V, -V_CC= -28V,

V_O= -13V

2, 3

1

+V_CC= 5V, -V_CC= 0V,

V_O= 1.4V

2, 3

1

+V_CC= 2V, -V_CC= -3V,

V_O= -1.6V

2, 3

1, 2

3

I_IO

Input offset Current

+V_CC= 30V, -V_CC= 0V,

(Note 7)

V_O= 15V, R_S= 20KΩ

75

+V_CC= 2V, -V_CC= -28V,

25

1, 2

3

V_O= -13V, R_S= 20KΩ

75

+V_CC= 5V, -V_CC= 0V,

25

1, 2

3

V_O= 1.4V, R_S= 20KΩ

75

+V_CC= 2V, -V_CC= -3V,

25

1, 2

3

V_O= -1.6V, R_S= 20KΩ

75

I_IB

Input Bias Current

+V_CC= 30V, -V_CC= 0V,

-100 +0.1

-200 +0.1

-100 +0.1

-200 +0.1

-100 +0.1

-200 +0.1

-100 +0.1

-200 +0.1

1, 2

3

V_O= 15V, R_S= 20KΩ

+V_CC= 2V, -V_CC= -28V,

1, 2

3

V_O= -13V, R_S= 20KΩ

+V_CC= 5V, -V_CC= 0V,

1, 2

3

V_O= 1.4V, R_S= 20KΩ

+V_CC= 2V, -V_CC= -3V,

1, 2

3

V_O= -1.6V, R_S= 20KΩ

CMRR

Input Voltage Common Mode

Rejection

2V ≤ +V_CC≤ 30V,

-28V ≤ -V_CC≤ 0V,

-13V ≤ V_O≤ 15V

76

dB

1, 2, 3

2V ≤ +V_CC≤ 5V,

-3V ≤ -V_CC≤ 0V,

-1.6V ≤ V_O≤ 1.4V

+V_CC= 30V, -V_CC= 0V,

V_O= +30V

70

dB

µA

nA

1, 2, 3

I_CEX

+I_IL

-I_IL

Output Leakage Current

Input Leakage Current

Logical "0" Output Voltage

1.0

+V_CC= 36V, -V_CC= 0V,

+V_I= 34V, -V_I= 0V

+V_CC= 36V, -V_CC= 0V,

+V_I= 0V, -V_I= 34V

+V_CC= 4.5V, -V_CC= 0V,

I_O= 4mA

-500 500

0.4

nA

V

1, 2, 3

1

V_OL

0.7

V

2, 3

1

+V_CC= 4.5V, -V_CC= 0V,

I_O= 8mA

1.5

V

2.0

V

2, 3

1, 2

3

I_CC

Power Supply Current

+V_CC= 5V, -V_CC= 0V,

V_ID= 15mV

2.0

mA

µV/˚C

3.0

+V_CC= 30V, -V_CC= 0V,

V_ID= 15mV

3.0

1, 2

3

4.0

∆

/ ∆T

Temperature Coefficient of

Input Offset Voltage

25˚C ≤ T_A≤ +125˚C

-55˚C ≤ T_A≤ 25˚C

(Note 9)

-25

25

2

IO

3

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4

LM193 JAN Electrical Characteristics (Continued)

DC Parameters (Continued)

Sub-

Symbol

Parameter

Conditions

Notes

(Note 9)

Min Max

-300 300

-400 400

Unit

pA/˚C

groups

∆I_IO/ ∆T

Temperature Coefficient of

Input Offset Current

25˚C ≤ T_A≤ +125˚C

-55˚C ≤ T_A≤ 25˚C

+V_CC= 15V, -V_CC= 0V,

R_L= 15KΩ,

2

3

A_VS

Open Loop Voltage Gain

(Note 8)

50

25

V/mV

4

1V ≤ V_O≤ 11V

5, 6

V_Lat

Voltage Latch (Logical "1"

Input)

+V_CC= 5V, -V_CC= 0V,

V_I= 10V, I_O= 4mA

0.4

V

9

AC Parameters

The following conditions apply, unless otherwise specified. +V_CC= 5V, −V_CC= 0V

Sub-

groups

7, 8B

8A

Symbol

Parameter

Conditions

Notes

Min Max

5.0

Unit

µS

t_RLH

Response Time

V_I= 100mV, R_L= 5.1KΩ,

V_OD= 5mV

7.0

V_I= 100mV, R_L= 5.1KΩ,

V_OD= 50mV

0.8

7, 8B

8A

1.2

t_RHL

Response Time

V_I= 100mV, R_L= 5.1KΩ,

V_OD= 5mV

2.5

7, 8B

8A

3.0

V_I= 100mV, R_L= 5.1KΩ,

V_OD= 50mV

0.8

7, 8B

8A

1.0

CS

Channel Separation

+V_CC= 20V, -V_CC= -10V,

A to B

80

dB

7

+V_CC= 20V, -V_CC= -10V,

B to A

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

(maximum junction temperature), θ (package junction

JA

Jmax

to ambient thermal resistance), and T (ambient temperature). The maximum allowable power dissipation at any temperature is P

= (T

- T )/θ or the

A

Dmax

Jmax A JA

number given in the Absolute Maximum Ratings, whichever is lower.

+

Note 3: Short circuits from the output to V can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output

+

current is approximately 20 mA independent of the magnitude of V .

Note 4: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP

transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action

+

on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V voltage level (or to ground for a large overdrive) for the time

duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again returns

to a value greater than −0.3V

.

DC

Note 5: Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the

comparator will provide a proper output state. The low input voltage state must not be less than −0.3V (or 0.3V below the magnitude of the negative power supply,

if used).

Note 6: Human body model, 1.5KΩ in series with 100pF.

Note 7: S/S R = 20KΩ, tested with R = 100KΩ for better resolution

S

Note 8: K in datalog is equivalent to V/mV.

Note 9: Calculated parameter for ∆V / ∆T and ∆I / ∆T.

IO

5

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Typical Performance Characteristics

Supply Current

Input Current

20143225

20143226

Response Time for Various Input Overdrives—Negative

Transition

Output Saturation Voltage

20143228

20143227

Response Time for Various Input Overdrives—Positive

Transition

20143229

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6

Application Hints

The LM193 series are high gain, wide bandwidth devices

which, like most comparators, can easily oscillate if the

output lead is inadvertently allowed to capacitively couple to

the inputs via stray capacitance. This shows up only during

the output voltage transition intervals as the comparator

change states. Power supply bypassing is not required to

solve this problem. Standard PC board layout is helpful as it

reduces stray input-output coupling. Reducing the input re-

The differential input voltage may be larger than V⁺without

damaging the device (Note 5). Protection should be provided

to prevent the input voltages from going negative more than

−0.3 V_DC(at 25˚C). An input clamp diode can be used as

shown in the applications section.

The output of the LM193 series is the uncommitted collector

of a grounded-emitter NPN output transistor. Many collectors

can be tied together to provide an output OR’ing function. An

output pull-up resistor can be connected to any available

power supply voltage within the permitted supply voltage

range and there is no restriction on this voltage due to the

magnitude of the voltage which is applied to the V⁺terminal

of the LM193 package. The output can also be used as a

simple SPST switch to ground (when a pull-up resistor is not

used). The amount of current which the output device can

sink is limited by the drive available (which is independent of

V⁺) and the β of this device. When the maximum current limit

is reached (approximately 16mA), the output transistor will

come out of saturation and the output voltage will rise very

rapidly. The output saturation voltage is limited by the ap-

proximately 60Ω r_SATof the output transistor. The low offset

voltage of the output transistor (1.0mV) allows the output to

clamp essentially to ground level for small load currents.

<

sistors to

10 kΩ reduces the feedback signal levels and

finally, adding even a small amount (1.0 to 10 mV) of positive

feedback (hysteresis) causes such a rapid transition that

oscillations due to stray feedback are not possible. Simply

socketing the IC and attaching resistors to the pins will cause

input-output oscillations during the small transition intervals

unless hysteresis is used. If the input signal is a pulse

waveform, with relatively fast rise and fall times, hysteresis is

not required.

All input pins of any unused comparators should be tied to

the negative supply.

The bias network of the LM193 series establishes a drain

current which is independent of the magnitude of the power

supply voltage over the range of from 2.0 V_DCto 30 V_DC

.

It is usually unnecessary to use a bypass capacitor across

the power supply line.

Typical Applications (V⁺=5.0 V_DC

)

Basic Comparator

Driving CMOS

Driving TTL

20143235

20143237

20143236

Squarewave Oscillator

Pulse Generator

Crystal Controlled Oscillator

20143238

20143240

20143239

* For large ratios of R1/R2,

D1 can be omitted.

7

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Typical Applications (V⁺=5.0 V_DC) (Continued)

Two-Decade High Frequency VCO

20143241

V* = +30 V

+250 mV

DC

≤ V ≤ +50 V

DC

C

DC

700Hz ≤ f ≤ 100kHz

o

Basic Comparator

Non-Inverting Comparator with Hysteresis

20143206

20143209

Inverting Comparator with Hysteresis

Output Strobing

20143210

20143211

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8

Typical Applications (V⁺=5.0 V_DC) (Continued)

AND Gate

OR Gate

20143213

20143212

Large Fan-in AND Gate

Limit Comparator

20143215

20143214

Comparing Input Voltages of Opposite Polarity

ORing the Outputs

20143216

20143217

9

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Typical Applications (V⁺=5.0 V_DC) (Continued)

Zero Crossing Detector (Single Power Supply)

One-Shot Multivibrator

20143221

20143222

Bi-Stable Multivibrator

One-Shot Multivibrator with Input Lock Out

20143224

20143223

Zero Crossing Detector

Comparator With a Negative Reference

20143244

20143243

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10

Typical Applications (V⁺=5.0 V_DC) (Continued)

Time Delay Generator

20143207

Split-Supply Applications (V⁺=+15 V_DCand V⁻=−15 V_DC

)

MOS Clock Driver

20143242

11

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Revision History Section

Date Released Revision

Section

Originator

L. Lytle

Changes

05/09/05

A

New Release. Corporate format

1 MDS datasheets converted into one Corp.

datasheet format. DC Drift table was deleted

due to no JANS product offerings.

MJLM193-X Rev 1A1 MDS will be archived.

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12

Physical Dimensions inches (millimeters) unless otherwise noted

Metal Can Package (H)

NS Package Number H08C

Ceramic Dual-In-Line Package

NS Package Number J08A

13

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Notes

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result

in a significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

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National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products

Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain

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型号：	LM193JAN
厂家：	National Semiconductor
描述：	Low Power Low Offset Voltage Dual Comparators 低功耗低失调电压双比较器比较器
文件：	总14页 (文件大小：682K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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