LM25005MH [NSC]
42V, 2.5A Step-Down Switching Regulator; 42V ， 2.5A降压型开关稳压器
| 型号： | LM25005MH |
| 厂家： | 
National Semiconductor |
| 描述： | 42V, 2.5A Step-Down Switching Regulator |
| 文件： | 总22页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2006
LM25005
42V, 2.5A Step-Down Switching Regulator
General Description
Features
The LM25005 switching regulator features all of the functions
necessary to implement an efficient, high voltage buck regu-
lator using a minimum of external components. This easy to
use regulator includes a 42V, 160mΩ, N-channel MOSFET,
with an output current capability of 2.5 Amps. The regulator
control method is based upon current mode control utilizing
an emulated current ramp. Current mode control provides in-
herent line voltage feed-forward, cycle-by-cycle current limit-
ing and ease of loop compensation. The use of an emulated
control ramp reduces noise sensitivity of the pulse-width mod-
ulation circuit, allowing reliable control of very small duty
cycles necessary in high input voltage applications. The op-
erating frequency is programmable from 50kHz to 500kHz.
An oscillator synchronization pin allows multiple LM25005
regulators to self-synchronize or to be synchronized to an ex-
ternal clock. Additional protection features include: current
limit, thermal shutdown and remote shutdown capability. The
device is available in a power enhanced TSSOP-20 package
featuring an exposed die attach pad to aid thermal dissipation.
Integrated 42V, 160mΩ N-channel MOSFET
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Ultra-wide input voltage range from 7V to 42V
Internal bias regulator
Adjustable output voltage from 1.225V
1.5% feedback reference accuracy
Current mode control with emulated inductor current ramp
Single resistor oscillator frequency setting
Oscillator synchronization input
Programmable soft-start
Shutdown / Standby input
Wide bandwidth error amplifier
Thermal Shutdown
Package
TSSOP-20EP (Exposed Pad)
■
Simplified Application Schematic
20170001
© 2007 National Semiconductor Corporation
201700
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Connection Diagram
20170002
Top View
20-Lead TSSOP
Ordering Information
Order Number
LM25005MH
Package Type
NSC Package Drawing
MXA20A
Supplied As
Exposed Pad TSSOP-20
Exposed Pad TSSOP-20
73 Units in Rail
LM25005MHX
MXA20A
2500 Units on Tape and Reel
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Pin Descriptions
Pin(S)
Name
Description
Application Information
1
VCC
Output of the bias regulator
Vcc tracks Vin up to 9V. Beyond 9V, Vcc is regulated to 7
Volts. A 0.1uF to 1uF ceramic decoupling capacitor is
required. An external voltage (7.5V – 14V) can be applied
to this pin to reduce internal power dissipation.
2
SD
Shutdown or UVLO input
If the SD pin voltage is below 0.7V the regulator will be in a
low power state. If the SD pin voltage is between 0.7V and
1.225V the regulator will be in standby mode. If the SD pin
voltage is above 1.225V the regulator will be operational. An
external voltage divider can be used to set a line
undervoltage shutdown threshold. If the SD pin is left open
circuit, a 5µA pull-up current source configures the regulator
fully operational.
3, 4
5
Vin
Input supply voltage
Nominal operating range: 7V to 42V
SYNC
Oscillator synchronization input or output The internal oscillator can be synchronized to an external
clock with an external pull-down device. Multiple LM25005
devices can be synchronized together by connection of their
SYNC pins.
6
7
8
COMP
FB
Output of the internal error amplifier
The loop compensation network should be connected
between this pin and the FB pin.
Feedback signal from the regulated
output
This pin is connected to the inverting input of the internal
error amplifier. The regulation threshold is 1.225V.
RT
Internal oscillator frequency set input
The internal oscillator is set with a single resistor, connected
between this pin and the AGND pin. The recommended
frequency range is 50KHz to 500KHz.
9
RAMP
Ramp control signal
An external capacitor connected between this pin and the
AGND pin sets the ramp slope used for current mode
control. Recommended capacitor range 50pF to 2000pF.
10
11
AGND
SS
Analog ground
Soft-start
Internal reference for the regulator control functions
An external capacitor and an internal 10µA current source
set the time constant for the rise of the error amp reference.
The SS pin is held low during standby, Vcc UVLO and
thermal shutdown.
12
OUT
Output voltage connection
Power ground
Connect directly to the regulated output voltage.
13, 14
PGND
Low side reference for the PRE switch and the IS sense
resistor.
15, 16
IS
Current sense
Current measurement connection for the re-circulating
diode. An internal sense resistor and a sample/hold circuit
sense the diode current near the conclusion of the off-time.
This current measurement provides the DC level of the
emulated current ramp.
17, 18
19
SW
Switching node
The source terminal of the internal buck switch. The SW pin
should be connected to the external Schottky diode and to
the buck inductor.
PRE
Pre-charge assist for the bootstrap
capacitor
This open drain output can be connected to SW pin to aid
charging the bootstrap capacitor during very light load
conditions or in applications where the output may be pre-
charged before the LM25005 is enabled. An internal pre-
charge MOSFET is turned on for 250ns each cycle just prior
to the on-time interval of the buck switch.
3
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Pin(S)
Name
Description
Application Information
20
BST
Boost input for bootstrap capacitor
An external capacitor is required between the BST and the
SW pins. A 0.022µF ceramic capacitor is recommended.
The capacitor is charged from Vcc via an internal diode
during the off-time of the buck switch.
NA
EP
Exposed Pad
Exposed metal pad on the underside of the device. It is
recommended to connect this pad to the PWB ground plane,
in order to aid in heat dissipation.
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BST to SW
OUT to GND
SD, SYNC, SS, FB to GND
ESD Rating (Note 2)
Human Body Model
Storage Temperature Range
14V
Limited to Vin
7V
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
2kV
VIN to GND
45V
60V
45V
-1.5V
45V
14V
-65°C to +150°C
BST to GND
PRE to GND
Operating Ratings (Note 1)
VIN
SW to GND (Steady State)
BST to VCC
7V to 42V
−40°C to + 125°C
Operation Junction Temperature
VCC to GND
Electrical Characteristics Specifications with standard typeface are for TJ = 25°C, and those with boldface type
apply over full Operating Junction Temperature range. VIN = 24V, RT = 32.4kΩ unless otherwise stated. (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
STARTUP REGULATOR
VccReg
Vcc Regulator Output
Vcc LDO Mode turn-off
6.85
7.15
9
7.45
V
V
Vcc Current Limit
Vcc = 0V
20
mA
VCC SUPPLY
Vcc UVLO Threshold
Vcc Undervoltage Hysteresis
Bias Current (Iin)
(Vcc increasing)
5.95
6.35
1
6.75
V
V
FB = 1.3V
SD = 0V
3
4.5
85
mA
µA
Shutdown Current (Iin)
50
SHUTDOWN THRESHOLDS
Shutdown Threshold
(SD Increasing)
0.5
0.7
0.1
0.9
V
V
Shutdown Hysteresis
Standby Threshold
(Standby Increasing)
1.18
1.225
0.1
1.27
V
Standby Hysteresis
V
SD Pull-up Current Source
5
µA
SWITCH CHARACTERSICS
Buck Switch Rds(on)
BOOST UVLO
160
3.8
320
mΩ
V
BOOST UVLO Hysteresis
Pre-charge Switch Rds(on)
Pre-charge Switch on-time
0.56
75
V
Ω
ns
275
CURRENT LIMIT
Cycle by Cycle Current Limit
RAMP = 0V
3
7
3.5
4.25
14
A
Cycle by Cycle Current Limit Delay
RAMP = 2.5V
100
ns
SOFT-START
OSCILLATOR
SS Current Source
10
µA
Frequency1
180
425
200
485
10
220
525
KHz
KHz
Frequency2
RT = 11kΩ
SYNC Source Impedance
SYNC Sink Impedance
SYNC Threshold (falling)
Upper SYNC Frequency
SYNC Pulse Width Minimum
kΩ
160
1.4
Ω
V
550
KHz
ns
15
5
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Symbol
Parameter
Conditions
Min
Typ
Max
Units
RAMP GENERATOR
Ramp Current 1
Ramp Current 2
PWM COMPARATOR
Vin = 36V, Vout=10V
Vin = 10V, Vout=10V
136
18
160
25
184
32
µA
µA
Forced Off-time
Min On-time
500
80
ns
ns
V
COMP to PWM Comparator Offset
ERROR AMPLIFIER
0.7
Feedback Voltage
FB Bias Current
Vfb = COMP
1.207
3
1.225
10
1.243
V
nA
DC Gain
70
dB
COMP Sink / Source Current
Unity Gain Bandwidth
mA
MHz
3
THERMAL SHUTDOWN
Tsd
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
165
25
°C
°C
THERMAL RESISTANCE
Junction to Case
Junction to Ambient
4
°C/W
°C/W
θJC
θJA
40
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Typical Performance Characteristics
Oscillator Frequency vs RT
Oscillator Frequency vs Temperature
FOSC = 200kHz
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20170021
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Soft Start Current vs Temperature
VCC vs ICC
VIN = 12V
20170022
20170023
VCC vs VIN
RL = 7kΩ
Error Amplifier Gain/Phase
AVCL = 101
20170024
20170025
Demoboard Efficiency vs IOUT and VIN
20170026
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Typical Application Circuit and Block Diagram
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PWM controller and boot-strap MOSFET gate driver. The in-
put pin (Vin) can be connected directly to the input voltage,
as high as 42 Volts. For input voltages below 9V, a low
dropout switch connects Vcc directly to Vin. In this supply
range, Vcc is approximately equal to Vin. For Vin voltage
greater than 9V, the low dropout switch is disabled and the
Vcc regulator is enabled to maintain Vcc at approximately 7V.
The wide operating range of 7V to 42V is achieved through
the use of this dual mode regulator.
Detailed Operating Description
The LM25005 switching regulator features all of the functions
necessary to implement an efficient high voltage buck regu-
lator using a minimum of external components. This easy to
use regulator integrates a 42V N-Channel buck switch with
an output current capability of 2.5 Amps. The regulator control
method is based on current mode control utilizing an emulat-
ed current ramp. Peak current mode control provides inherent
line voltage feed-forward, cycle-by-cycle current limiting, and
ease of loop compensation. The use of an emulated control
ramp reduces noise sensitivity of the pulse-width modulation
circuit, allowing reliable processing of very small duty cycles
necessary in high input voltage applications. The operating
frequency is user programmable from 50kHz to 500kHz. An
oscillator synchronization pin allows multiple LM25005 regu-
lators to self synchronize or be synchronized to an external
clock. The output voltage can be set as low as 1.225V. Fault
protection features include, current limiting, thermal shutdown
and remote shutdown capability. The device is available in the
TSSOP-20 package featuring an exposed pad to aid thermal
dissipation.
The output of the Vcc regulator is current limited to 20mA.
Upon power up, the regulator sources current into the capac-
itor connected to the Vcc pin. When the voltage at the Vcc pin
exceeds the Vcc UVLO threshold of 6.3V and the SD pin is
greater than 1.225V, the output switch is enabled and a soft-
start sequence begins. The output switch remains enabled
until Vcc falls below 5.3V or the SD pin falls below 1.125V.
An auxiliary supply voltage can be applied to the Vcc pin to
reduce the IC power dissipation. If the auxiliary voltage is
greater than 7.3V, the internal regulator will essentially
shut off, reducing the IC power dissipation. The Vcc regulator
series pass transistor includes a diode between Vcc and Vin
that should not be forward biased in normal operation. There-
fore the auxiliary Vcc voltage should never exceed the Vin
voltage.
The functional block diagram and typical application of the
LM25005 are shown in Figure 1. The LM25005 can be applied
in numerous applications to efficiently step-down a high, un-
regulated input voltage. The device is well suited for telecom,
industrial and automotive power bus voltage ranges.
In high voltage applications extra care should be taken to en-
sure the Vin pin does not exceed the absolute maximum
voltage rating of 45V. During line or load transients, voltage
ringing on the Vin line that exceeds the Absolute Maximum
Ratings can damage the IC. Both careful PC board layout and
the use of quality bypass capacitors located close to the Vin
and GND pins are essential.
High Voltage Start-Up Regulator
The LM25005 contains a dual-mode internal high voltage
startup regulator that provides the Vcc bias supply for the
20170004
FIGURE 2. Vin and Vcc Sequencing
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Shutdown / Standby
The LM25005 contains a dual level Shutdown (SD) circuit.
When the SD pin voltage is below 0.7V, the regulator is in a
low current shutdown mode. When the SD pin voltage is
greater than 0.7V but less than 1.225V, the regulator is in
standby mode. In standby mode the Vcc regulator is active
but the output switch is disabled. When the SD pin voltage
exceeds 1.225V, the output switch is enabled and normal op-
eration begins. An internal 5µA pull-up current source config-
ures the regulator to be fully operational if the SD pin is left
open.
An external set-point voltage divider from Vin to GND can be
used to set the operational input range of the regulator. The
divider must be designed such that the voltage at the SD pin
will be greater than 1.225V when Vin is in the desired oper-
ating range. The internal 5µA pull-up current source must be
included in calculations of the external set-point divider. Hys-
teresis of 0.1V is included for both the shutdown and standby
thresholds. The voltage at the SD pin should never exceed
8V. When using an external set-point divider, it may be nec-
essary to clamp the SD pin to limit its voltage at high input
voltage conditions.
20170006
FIGURE 4. Sync from Multiple Devices
Multiple LM25005 and/or LM5005 devices can be synchro-
nized together simply by connecting the SYNC pins together.
In this configuration all of the devices will be synchronized to
the highest frequency device. The diagram in Figure 5 illus-
trates the SYNC input/output features of the LM25005. The
internal oscillator circuit drives the SYNC pin with a strong
pull-down / weak pull-up inverter. When the SYNC pin is
pulled low either by the internal oscillator or an external clock,
the ramp cycle of the oscillator is terminated and a new os-
cillator cycle begins. Thus, if the SYNC pins of several
LM25005 IC’s are connected together, the IC with the highest
internal clock frequency will pull the connected SYNC pins low
first and terminate the oscillator ramp cycles of the other IC’s.
The LM25005 or LM5005 with the highest programmed clock
frequency will serve as the master and control the switching
frequency of the all the devices with lower oscillator frequen-
cy.
The SD pin can also be used to implement various remote
enable / disable functions. Pulling the UVLO pin below the
0.7V threshold totally disables the controller. If the SD pin
voltage is above 1.225V the regulator will be operational.
Oscillator and Sync Capability
The LM25005 oscillator frequency is set by a single external
resistor connected between the RT pin and the AGND pin.
The RT resistor should be located very close to the device and
connected directly to the pins of the IC (RT and AGND).To
set a desired oscillator frequency (F), the necessary value for
the RT resistor can be calculated from the following equation:
The SYNC pin can be used to synchronize the internal oscil-
lator to an external clock. The external clock must be of
higher frequency than the free-running frequency set by the
RT resistor. A clock circuit with an open drain output is the
recommended interface from the external clock to the SYNC
pin. The clock pulse duration should be greater than 15 ns.
20170005
FIGURE 3. Sync from External Clock
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20170007
FIGURE 5. Simplified Oscillator Block Diagram and SYNC I/O Circuit
Error Amplifier and PWM
Comparator
RAMP Generator
The ramp signal used in the pulse width modulator for current
mode control is typically derived directly from the buck switch
current. This switch current corresponds to the positive slope
portion of the output inductor current. Using this signal for the
PWM ramp simplifies the control loop transfer function to a
single pole response and provides inherent input voltage
feed-forward compensation. The disadvantage of using the
buck switch current signal for PWM control is the large leading
edge spike due to circuit parasitics that must be filtered or
blanked. Also, the current measurement may introduce sig-
nificant propagation delays. The filtering, blanking time and
propagation delay limit the minimum achievable pulsewidth.
In applications where the input voltage may be relatively large
in comparison to the output voltage, controlling small
pulsewidths and duty cycles is necessary for regulation. The
LM25005 utilizes a unique ramp generator, which does not
actually measure the buck switch current but rather recon-
structs the signal. Reconstructing or emulating the inductor
current provides a ramp signal to the PWM comparator that
is free of leading edge spikes and measurement or filtering
delays. The current reconstruction is comprised of two ele-
ments; a sample & hold DC level and an emulated current
ramp.
The internal high gain error amplifier generates an error signal
proportional to the difference between the regulated output
voltage and an internal precision reference (1.225V). The
output of the error amplifier is connected to the COMP pin
allowing the user to provide loop compensation components,
generally a type II network, as illustrated in Figure 1. This
network creates a pole at DC, a zero and a noise reducing
high frequency pole. The PWM comparator compares the
emulated current sense signal from the RAMP generator to
the error amplifier output voltage at the COMP pin.
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20170008
FIGURE 6. Composition of Current Sense Signal
The Sample and Hold DC level illustrated in Figure 6. is de-
rived from a measurement of the re-circulating Schottky diode
anode current. The re-circulating diode anode should be con-
nected to the IS pin. The diode current flows through an
internal current sense resistor between the IS and PGND
pins. The voltage level across the sense resistor is sampled
and held just prior to the onset of the next conduction interval
of the buck switch. The diode current sensing and sample &
hold provide the dc level of the reconstructed current signal.
The positive slope inductor current ramp is emulated by an
external capacitor connected from the RAMP pin to AGND
and an internal voltage controlled current source. The ramp
current source that emulates the inductor current is a function
of the Vin and Vout voltages per the following equation:
oscillation is normally characterized by observing alternating
wide and narrow pulses at the switch node. Adding a fixed
slope voltage ramp (slope compensation) to the current sense
signal prevents this oscillation. The 25µA of offset current
provided from the emulated current source adds some fixed
slope to the ramp signal. In some high output voltage, high
duty cycle applications, additional slope may be required. In
these applications, a pull-up resistor may be added between
the VCC and RAMP pins to increase the ramp slope compen-
sation.
For VOUT > 7.5V:
Calculate optimal slope current, IOS = VOUT x 5µA/V.
For example, at VOUT = 10V, IOS = 50µA.
Install a resistor from the RAMP pin to VCC
RRAMP = VCC / (IOS - 25µA)
:
IRAMP = (5µ x (Vin – Vout)) + 25µA
Proper selection of the RAMP capacitor depends upon the
selected value of the output inductor. The value of CRAMP can
be selected from: CRAMP = L x 10-5, where L is the value of
the output inductor in Henrys. With this value, the scale factor
of the emulated current ramp will be approximately equal to
the scale factor of the dc level sample and hold ( 0.5 V / A).
The CRAMP capacitor should be located very close to the de-
vice and connected directly to the pins of the IC (RAMP and
AGND).
20170035
For duty cycles greater than 50%, peak current mode control
circuits are subject to sub-harmonic oscillation. Sub-harmonic
FIGURE 7. RRAMP to VCC for VOUT > 7.5V
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Current Limit
Boost Pin
The LM25005 contains a unique current monitoring scheme
for control and over-current protection. When set correctly,
the emulated current sense signal provides a signal which is
proportional to the buck switch current with a scale factor of
0.5 V / A. The emulated ramp signal is applied to the current
limit comparator. If the emulated ramp signal exceeds 1.75V
(3.5A) the present current cycle is terminated (cycle-by-cycle
current limiting). In applications with small output inductance
and high input voltage the switch current may overshoot due
to the propagation delay of the current limit comparator. If an
overshoot should occur, the diode current sampling circuit will
detect the excess inductor current during the off-time of the
buck switch. If the Sample and Hold DC Level exceeds the
1.75V current limit threshold, the buck switch will be disabled
and skip pulses until the diode current sampling circuit detects
the inductor current has decayed below the current limit
threshold. This approach prevents current runaway condi-
tions due to propagation delays or inductor saturation since
the inductor current is forced to decay following any current
overshoot.
The LM25005 integrates an N-Channel buck switch and as-
sociated floating high voltage level shift / gate driver. This gate
driver circuit works in conjunction with an internal diode and
an external bootstrap capacitor. A 0.022µF ceramic capacitor,
connected with short traces between the BST pin and SW pin,
is recommended. During the off-time of the buck switch, the
SW pin voltage is approximately - 0.5V and the bootstrap ca-
pacitor is charged from Vcc through the internal bootstrap
diode. When operating with a high PWM duty cycle, the buck
switch will be forced off each cycle for 500ns to ensure that
the bootstrap capacitor is recharged.
Under very light load conditions or when the output voltage is
pre-charged, the SW voltage will not remain low during the
off-time of the buck switch. If the inductor current falls to zero
and the SW pin rises, the bootstrap capacitor will not receive
sufficient voltage to operate the buck switch gate driver. For
these applications, the PRE pin can be connected to the SW
pin to pre-charge the bootstrap capacitor. The internal pre-
charge MOSFET and diode connected between the PRE pin
and PGND turns on each cycle for 250ns just prior to the onset
of a new switching cycle. If the SW pin is at a normal negative
voltage level (continuous conduction mode), then no current
will flow through the pre-charge MOSFET/diode.
Soft-Start
The soft-start feature allows the regulator to gradually reach
the initial steady state operating point, thus reducing start-up
stresses and surges. The internal soft-start current source,
set to 10µA, gradually increases the voltage of an external
soft-start capacitor connected to the SS pin. The soft-start
capacitor voltage is connected to the reference input of the
error amplifier. Various sequencing and tracking schemes
can be implemented using external circuits that limit or clamp
the voltage level of the SS pin.
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the
integrated circuit in the event the maximum junction temper-
ature is exceeded. When activated, typically at 165 degrees
Celsius, the controller is forced into a low power reset state,
disabling the output driver and the bias regulator. This feature
is provided to prevent catastrophic failures from accidental
device overheating.
In the event a fault is detected (over-temperature, Vcc UVLO,
SD) the soft-start capacitor will be discharged. When the fault
condition is no longer present a new soft-start sequence will
commence.
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The selected inductor (see Table 1) has a conservative 6.2
Amp saturation current rating. For this manufacturer, the sat-
uration rating is defined as the current necessary for the
inductance to reduce by 30%, at 20°C.
Application Information
EXTERNAL COMPONENTS
The procedure for calculating the external components is il-
lustrated with the following design example. The Bill of Mate-
rials for this design is listed in Table1. The circuit shown in
Figure 1 is configured for the following specifications:
C3 (CRAMP
)
With the inductor value selected, the value of C3 (CRAMP
necessary for the emulation ramp circuit is:
)
•
•
•
•
•
VOUT = 5V
VIN = 7V to 42V
Fs = 300 KHz
Minimum load current (for CCM) = 250 mA
Maximum load current = 2.5A
CRAMP = L x 10-5
Where L is in Henrys
With L1 selected for 33µH the recommended value for C3 is
330pF.
R3 (RT)
RT sets the oscillator switching frequency. Generally, higher
frequency applications are smaller but have higher losses.
Operation at 300KHz was selected for this example as a rea-
sonable compromise for both small size and high efficiency.
The value of RT for 300KHz switching frequency can be cal-
culated as follows:
C9, C10
The output capacitors C9, and C10, smooth the inductor rip-
ple current and provide a source of charge for transient load-
ing conditions. For this design a 22µF ceramic capacitor and
a 150µF SP organic capacitor were selected. The ceramic
capacitor provides ultra low ESR to reduce the output ripple
voltage and noise spikes, while the SP capacitor provides a
large bulk capacitance in a small volume for transient loading
conditions. An approximation for the output ripple voltage is:
The nearest standard value of 21 kΩ was chosen for RT.
L1
The inductor value is determined based on the operating fre-
quency, load current, ripple current, and the minimum and
maximum input voltage (VIN(min), VIN(max)).
D1
A Schottky type re-circulating diode is required for all
LM25005 applications. Ultra-fast diodes are not recommend-
ed and may result in damage to the IC due to reverse recovery
current transients. The near ideal reverse recovery charac-
teristics and low forward voltage drop are particularly impor-
tant diode characteristics for high input voltage and low output
voltage applications common to the LM25005. The reverse
recovery characteristic determines how long the current
surge lasts each cycle when the buck switch is turned on. The
reverse recovery characteristics of Schottky diodes minimize
the peak instantaneous power in the buck switch occurring
during turn-on each cycle. The resulting switching losses of
the buck switch are significantly reduced when using a Schot-
tky diode. The reverse breakdown rating should be selected
for the maximum VIN, plus some safety margin.
20170010
FIGURE 8. Inductor Current Waveform
To keep the circuit in continuous conduction mode (CCM), the
maximum ripple current IRIPPLE should be less than twice the
minimum load current, or 0.5 Ap-p. Using this value of ripple
current, the value of inductor (L1) is calculated using the fol-
lowing:
The forward voltage drop has a significant impact on the con-
version efficiency, especially for applications with a low output
voltage. “Rated” current for diodes vary widely from various
manufactures. The worst case is to assume a short circuit
load condition. In this case the diode will carry the output cur-
rent almost continuously. For the LM25005 this current can
be as high as 3.5A. Assuming a worst case 1V drop across
the diode, the maximum diode power dissipation can be as
high as 3.5W. For the reference design a 60V Schottky in a
DPAK package was selected.
C1, C2
The regulator supply voltage has a large source impedance
at the switching frequency. Good quality input capacitors are
necessary to limit the ripple voltage at the VIN pin while sup-
plying most of the switch current during the on-time. When the
buck switch turns on, the current into the VIN pin steps to the
lower peak of the inductor current waveform, ramps up to the
peak value, then drops to zero at turn-off. The average current
into VIN during the on-time is the load current. The input ca-
This procedure provides a guide to select the value of L1. The
nearest standard value (33 µH) will be used. L1 must be rated
for the peak current (IPK+) to prevent saturation. During normal
loading conditions, the peak current occurs at maximum load
current plus maximum ripple. During an overload condition
the peak current is limited to 3.5A nominal (4.25A maximum).
www.national.com
14
pacitance should be selected for RMS current rating and
minimum ripple voltage. A good approximation for the re-
quired ripple current rating necessary is IRMS > IOUT / 2.
components can be omitted. With the SD pin open circuit the
LM25005 responds once the Vcc UVLO threshold is satisfied.
R7, C11
Quality ceramic capacitors with a low ESR should be selected
for the input filter. To allow for capacitor tolerances and volt-
age effects, two 2.2 µF, 100V ceramic capacitors will be used.
If step input voltage transients are expected near the maxi-
mum rating of the LM25005, a careful evaluation of ringing
and possible spikes at the device VIN pin should be complet-
ed. An additional damping network or input voltage clamp
may be required in these cases.
A snubber network across the power diode reduces ringing
and spikes at the switching node. Excessive ringing and
spikes can cause erratic operation and couple spikes and
noise to the output. In the limit, spikes beyond the rating of
the LM25005 or the re-circulating diode can damage these
devices. Selecting the values for the snubber is best accom-
plished through empirical methods. First, make sure the lead
lengths for the snubber connections are very short. For the
current levels typical for the LM25005 a resistor value be-
tween 5 and 20 Ohms is adequate. Increasing the value of
the snubber capacitor results in more damping but higher
losses. Select a minimum value of C11 that provides ade-
quate damping of the SW pin waveform at high load.
C8
The capacitor at the VCC pin provides noise filtering and sta-
bility for the VCC regulator. The recommended value of C8
should be no smaller than 0.1 µF, and should be a good qual-
ity, low ESR, ceramic capacitor. A value of 0.47 µF was
selected for this design.
R4, C5, C6
C7
These components configure the error amplifier gain charac-
teristics to accomplish a stable overall loop gain. One advan-
tage of current mode control is the ability to close the loop with
only two feedback components, R4 and C5. The overall loop
gain is the product of the modulator gain and the error ampli-
fier gain. The DC modulator gain of the LM25005 is as follows:
The bootstrap capacitor between the BST and the SW pins
supplies the gate current to charge the buck switch gate at
turn-on. The recommended value of C7 is 0.022 µF, and
should be a good quality, low ESR, ceramic capacitor.
C4
The capacitor at the SS pin determines the soft-start time, i.e.
the time for the reference voltage and the output voltage, to
reach the final regulated value. The time is determined from:
DC Gain(MOD) = Gm(MOD) x RLOAD = 2 x RLOAD
The dominant low frequency pole of the modulator is deter-
mined by the load resistance (RLOAD,) and output capacitance
(COUT). The corner frequency of this pole is:
fp(MOD) = 1 / (2π RLOAD COUT
)
For this application, a C4 value of 0.01 µF was chosen which
corresponds to a soft-start time of 1 ms.
For RLOAD = 5 Ω and COUT = 177 µF then fp(MOD) = 180Hz
DC Gain(MOD) = 2 x 5 = 10 = 20 dB
R5, R6
R5 and R6 set the output voltage level, the ratio of these re-
sistors is calculated from:
For the design example of Figure 1 the following modulator
gain vs. frequency characteristic was measured as shown in
Figure 9.
R5/R6 = (VOUT / 1.225V) - 1
For a 5V output, the R5/R6 ratio calculates to 3.082. The re-
sistors should be chosen from standard value resistors, a
good starting point is selection in the range of 1.0 kΩ - 10
kΩ. Values of 5.11 kΩ for R5, and 1.65 kΩ for R6 were se-
lected.
R1, R2, C12
A voltage divider can be connected to the SD pin to set a
minimum operating voltage Vin(min) for the regulator. If this
feature is required, the easiest approach to select the divider
resistor values is to select a value for R1 (between 10 kΩ and
100 kΩ recommended) then calculate R2 from:
Capacitor C12 provides filtering for the divider. The voltage at
the SD pin should never exceed 8V, when using an external
set-point divider it may be necessary to clamp the SD pin at
high input voltage conditions. The reference design utilizes
the full range of the LM25005 (7V to 42V); therefore these
20170015
FIGURE 9. Gain and Phase of Modulator
RLOAD = 5 Ohms and COUT = 177 µF
15
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Components R4 and C5 configure the error amplifier as a type
II configuration which has a pole at DC and a zero at fZ = 1 /
(2πR4C5). The error amplifier zero cancels the modulator
pole leaving a single pole response at the crossover frequen-
cy of the loop gain. A single pole response at the crossover
frequency yields a very stable loop with 90 degrees of phase
margin.
For the design example, a target loop bandwidth (crossover
frequency) of 20 kHz was selected. The compensation net-
work zero (fZ) should be selected at least an order of magni-
tude less than the target crossover frequency. This constrains
the product of R4 and C5 for a desired compensation network
zero 1 / (2π R4 C5) to be less than 2kHz. Increasing R4 while
proportionally decreasing C5, increases the error amp gain.
Conversely, decreasing R4 while proportionally increasing
C5, decreases the error amp gain. For the design example
C5 was selected for 0.01µF and R4 was selected for 49.9
kΩ. These values configure the compensation network zero
at 320 Hz. The error amp gain at frequencies greater than fZ
is: R4 / R5, which is approximately 10 (20dB).
20170017
FIGURE 11. Overall Loop Gain and Phase
If a network analyzer is available, the modulator gain can be
measured and the error amplifier gain can be configured for
the desired loop transfer function. If a network analyzer is not
available, the error amplifier compensation components can
be designed with the guidelines given. Step load transient
tests can be performed to verify acceptable performance. The
step load goal is minimum overshoot with a damped re-
sponse. C6 can be added to the compensation network to
decrease noise susceptibility of the error amplifier. The value
of C6 must be sufficiently small since the addition of this ca-
pacitor adds a pole in the error amplifier transfer function. This
pole must be well beyond the loop crossover frequency. A
good approximation of the location of the pole added by C6
is: fp2 = fz x C5 / C6.
BIAS POWER DISSIPATION REDUCTION
Buck regulators operating with high input voltage can dissi-
pate an appreciable amount of power for the bias of the IC.
The VCC regulator must step-down the input voltage VIN to a
nominal VCC level of 7V. The large voltage drop across the
VCC regulator translates into a large power dissipation within
the Vcc regulator. There are several techniques that can sig-
nificantly reduce this bias regulator power dissipation. Figure
12 and Figure 13 depict two methods to bias the IC from the
output voltage. In each case the internal Vcc regulator is used
to initially bias the VCC pin. After the output voltage is estab-
lished, the VCC pin potential is raised above the nominal 7V
regulation level, which effectively disables the internal VCC
regulator. The voltage applied to the VCC pin should never
exceed 14V. The VCC voltage should never be larger than the
VIN voltage.
20170016
FIGURE 10. Error Amplifier Gain and Phase
The overall loop can be predicted as the sum (in dB) of the
modulator gain and the error amp gain.
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16
20170018
FIGURE 12. VCC Bias from VOUT for 8V < VOUT < 14V
20170019
FIGURE 13. VCC Bias with Additional Winding on the Output Inductor
17
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PCB LAYOUT AND THERMAL CONSIDERATIONS
The two highest power dissipating components are the re-
circulating diode and the LM25005 regulator IC. The easiest
method to determine the power dissipated within the
LM25005 is to measure the total conversion losses (Pin –
Pout) then subtract the power losses in the Schottky diode,
output inductor and snubber resistor. An approximation for
the Schottky diode loss is P = (1-D) x Iout x Vfwd. An approx-
imation for the output inductor power is P = IOUT2 x R x 1.1,
where R is the DC resistance of the inductor and the 1.1 factor
is an approximation for the ac losses. If a snubber is used, the
power loss can be estimated with an oscilloscope by obser-
vation of the resistor voltage drop at both turn-on and turn-off
transitions. The regulator has an exposed thermal pad to aid
power dissipation. Adding several vias under the device to the
ground plane will greatly reduce the regulator junction tem-
perature. Selecting a diode with an exposed pad will aid the
power dissipation of the diode.
The circuit in Figure 1 serves as both a block diagram of the
LM25005 and a typical application board schematic for the
LM25005. In a buck regulator there are two loops where cur-
rents are switched very fast. The first loop starts from the input
capacitors, to the regulator VIN pin, to the regulator SW pin,
to the inductor then out to the load. The second loop starts
from the output capacitor ground, to the regulator PGND pins,
to the regulator IS pins, to the diode anode, to the inductor
and then out to the load. Minimizing the loop area of these
two loops reduces the stray inductance and minimizes noise
and possible erratic operation. A ground plane in the PC
board is recommended as a means to connect the input filter
capacitors to the output filter capacitors and the PGND pins
of the regulator. Connect all of the low power ground connec-
tions (CSS, RT, CRAMP) directly to the regulator AGND pin.
Connect the AGND and PGND pins together through the top-
side copper area covering the entire underside of the device.
Place several vias in this underside copper area to the ground
plane.
TABLE 1. 5V, 2.5A Demo Board Bill of Materials
ITEM
PART NUMBER DESCRIPTION
VALUE
C
C
C
C
C
C
C
C
C
C
C
C
D
1
C4532X7R2A225M
C4532X7R2A225M
C0805C331G1GAC
C2012X7R2A103K
C2012X7R2A103K
OPEN
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, CER, KEMET
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
NOT USED
2.2µ, 100V
2.2µ, 100V
330p, 100V
0.01µ, 100V
0.01µ, 100V
2
3
4
5
6
7
C2012X7R2A223K
C2012X7R1C474M
C3225X7R1C226M
EEFHE0J151R
C0805C331G1GAC
OPEN
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, CER, TDK
CAPACITOR, SP, PANASONIC
CAPACITOR, CER, KEMET
NOT USED
0.022µ, 100V
0.47µ, 16V
22µ, 16V
8
9
10
11
12
1
150µ, 6.3V
330p, 100V
CSHD6-60C
DIODE, 60V, CENTRAL
DIODE, 100V, IR (D1-ALT)
INDUCTOR, COOPER
NOT USED
6CWQ10FN
L
1
1
2
3
4
5
6
7
1
DR127-330
33µH
R
R
R
R
R
R
R
U
OPEN
OPEN
NOT USED
CRCW08052102F
CRCW08054992F
CRCW08055111F
CRCW08051651F
CRCW2512100J
LM25005
RESISTOR
21K
49.9K
5.11K
1.65K
10, 1W
RESISTOR
RESISTOR
RESISTOR
RESISTOR
REGULATOR, NATIONAL SEMICONDUCTOR
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18
PCB Layout
20170029
20170030
20170031
Component Side
Solder Side
Silkscreen
19
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead TSSOP Package
NS Package Number MXA20A
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20
Notes
21
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Notes
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