LM2524DMDC [NSC]
暂无描述;
| 型号： | LM2524DMDC |
| 厂家： | 
National Semiconductor |
| 描述： | 暂无描述 脉冲 |
| 文件： | 总22页 (文件大小：1167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2005
LM2524D/LM3524D
Regulating Pulse Width Modulator
one pulse per period even in noisy environments. The
LM3524D includes double pulse suppression logic that in-
sures when a shut-down condition is removed the state of
the T-flip-flop will change only after the first clock pulse has
arrived. This feature prevents the same output from being
pulsed twice in a row, thus reducing the possibility of core
saturation in push-pull designs.
General Description
The LM3524D family is an improved version of the industry
standard LM3524. It has improved specifications and addi-
tional features yet is pin for pin compatible with existing 3524
families. New features reduce the need for additional exter-
nal circuitry often required in the original version.
The LM3524D has a 1% precision 5V reference. The cur-
rent carrying capability of the output drive transistors has
been raised to 200 mA while reducing VCEsat and increasing
VCE breakdown to 60V. The common mode voltage range of
the error-amp has been raised to 5.5V to eliminate the need
for a resistive divider from the 5V reference.
Features
n Fully interchangeable with standard LM3524 family
n
1% precision 5V reference with thermal shut-down
n Output current to 200 mA DC
n 60V output capability
In the LM3524D the circuit bias line has been isolated from
the shut-down pin. This prevents the oscillator pulse ampli-
tude and frequency from being disturbed by shut-down. Also
at high frequencies (.300 kHz) the max. duty cycle per
output has been improved to 44% compared to 35% max.
duty cycle in other 3524s.
n Wide common mode input range for error-amp
n One pulse per period (noise suppression)
n Improved max. duty cycle at high frequencies
n Double pulse suppression
n Synchronize through pin 3
In addition, the LM3524D can now be synchronized exter-
nally, through pin 3. Also a latch has been added to insure
Connection Diagram
00865002
Top View
Order Number LM2524DN or LM3524DN
See NS Package Number N16E
Order Number LM3524DM
See NS Package Number M16A
© 2005 National Semiconductor Corporation
DS008650
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Block Diagram
00865001
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2
Absolute Maximum Ratings (Note 5)
Internal Power Dissipation
Operating Junction Temperature
Range (Note 2)
1W
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
LM2524D
−40˚C to +125˚C
0˚C to +125˚C
150˚
Supply Voltage
40V
LM3524D
Collector Supply Voltage
(LM2524D)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering 4 sec.)
M, N Pkg.
55V
40V
−65˚C to +150˚C
(LM3524D)
Output Current DC (each)
Oscillator Charging Current (Pin 7)
200 mA
5 mA
260˚C
Electrical Characteristics
(Note 1)
LM2524D
Tested
Limit
LM3524D
Symbol
Parameter
Conditions
Design
Limit
Tested
Limit
Design
Limit
Units
Typ
Typ
(Note 3) (Note 4)
(Note 3) (Note 4)
REFERENCE SECTION
VREF
Output Voltage
5
4.85
5.15
15
4.80
5.20
30
5
4.75
5.25
VMin
VMax
mVMax
mVMax
dB
VRLine
VRLoad
Line Regulation
Load Regulation
Ripple Rejection
VIN = 8V to 40V
10
10
66
10
10
66
25
25
50
50
IL = 0 mA to 20 mA
f = 120 Hz
15
25
IOS
Short Circuit
Current
VREF = 0
25
25
mA Min
50
50
180
200
mA Max
µVrms Max
mV/kHr
NO
Output Noise
Long Term
Stability
10 Hz ≤ f ≤ 10 kHz
40
20
100
500
40
20
100
TA = 125˚C
OSCILLATOR SECTION
fOSC
Max. Freq.
RT = 1k, CT = 0.001 µF
(Note 7)
550
20
350
20
kHzMin
kHzMin
fOSC
Initial
RT = 5.6k, CT = 0.01 µF
(Note 7)
17.5
17.5
Accuracy
22.5
34
22.5
30
kHzMax
kHzMin
RT = 2.7k, CT = 0.01 µF
(Note 7)
38
38
42
1
46
kHzMax
∆fOSC
∆fOSC
Freq. Change
with VIN
VIN = 8 to 40V
0.5
0.5
1.0
%
Max
Freq. Change
with Temp.
TA = −55˚C to +125˚C
at 20 kHz RT = 5.6k,
CT = 0.01 µF
5
5
3
%
VOSC
tPW
Output Amplitude
(Pin 3) (Note 8)
Output Pulse
Width (Pin 3)
Sawtooth Peak
Voltage
RT = 5.6k, CT = 0.01 µF
3
2.4
1.5
3.6
2.4
1.5
3.8
VMin
µsMax
VMax
RT = 5.6k, CT = 0.01 µF
RT = 5.6k, CT = 0.01 µF
0.5
3.4
0.5
3.8
3
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Electrical Characteristics (Continued)
(Note 1)
LM2524D
Tested
Limit
LM3524D
Tested
Limit
Symbol
Parameter
Conditions
Design
Limit
Design
Limit
Units
Typ
Typ
(Note 3) (Note 4)
(Note 3) (Note 4)
0.6
Sawtooth Valley
Voltage
RT = 5.6k, CT = 0.01 µF
1.1
0.8
0.6
VMin
ERROR-AMP SECTION
VIO
Input Offset
Voltage
VCM = 2.5V
2
1
8
8
10
10
1
2
1
10
10
1
mVMax
µAMax
µAMax
µAMin
IIB
Input Bias
Current
VCM = 2.5V
IIO
Input Offset
Current
VCM = 2.5V
0.5
1.0
65
0.5
ICOSI
Compensation
Current (Sink)
VIN(I) − VIN(NI) = 150 mV
65
95
95
125
125
µAMax
µAMin
ICOSO
Compensation
VIN(NI) − VIN(I) = 150 mV
−125
−125
Current (Source)
−95
80
−95
80
−65
74
−65
µAMax
dBMin
VMin
∞
AVOL
Open Loop Gain
Common Mode
Input Voltage
Range
RL
=
, VCM = 2.5 V
60
1.4
5.4
70
1.5
5.5
60
VCMR
1.5
5.5
VMax
CMRR
GBW
Common Mode
Rejection Ratio
Unity Gain
90
3
80
90
2
80
dBMin
MHz
AVOL = 0 dB, VCM = 2.5V
Bandwidth
∞
VO
Output Voltage
Swing
RL
=
0.5
5.5
0.5
5.5
65
VMin
VMax
dbMin
PSRR
Power Supply
Rejection Ratio
VIN = 8 to 40V
80
70
80
COMPARATOR SECTION
Minimum Duty
Pin 9 = 0.8V,
0
0
0
0
%
Max
Cycle
[RT = 5.6k, CT = 0.01 µF]
Pin 9 = 3.9V,
Maximum Duty
Cycle
49
44
45
35
49
44
45
35
%
Min
[RT = 5.6k, CT = 0.01 µF]
Pin 9 = 3.9V,
Maximum Duty
Cycle
%
Min
[RT = 1k, CT = 0.001 µF]
Zero Duty Cycle
VCOMPZ
VCOMPM
IIB
Input Threshold
(Pin 9)
1
1
V
V
Input Threshold
(Pin 9)
Maximum Duty Cycle
3.5
−1
3.5
−1
Input Bias
Current
µA
CURRENT LIMIT SECTION
VSEN
Sense Voltage
V(Pin 2) − V(Pin 1)
150 mV
≥
180
220
180
220
mVMin
mVMax
200
4
200
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Electrical Characteristics (Continued)
(Note 1)
LM2524D
Tested
Limit
LM3524D
Tested
Limit
Symbol
Parameter
Conditions
Design
Limit
Design
Limit
Units
Typ
Typ
(Note 3) (Note 4)
(Note 3) (Note 4)
TC-Vsense
Sense Voltage T.C.
Common Mode
Voltage Range
0.2
−0.7
1
0.2
−0.7
1
mV/˚C
VMin
V5 − V4 = 300 mV
VMax
SHUT DOWN SECTION
VSD
High Input
Voltage
V(Pin 2) − V(Pin 1)
150 mV
≥
1
1
0.5
1.5
1
1
0.5
1.5
VMin
VMax
mA
ISD
High Input
Current
I(pin 10)
OUTPUT SECTION (EACH OUTPUT)
VCES
Collector Emitter
IC ≤ 100 µA
55
50
40
VMin
Voltage Breakdown
ICES
Collector Leakage VCE = 60V
Current
VCE = 55V
VCE = 40V
IE = 20 mA
IE = 200 mA
IE = 50 mA
0.1
µAMax
VMax
VMin
0.1
0.2
1.5
18
50
0.7
2.5
17
VCESAT
VEO
tR
Saturation
Voltage
0.2
1.5
18
0.5
2.2
17
Emitter Output
Voltage
Rise Time
VIN = 20V,
IE = −250 µA
RC = 2k
200
100
200
100
ns
ns
tF
Fall Time
RC = 2k
SUPPLY CHARACTERISTICS SECTION
VIN
T
Input Voltage
Range
After Turn-on
8
8
VMin
VMax
˚C
40
40
Thermal Shutdown (Note 2)
Temp.
160
5
160
5
IIN
Stand By Current
VIN = 40V (Note 6)
10
10
mA
Note 1: Unless otherwise stated, these specifications apply for T = T = 25˚C. Boldface numbers apply over the rated temperature range: LM2524D is −40˚ to 85˚C
A
J
and LM3524D is 0˚C to 70˚C. V = 20V and f
= 20 kHz.
IN
OSC
Note 2: For operation at elevated temperatures, devices in the N package must be derated based on a thermal resistance of 86˚C/W, junction to ambient. Devices
in the M package must be derated at 125˚C/W, junction to ambient.
Note 3: Tested limits are guaranteed and 100% tested in production.
Note 4: Design limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage range. These limits are not used to
calculate outgoing quality level.
Note 5: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its rated operating conditions.
Note 6: Pins 1, 4, 7, 8, 11, and 14 are grounded; Pin 2 = 2V. All other inputs and outputs open.
Note 7: The value of a C capacitor can vary with frequency. Careful selection of this capacitor must be made for high frequency operation. Polystyrene was used
t
in this test. NPO ceramic or polypropylene can also be used.
Note 8: OSC amplitude is measured open circuit. Available current is limited to 1 mA so care must be exercised to limit capacitive loading of fast pulses.
5
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Typical Performance Characteristics
Switching Transistor
Peak Output Current
vs Temperature
Maximum Average Power
Dissipation (N, M Packages)
00865029
00865028
Maximum & Minimum
Duty Cycle Threshold
Voltage
Output Transistor
Saturation Voltage
00865030
00865031
Output Transistor Emitter
Voltage
Reference Transistor
Peak Output Current
00865032
00865033
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Typical Performance Characteristics (Continued)
Standby Current
vs Voltage
Standby Current
vs Temperature
00865034
00865035
Current Limit Sense Voltage
00865036
Test Circuit
00865004
7
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Functional Description
INTERNAL VOLTAGE REGULATOR
The LM3524D has an on-chip 5V, 50 mA, short circuit pro-
tected voltage regulator. This voltage regulator provides a
supply for all internal circuitry of the device and can be used
as an external reference.
For input voltages of less than 8V the 5V output should be
shorted to pin 15, VIN, which disables the 5V regulator. With
these pins shorted the input voltage must be limited to a
maximum of 6V. If input voltages of 6V–8V are to be used, a
pre-regulator, as shown in Figure 1, must be added.
00865005
FIGURE 2.
00865010
*Minimum C of 10 µF required for stability.
O
FIGURE 1.
OSCILLATOR
The LM3524D provides a stable on-board oscillator. Its fre-
quency is set by an external resistor, RT and capacitor, CT. A
graph of RT, CT vs oscillator frequency is shown is Figure 2.
The oscillator’s output provides the signals for triggering an
internal flip-flop, which directs the PWM information to the
outputs, and a blanking pulse to turn off both outputs during
transitions to ensure that cross conduction does not occur.
The width of the blanking pulse, or dead time, is controlled
by the value of CT, as shown in Figure 3. The recommended
values of RT are 1.8 kΩ to 100 kΩ, and for CT, 0.001 µF to
0.1 µF.
00865006
FIGURE 3.
ERROR AMPLIFIER
If two or more LM3524D’s must be synchronized together,
the easiest method is to interconnect all pin 3 terminals, tie
all pin 7’s (together) to a single CT, and leave all pin 6’s open
except one which is connected to a single RT. This method
works well unless the LM3524D’s are more than 6" apart.
The error amplifier is a differential input, transconductance
amplifier. Its gain, nominally 86 dB, is set by either feedback
or output loading. This output loading can be done with
either purely resistive or a combination of resistive and re-
active components. A graph of the amplifier’s gain vs output
load resistance is shown in Figure 4.
A second synchronization method is appropriate for any
circuit layout. One LM3524D, designated as master, must
have its RTCT set for the correct period. The other slave
LM3524D(s) should each have an RTCT set for a 10% longer
period. All pin 3’s must then be interconnected to allow the
master to properly reset the slave units.
The oscillator may be synchronized to an external clock
source by setting the internal free-running oscillator fre-
quency 10% slower than the external clock and driving pin 3
with a pulse train (approx. 3V) from the clock. Pulse width
should be greater than 50 ns to insure full synchronization.
00865007
FIGURE 4.
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8
CURRENT LIMITING
Functional Description (Continued)
The function of the current limit amplifier is to override the
error amplifier’s output and take control of the pulse width.
The output duty cycle drops to about 25% when a current
limit sense voltage of 200 mV is applied between the +CL
and −CLsense terminals. Increasing the sense voltage ap-
proximately 5% results in a 0% output duty cycle. Care
should be taken to ensure the −0.7V to +1.0V input common-
mode range is not exceeded.
The output of the amplifier, or input to the pulse width modu-
lator, can be overridden easily as its output impedance is
very high (ZO . 5 MΩ). For this reason a DC voltage can be
applied to pin 9 which will override the error amplifier and
force a particular duty cycle to the outputs. An example of
this could be a non-regulating motor speed control where a
variable voltage was applied to pin 9 to control motor speed.
A graph of the output duty cycle vs the voltage on pin 9 is
shown in Figure 5.
In most applications, the current limit sense voltage is pro-
duced by a current through a sense resistor. The accuracy of
this measurement is limited by the accuracy of the sense
resistor, and by a small offset current, typically 100 µA,
flowing from +CL to −CL.
The duty cycle is calculated as the percentage ratio of each
output’s ON-time to the oscillator period. Paralleling the out-
puts doubles the observed duty cycle.
OUTPUT STAGES
The outputs of the LM3524D are NPN transistors, capable of
a maximum current of 200 mA. These transistors are driven
180˚ out of phase and have non-committed open collectors
and emitters as shown in Figure 6.
00865009
00865008
FIGURE 6.
FIGURE 5.
The amplifier’s inputs have a common-mode input range of
1.5V–5.5V. The on board regulator is useful for biasing the
inputs to within this range.
9
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Typical Applications
00865011
FIGURE 7. Positive Regulator, Step-Up Basic Configuration (IIN(MAX) = 80 mA)
00865012
FIGURE 8. Positive Regulator, Step-Up Boosted Current Configuration
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Typical Applications (Continued)
00865013
FIGURE 9. Positive Regulator, Step-Down Basic Configuration (IIN(MAX) = 80 mA)
11
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Typical Applications (Continued)
00865014
FIGURE 10. Positive Regulator, Step-Down Boosted Current Configuration
00865015
FIGURE 11. Boosted Current Polarity Inverter
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12
Typical Applications (Continued)
BASIC SWITCHING REGULATOR THEORY
AND APPLICATIONS
The circuit works as follows: Q1 is used as a switch, which
has ON and OFF times controlled by the pulse width modu-
lator. When Q1 is ON, power is drawn from VIN and supplied
to the load through L1; VA is at approximately VIN, D1 is
reverse biased, and Co is charging. When Q1 turns OFF the
inductor L1 will force VA negative to keep the current flowing
in it, D1 will start conducting and the load current will flow
through D1 and L1. The voltage at VAis smoothed by the L1,
Co filter giving a clean DC output. The current flowing
through L1 is equal to the nominal DC load current plus
some ∆IL which is due to the changing voltage across it. A
good rule of thumb is to set ∆ILP-P . 40% x Io.
The basic circuit of a step-down switching regulator circuit is
shown in Figure 12, along with a practical circuit design
using the LM3524D in Figure 15.
00865016
FIGURE 12. Basic Step-Down Switching Regulator
00865017
FIGURE 13. Relation of Switch Timing to Inductor Current in Step-Down Regulator
+
−
Neglecting VSAT, VD, and settling ∆IL = ∆IL
;
ηMAX will be further decreased due to switching losses in
Q1. For this reason Q1 should be selected to have the
maximum possible fT, which implies very fast rise and fall
times.
where T = Total Period
CALCULATING INDUCTOR L1
The above shows the relation between VIN, Vo and duty
cycle.
as Q1 only conducts during tON
.
−
Since ∆IL+ = ∆IL = 0.4Io
Solving the above for L1
The efficiency, η, of the circuit is:
13
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Typical Applications (Continued)
where: L1 is in Henrys
f is switching frequency in Hz
Also, see LM1578 data sheet for graphical methods of in-
ductor selection.
CALCULATING OUTPUT FILTER CAPACITOR Co:
00865019
Figure 13 shows L1’s current with respect to Q1’s tON and
tOFF times (VA is at the collector of Q1). This curent must
flow to the load and Co. Co’s current will then be the differ-
ence between IL, and Io.
FIGURE 14. Inductor Current Slope in Step-Down
Regulator
Ico = IL − Io
A complete step-down switching regulator schematic, using
the LM3524D, is illustrated in Figure 15. Transistors Q1 and
Q2 have been added to boost the output to 1A. The 5V
regulator of the LM3524D has been divided in half to bias the
error amplifier’s non-inverting input to within its common-
mode range. Since each output transistor is on for half the
period, actually 45%, they have been paralleled to allow
longer possible duty cycle, up to 90%. This makes a lower
possible input voltage. The output voltage is set by:
From Figure 13 it can be seen that current will be flowing into
Co for the second half of tON through the first half of tOFF, or
a time, tON/2 + tOFF/2. The current flowing for this time is
∆IL/4. The resulting ∆Vc or ∆Vo is described by:
where VNI is the voltage at the error amplifier’s non-inverting
input.
Resistor R3 sets the current limit to:
Figures 16, 17 and show a PC board layout and stuffing
diagram for the 5V, 1A regulator of Figure 15. The regulator’s
performance is listed in Table 1.
For best regulation, the inductor’s current cannot be allowed
to fall to zero. Some minimum load current Io, and thus
inductor current, is required as shown below:
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Typical Applications (Continued)
00865020
*Mounted to Staver Heatsink No. V5-1.
Q1 = BD344
Q2 = 2N5023
>
L1 = 40 turns No. 22 wire on Ferroxcube No. K300502 Torroid core.
FIGURE 15. 5V, 1 Amp Step-Down Switching Regulator
15
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Typical Applications (Continued)
TABLE 1.
Parameter
Conditions
Typical
Characteristics
Output Voltage
Switching Frequency
Short Circuit
VIN = 10V, Io = 1A
VIN = 10V, Io = 1A
VIN = 10V
5V
20 kHz
1.3A
Current Limit
Load Regulation
VIN = 10V
3 mV
6 mV
Io = 0.2 − 1A
∆VIN = 10 − 20V,
Io = 1A
Line Regulation
Efficiency
VIN = 10V, Io = 1A
VIN = 10V, Io = 1A
80%
Output Ripple
10 mVp-p
00865021
FIGURE 16. 5V, 1 Amp Switching Regulator, Foil Side
00865022
FIGURE 17. Stuffing Diagram, Component Side
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16
Typical Applications (Continued)
THE STEP-UP SWITCHING REGULATOR
Figure 18 shows the basic circuit for a step-up switching
regulator. In this circuit Q1 is used as a switch to alternately
apply VIN across inductor L1. During the time, tON, Q1 is ON
and energy is drawn from VIN and stored in L1; D1 is reverse
biased and Io is supplied from the charge stored in Co. When
Q1 opens, tOFF, voltage V1 will rise positively to the point
where D1 turns ON. The output current is now supplied
through L1, D1 to the load and any charge lost from Co
during tON is replenished. Here also, as in the step-down
regulator, the current through L1 has a DC component plus
some ∆IL. ∆IL is again selected to be approximately 40% of
IL. Figure 19 shows the inductor’s current in relation to Q1’s
ON and OFF times.
00865023
FIGURE 18. Basic Step-Up Switching Regulator
00865024
FIGURE 19. Relation of Switch Timing to Inductor Current in Step-Up Regulator
In calculating input current IIN(DC), which equals the induc-
tor’s DC current, assume first 100% efficiency:
Since ∆IL+ = ∆IL−, VIN ON
t
= VotOFF − VINtOFF,
and neglecting VSAT and VD1
for η = 100%, POUT = PIN
The above equation shows the relationship between VIN, Vo
and duty cycle.
17
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Typical Applications (Continued)
This equation shows that the input, or inductor, current is
larger than the output current by the factor (1 + tON/tOFF).
Since this factor is the same as the relation between Vo and
VIN, IIN(DC) can also be expressed as:
So far it is assumed η = 100%, where the actual efficiency or
ηMAX will be somewhat less due to the saturation voltage of
Q1 and forward on voltage of D1. The internal power loss
This equation assumes only DC losses, however ηMAX is
further decreased because of the switching time of Q1 and
D1.
due to these voltages is the average IL current flowing, or IIN
,
through either VSAT or VD1. For VSAT = VD1 = 1V this power
loss becomes IIN(DC) (1V). ηMAX is then:
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The network D1, C1 forms a slow start circuit.
Typical Applications (Continued)
This holds the output of the error amplifier initially low thus
reducing the duty-cycle to a minimum. Without the slow start
circuit the inductor may saturate at turn-on because it has to
supply high peak currents to charge the output capacitor
from 0V. It should also be noted that this circuit has no
supply rejection. By adding a reference voltage at the non-
inverting input to the error amplifier, see Figure 21, the input
voltage variations are rejected.
In calculating the output capacitor Co it can be seen that Co
supplies Io during tON. The voltage change on Co during this
time will be some ∆Vc = ∆Vo or the output ripple of the
regulator. Calculation of Co is:
The LM3524D can also be used in inductorless switching
regulators. Figure 22 shows a polarity inverter which if con-
nected to Figure 20 provides a −15V unregulated output.
where: Co is in farads, f is the switching frequency,
∆Vo is the p-p output ripple
Calculation of inductor L1 is as follows:
VIN is applied across L1
where: L1 is in henrys, f is the switching frequency in Hz
To apply the above theory, a complete step-up switching
regulator is shown in Figure 20. Since VIN is 5V, VREF is tied
to VIN. The input voltage is divided by 2 to bias the error
amplifier’s inverting input. The output voltage is:
19
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Typical Applications (Continued)
00865025
>
L1 = 25 turns No. 24 wire on Ferroxcube No. K300502 Toroid core.
FIGURE 20. 15V, 0.5A Step-Up Switching Regulator
00865026
FIGURE 21. Replacing R3/R4 Divider in Figure 20 with Reference Circuit Improves Line Regulation
00865027
FIGURE 22. Polarity Inverter Provides Auxiliary −15V Unregulated Output from Circuit of Figure 20
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20
Physical Dimensions inches (millimeters)
unless otherwise noted
Molded Surface-Mount Package (M)
Order Number LM3524DM
NS Package Number M16A
21
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number LM2524DN or LM3524DN
NS Package Number N16E
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
National Semiconductor
Americas Customer
Support Center
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
National Semiconductor
Asia Pacific Customer
Support Center
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
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