LM26420XSQ [NSC]
Dual 2.0A, High Frequency Synchronous Step-Down DC-DC Regulator; 双2.0A ，高频同步降压型DC- DC稳压器
| 型号： | LM26420XSQ |
| 厂家： | 
National Semiconductor |
| 描述： | Dual 2.0A, High Frequency Synchronous Step-Down DC-DC Regulator |
| 文件： | 总28页 (文件大小：609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 31, 2010
LM26420
Dual 2.0A, High Frequency Synchronous Step-Down DC-
DC Regulator
General Description
Features
The LM26420 regulator is a monolithic, high frequency, dual
PWM step-down DC/DC converter in a 16 Pin LLP and a 20
Pin eTSSOP package. It provides all the active functions to
provide local DC/DC conversion with fast transient response
and accurate regulation in the smallest possible PCB area.
With a minimum of external components, the LM26420 is
easy to use. The ability to drive two 2.0A loads with an internal
75 mΩ PMOS top switch and an internal 50 mΩ NMOS bottom
switch using state-of-the-art 0.5 µm BiCMOS technology re-
sults in the best power density available. The world-class
control circuitry allows on-times as low as 30ns, thus sup-
porting exceptionally high frequency conversion over the en-
tire 3V to 5.5V input operating range down to the minimum
output voltage of 0.8V. Switching frequency is internally set
to 550 kHz or 2.2 MHz, allowing the use of extremely small
surface mount inductors and chip capacitors. Even though the
operating frequency is high, efficiencies up to 93% are easy
to achieve. External shutdown is included, featuring an ultra-
low stand-by current. The LM26420 utilizes current-mode
control and internal compensation to provide high-perfor-
mance regulation over a wide range of operating conditions.
Additional features include internal soft-start circuitry to re-
duce inrush current, pulse-by-pulse current limit, thermal
shutdown, power good indicators, precision enables, and out-
put over-voltage protection.
Input voltage range of 3.0V to 5.5V
■
■
■
■
Output voltage range of 0.8V to 4.5V
2.0A output current per output
High Switching Frequencies
2.2MHz (LM26420X)
0.55MHz (LM26420Y)
75mΩ PMOS switch
50mΩ NMOS switch
0.8V, 1.5% Internal Voltage Reference
■
■
■
■
■
■
■
■
■
■
■
Internal soft-start
Independent power good for each output
Independent precision enable for each output
Current mode, PWM operation
Thermal Shutdown
Over voltage protection
Start-up into Pre-biased Output Loads
Outputs are 180° out of phase
Applications
Local 5V to Vcore Step-Down Converters
■
■
■
■
■
■
Core Power in HDDs
Set-Top Boxes
USB Powered Devices
DSL Modems
Powering Core and I/O voltages for FPGAs, CPLDs, and
ASICs
Typical Application Circuit
30069664
30069684
© 2010 National Semiconductor Corporation
300696
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Connection Diagrams
30069601
16-Pin LLP (TOP VIEW)
20-Pin eTSSOP (TOP VIEW)30069602
Ordering Information
Frequency
Order Number
NSC Package
Drawing
Package Type
eTSSOP-20
LLP-16
Top Mark
LM26420XMH
L26420X
Supplied As
Option
LM26420XMH
75 units Rail
MXA20A
SQB16A
MXA20A
SQB16A
LM26420XMHX
2.2MHz
2500 units Tape and Reel
1000 units Tape and Reel
4500 units Tape and Reel
75 units Rail
LM26420XSQ
LM26420XSQX
LM26420YMH
eTSSOP-20
LLP-16
LM26420YMH
L26420Y
LM26420YMHX
0.55MHz
2500 units Tape and Reel
1000 units Tape and Reel
4500 units Tape and Reel
LM26420YSQ
LM26420YSQX
NOPB versions available as well
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Pin Descriptions 20-Pin eTSSOP
Pin
3, 4
17, 18
1
Name
VIND1
VIND2
VINC
Function
Power Input supply for Buck 1.
Power Input supply for Buck 2.
Input supply for control circuitry.
Power ground pin for Buck 1.
Power ground pin for Buck 2.
6,7
PGND1
PGND2
AGND
14, 15
20
Signal ground pin. Place the bottom resistor of the feedback network as close as possible
to pin.
9
PG1
PG2
Power Good Indicator for Buck 1. Pin is connected through a resistor to an external supply
(open drain output).
12
Power Good Indicator for Buck 2. Pin is connected through a resistor to an external supply
(open drain output).
8
13
5
FB1
FB2
Feedback pin for Buck 1. Connect to external resistor divider to set output voltage.
Feedback pin for Buck 2. Connect to external resistor divider to set output voltage.
Output switch for Buck 1. Connect to the inductor.
SW1
SW2
EN1
16
2
Output switch for Buck 2. Connect to the inductor.
Enable control input. Logic high enable operation for Buck 1. Do not allow this pin to float
or be greater than VIN + 0.3V.
19
EN2
Enable control input. Logic high enable operation for Buck 2. Do not allow this pin to float
or be greater than VIN + 0.3V.
10, 11, DAP
Die Attach Pad
Connect to system ground for low thermal impedance, but it cannot be used as a primary
GND connection.
Pin Descriptions 16-Pin LLP
Pin
1,2
11, 12
15
Name
VIND1
VIND2
VINC
Function
Power Input supply for Buck 1.
Power Input supply for Buck 2.
Input supply for control circuitry.
Power ground pin for Buck 1.
Power ground pin for Buck 2.
4
PGND1
PGND2
AGND
9
14
Signal ground pin. Place the bottom resistor of the feedback network as close as possible
to pin.
6
7
PG1
PG2
Power Good Indicator for Buck 1. Pin is connected through a resistor to an external supply
(open drain output).
Power Good Indicator for Buck 2. Pin is connected through a resistor to an external supply
(open drain output).
5
8
FB1
FB2
Feedback pin for Buck 1. Connect to external resistor divider to set output voltage.
Feedback pin for Buck 2. Connect to external resistor divider to set output voltage.
Output switch for Buck 1. Connect to the inductor.
3
SW1
SW2
EN1
10
16
Output switch for Buck 2. Connect to the inductor.
Enable control input. Logic high enable operation for Buck 1. Do not allow this pin to float
or be greater than VIN + 0.3V.
13
EN2
Enable control input. Logic high enable operation for Buck 2. Do not allow this pin to float
or be greater than VIN + 0.3V.
DAP
Die Attach Pad
Connect to system ground for low thermal impedance and as a primary electrical GND
connection.
3
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Junction Temperature (Note 2)
Storage Temperature
Soldering Information
150°C
−65°C to +150°C
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ꢀInfrared or Convection Reflow
(15 sec)
220°C
VIN
-0.5V to 7V
-0.5V to 3V
-0.5V to 7V
-0.5V to 7V
FB Voltage
EN Voltage
SW Voltage
ESD Susceptibility
Operating Ratings
VIN
3V to 5.5V
−40°C to +125°C
Junction Temperature
Human Body Model (Note 3)
1.5kV
Electrical Characteristics Per Buck VIN = 5V unless otherwise indicated under the Conditions column.
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to
+125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the
most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Symbol
Parameter
Feedback Voltage
Conditions
Min
Typ
0.800
0.05
Max
Units
V
VFB
0.788
0.812
Feedback Voltage Line Regulation
Feedback Input Bias Current
VIN = 3V to 5.5V
%/V
ΔVFB/VIN
IB
0.40
2.628
2.3
100
nA
V
VIN Rising
VIN Falling
2.90
Under-voltage Lockout
UVLO Hysteresis
UVLO
2.0
V
330
2.2
mV
LM26420-X
1.85
0.4
2.65
0.7
FSW
FFB
Switching Frequency
MHz
kHz
%
LM26420-Y
0.55
300
150
91.5
98
LM26420-X
Frequency Fold-back
LM26420-Y
LM26420-X
86
90
DMAX
Maximum Duty Cycle
LM26420-Y
LLP-16 Package
eTSSOP-20 Package
LLP-16 Package
eTSSOP-20 Package
VIN = 3.3V
75
135
135
100
80
RDSON_TOP
RDSON_BOT
TOP Switch On Resistance
BOTTOM Switch On Resistance
mΩ
mΩ
70
55
45
ICL_TOP
ICL_BOT
ΔΦ
TOP Switch Current Limit
2.4
0.4
3.3
A
A
°
BOTTOM Switch Reverse Current Limit
Phase Shift Between SW1 and SW2
VIN = 3.3V
0.75
180
160
0.97
200
Enable Threshold Voltage
Enable Threshold Hysteresis
Switch Leakage
1.04
0.15
-0.7
5.0
1.12
VEN_TH
V
ISW_TOP
IEN
µA
nA
Enable Pin Current
Sink/Source
VPG-TH-U
Upper Power Good Threshold
Upper Power Good Hysteresis
Lower Power Good Threshold
Lower Power Good Hysteresis
FB Pin Voltage Rising
848
656
925
40
1,008
791
mV
mV
mV
mV
VPG-TH-L
FB Pin Voltage Rising
710
40
VINC Quiescent Current (non-switching) LM26420X/Y VFB = 0.9
with both outputs on
3.3
5.0
6.2
mA
IQVINC
VINC Quiescent Current (switching) with LM26420X/Y VFB = 0.7
both outputs on
4.7
All Options VEN = 0V
LM26420X/Y VFB = 0.9
LM26420X VFB = 0.7
LM26420Y VFB = 0.7
All Options VEN = 0V
0.05
0.9
VINC Quiescent Current (shutdown)
µA
mA
µA
1.5
15.0
7.5
VIND Quiescent Current (non-switching)
11.0
3.7
IQVIND
VIND Quiescent Current (switching)
VIND Quiescent Current (shutdown)
0.1
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Symbol
Parameter
Junction to Ambient
0 LFPM Air Flow (Note 4)
Junction to Case (Note 4)
Thermal Shutdown Temperature
Conditions
Min
Typ
40
Max
Units
°C/W
°C
LLP-16
θJA
eTSSOP-20
LLP-16
35
6.8
3.9
165
θJC
eTSSOP-20
TSD
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Range indicates conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: Thermal shutdown will occur if the junction temperature exceeds the maximum junction temperature of the device.
Note 3: The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-A114.
Note 4: Applies to a 4-layer standard JEDEC thermal test board or 4LJEDEC is 4"x3" in size. The board has 2 imbedded copper layers which cover roughly the
same size as the board. The copper thickness for the four layers, starting from the top one, is 2 oz./1oz./1oz./2 oz. For LLP, thermal vias are placed between the
die attach pad in the 1st. copper layer and 2nd. copper layer.
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Typical Performance Characteristics
All curves taken at VIN = 5.0V with configuration in typical application circuit shown in Application Information section of this
datasheet. TJ = 25°C, unless otherwise specified.
η vs Load "X" VIN = 5V, VOUT = 3.3V
η vs Load "Y" VIN = 5V, VOUT = 3.3V
30069682
30069683
η vs Load - "X" VIN = 5V & 3V, VOUT = 2.5V
η vs Load "Y" VIN = 5V & 3V, VOUT = 2.5V
30069685
30069684
η vs Load "X" VIN = 5V & 3V, VOUT = 1.8V
η vs Load "Y" VIN = 5V & 3V, VOUT = 1.8V
30069690
30069687
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η vs Load "X" VIN= 5V & 3V, VOUT = 1.2V
η vs Load "Y" VIN = 5V & 3V, VOUT = 1.2V
30069688
30069689
η vs Load "X" VIN = 5V & 3V, VOUT = 0.8V
η vs Load "Y" VIN = 5V & 3V, VOUT = 0.8V
30069641
30069642
Load Regulation
VIN = 5V, VOUT = 1.8V (All Options)
Load Regulation
VIN = 3V, VOUT = 1.8V (All Options)
30069643
30069645
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Line Regulation - "X"
VOUT = 1.8V, IOUT = 1,000mA
Line Regulation - "Y"
VOUT = 1.8V, IOUT = 1,000mA
30069627
30069646
Oscillator Frequency vs Temperature - "X"
Oscillator Frequency vs Temperature - "Y"
30069648
30069647
RDSON TOP vs Temperature (LLP-16 Package)
RDSON BOTTOM vs Temperature (LLP-16 Package)
30069649
30069650
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RDSON TOP vs Temperature (eTSSOP-20 Package)
RDSON BOTTOM vs Temperature (eTSSOP-20 Package)
30069691
30069692
IQ (Quiescent Current Switching) - "X"
IQ (Quiescent Current Switching) - "Y"
30069654
30069655
Load Transient Response - X Version
(VOUT = 1.2V, 25-100% Load Transient)
Load Transient Response - Y Version
(VOUT = 1.2V, 25-100% Load Transient)
30069639
30069656
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Start-Up (Soft-Start)
(VOUT = 1.8V @ 1A, VIN = 5V)
Enable - Disable
(VOUT = 1.8V @ 1A, VIN = 5V)
30069657
30069658
VFB vs Temperature
Current Limit vs Temperature
(VIN = 5V and 3.3V)
30069659
30069653
Reverse Current Limit vs Temperature
Short Circuit Waveforms
30069698
30069680
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Simplified Block Diagram Per Buck
30069604
FIGURE 1.
11
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Applications Information
THEORY OF OPERATION
current and eliminate overshoot on VOUT. During soft-start,
the error amplifier’s reference voltage ramps from 0V to its
nominal value of 0.8V in approximately 600 µs. If the con-
verter is turned on into a pre-biased condition then the feed-
back will begin ramping from the pre-bias voltage but at the
same rate as if it had started from 0V. The two outputs startup
ratiometrically if enabled at the same time, see figure below.
The LM26420 is a constant frequency dual PWM buck syn-
chronous regulator IC that delivers two 2.0A load currents.
The regulator has a preset switching frequency of 2.2MHz or
550kHz. This high frequency allows the LM26420 to operate
with small surface mount capacitors and inductors, resulting
in a DC/DC converter that requires a minimum amount of
board space. The LM26420 is internally compensated, so it
is simple to use and requires few external components. The
LM26420 uses current-mode control to regulate the output
voltage. The following operating description of the LM26420
will refer to the Simplified Block Diagram (Figure 1), which
depicts the functional blocks for one of the two channels, and
to the waveforms in Figure 2. The LM26420 supplies a regu-
lated output voltage by switching the internal PMOS and
NMOS switches at constant frequency and variable duty cy-
cle. A switching cycle begins at the falling edge of the reset
pulse generated by the internal clock. When this pulse goes
low, the output control logic turns on the internal PMOS con-
trol switch (TOP Switch). During this on-time, the SW pin
voltage (VSW) swings up to approximately VIN, and the induc-
tor current (IL) increases with a linear slope. IL is measured
by the current sense amplifier, which generates an output
proportional to the switch current. The sense signal is
summed with the regulator’s corrective ramp and compared
to the error amplifier’s output, which is proportional to the dif-
ference between the feedback voltage and VREF. When the
PWM comparator output goes high, the TOP Switch turns off
and the NMOS switch (BOTTOM Switch) turns on after a short
delay, which is controlled by the Dead-Time-Control Logic,
until the next switching cycle begins. During the top switch off-
time, inductor current discharges through the BOTTOM
Switch, which forces the SW pin to swing to ground. The reg-
ulator loop adjusts the duty cycle (D) to maintain a constant
output voltage.
OUTPUT OVER-VOLTAGE PROTECTION
The over-voltage comparator compares the FB pin voltage to
a voltage that is approximately 15% higher than the internal
reference VREF. Once the FB pin voltage goes 15% above the
internal reference, the internal PMOS control switch is turned
off, which allows the output voltage to decrease toward reg-
ulation.
UNDER-VOLTAGE LOCKOUT
Under-voltage lockout (UVLO) prevents the LM26420 from
operating until the input voltage exceeds 2.628V (typ). The
UVLO threshold has approximately 330 mV of hysteresis, so
the part will operate until VIN drops below 2.3V (typ). Hystere-
sis prevents the part from turning off during power up if VIN is
non-monotonic.
CURRENT LIMIT
The LM26420 uses cycle-by-cycle current limiting to protect
the output switch. During each switching cycle, a current limit
comparator detects if the output switch current exceeds 3.3A
(typ), and turns off the switch until the next switching cycle
begins.
THERMAL SHUTDOWN
Thermal shutdown limits total power dissipation by turning off
the output switch when the IC junction temperature exceeds
165°C. After thermal shutdown occurs, the output switch does
not turn on until the junction temperature drops to approxi-
mately 150°C.
POWER GOOD
30069666
The LM26420 features and open drain power good (PG) pin
to sequence external supplies or loads and to provide fault
detection. This pin requires an external resistor (RPG) to pull
PG high when the output is within the PG tolerance window.
Typical values for this resistor range from 10 kΩ to 100 kΩ.
FIGURE 2. Typical Waveforms
SOFT-START
This function forces VOUT to increase at a controlled rate dur-
ing start up in a controlled fashion, which helps reduce inrush
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PRECISION ENABLE
with a resistor divider network. It can also be set to turn on at
a specific input voltage when used in conjunction with a re-
sistor divider network connected to the input voltage. The
device is enabled when the EN pin exceeds 1.04V and has a
150mV hysteresis.
The LM26420 features independent precision enables that
allow the converter to be controlled by an external signal. This
feature allows the device to be sequenced either by a external
control signal or the output of another converter in conjunction
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Design Guide
INDUCTOR SELECTION
The Duty Cycle (D) can be approximated quickly using the
ratio of output voltage (VOUT) to input voltage (VIN):
Where
When selecting an inductor, make sure that it is capable of
supporting the peak output current without saturating. Induc-
tor saturation will result in a sudden reduction in inductance
and prevent the regulator from operating correctly. The peak
current of the inductor is used to specify the maximum output
current of the inductor and saturation is not a concern due to
the exceptionally small delay of the internal current limit sig-
nal. For example, if the designed maximum output current is
2.0A and the peak current is 2.3A, then the inductor should
be specified with a saturation current limit of > 2.3A. There is
no need to specify the saturation or peak current of the in-
ductor at the 3.25A typical switch current limit. The difference
in inductor size is a factor of 5. Ferrite based inductors are
preferred to minimize core losses when opperating with the
frequencies used by the LM26420. This presents little restric-
tion since the variety of ferrite-based inductors is huge. Lastly,
inductors with lower series resistance (RDCR) will provide bet-
ter operating efficiency. For recommended inductors see Ex-
ample Circuits.
The voltage drop across the internal NMOS (SW_BOT) and
PMOS (SW_TOP) must be included to calculate a more ac-
curate duty cycle. Calculate D by using the following formulas:
VSW_TOP and VSW_BOT can be approximated by:
VSW_TOP = IOUT x RDSON_TOP
VSW_BOT = IOUT x RDSON_BOT
The inductor value determines the output ripple current. Low-
er inductor values decrease the size of the inductor, but
increase the output ripple current. An increase in the inductor
value will decrease the output ripple current.
One must ensure that the minimum current limit (2.4A) is not
exceeded, so the peak current in the inductor must be calcu-
lated. The peak current (ILPK) in the inductor is calculated by:
INPUT CAPACITOR SELECTION
ILPK = IOUT + ΔiL
The input capacitors provide the AC current needed by the
nearby power switch so that current provided by the upstream
power supply does not carry a lot of AC content, generating
less EMI. To the buck regulator in question, the input capac-
itor also prevents the drain voltage of the FET switch from
dipping when the FET is turned on, therefore providing a
healthy line rail for the LM26420 to work with. Since typically
most of the AC current is provided by the local input capaci-
tors, the power loss in those capacitors can be a concern. In
the case of the LM26420 regulator, since the two channels
operate 180° out of phase, the AC stress in the input capac-
itors is less than if they operated in phase. The measure for
the AC stress is called input ripple RMS current. It is strongly
recommended that at least one 10µF ceramic capacitor be
placed next to each of the VIND pins. Bulk capacitors such as
electrolytic capacitors or OSCON capacitors can be added to
help stabilize the local line voltage, especially during large
load transient events. As for the ceramic capacitors, use X7R
or X5R types. They maintain most of their capacitance over
a wide temperature range. Try to avoid sizes smaller than
0805. Otherwise significant drop in capacitance may be
caused by the DC bias voltage. See OUTPUT CAPACITOR
SELECTION section for more information. The DC voltage
rating of the ceramic capacitor should be higher than the
highest input voltage.
30069605
FIGURE 3. Inductor Current
In general,
ΔiL = 0.1 x (IOUT) → 0.2 x (IOUT
)
If ΔiL = 20% of 2A, the peak current in the inductor will be 2.4A.
The minimum guaranteed current limit over all operating con-
ditions is 2.4A. One can either reduce ΔiL, or make the engi-
neering judgment that zero margin will be safe enough. The
typical current limit is 3.3A.
Capacitor temperature is a major concern in board designs.
While using a 10µF or higher MLCC as the input capacitor is
a good starting point, it is a good idea to check the tempera-
ture in the real thermal environment to make sure the capac-
itors are not over heated. Capacitor vendors may provide
curves of ripple RMS current vs. temperature rise, based on
a designated thermal impedance. In reality, the thermal
impedance may be very different. So it is always a good idea
to check the capacitor temperature on the board.
The LM26420 operates at frequencies allowing the use of ce-
ramic output capacitors without compromising transient re-
sponse. Ceramic capacitors allow higher inductor ripple
without significantly increasing output ripple. See the output
capacitor section for more details on calculating output volt-
age ripple. Now that the ripple current is determined, the
inductance is calculated by:
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Since the duty cycles of the two channels may overlap, cal-
culation of the input ripple RMS current is a little tedious. Use
the following equation.
RDC is the winding resistance of the inductor. RDS is the ON
resistance of the MOSFET switch.
Example:
VIN = 5V, VOUT1 = 3.3V, IOUT1 = 2A, VOUT2 = 1.2V, IOUT2 = 1.5A,
RDS = 170mΩ, RDC = 30mΩ. (IOUT1 is the same as I1 in the
input ripple RMS current equation, IOUT2 is the same as I2).
First, find out the duty cycles. Plug the numbers into the duty
cycle equation and we get D1 = 0.75, and D2 = 0.33. Next,
follow the decision tree in to find out the values of d1, d2 and
d3. In this case, d1 = 0.5, d2 = D2 + 0.5 - D1 = 0.08, and d3
= D1 - 0.5 = 0.25. Iav = IOUT1·D1 + IOUT2·D2 = 1.995A. Plug all
the numbers into the input ripple RMS current equation and
the result is Iirrms = 0.77A.
I1 is Channel 1's maximum output current. I2 is Channel 2's
maximum output current. d1 is the non-overlapping portion of
Channel 1's duty cycle D1. d2 is the non-overlapping portion
of Channel 2's duty cycle D2. d3 is the overlapping portion of
the two duty cycles. Iav is the average input current. Iav=
I1·D1 + I2·D2. To quickly determine the values of d1, d2 and
d3, refer to the decision tree in . To determine the duty cycle
of each channel, use D = VOUT/VIN for a quick result or use
the following equation for a more accurate result.
30069681
FIGURE 4. Determining d1, d2 and d3
OUTPUT CAPACITOR
switching edge noise will couple through parasitic capaci-
tances in the inductor to the output. A ceramic capacitor will
bypass this noise while a tantalum will not. Since the output
capacitor is one of the two external components that control
the stability of the regulator control loop, most applications will
require a minimum of 22 µF of output capacitance. Capaci-
tance often, but not always, can be increased significantly
with little detriment to the regulator stability. Like the input ca-
pacitor, recommended multilayer ceramic capacitors are X7R
or X5R types.
The output capacitor is selected based upon the desired out-
put ripple and transient response. The initial current of a load
transient is provided mainly by the output capacitor. The out-
put ripple of the converter is:
When using MLCCs, the ESR is typically so low that the ca-
pacitive ripple may dominate. When this occurs, the output
ripple will be approximately sinusoidal and 90° phase shifted
from the switching action. Given the availability and quality of
MLCCs and the expected output voltage of designs using the
LM26420, there is really no need to review any other capacitor
technologies. Another benefit of ceramic capacitors is their
ability to bypass high frequency noise. A certain amount of
PROGRAMMING OUTPUT VOLTAGE
The output voltage is set using the following equation where
R2 is connected between the FB pin and GND, and R1 is
connected between VOUT and the FB pin. A good value for R2
is 10kΩ. When designing a unity gain converter (VOUT = 0.8V),
R1 should be between 0Ω and 100Ω, and R2 should be on
the order of 5kΩ to 50kΩ, 10kΩ is the suggested value.
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time constant should be at least 2 µS. CF should be placed as
close as possible to IC with a direct connection from VINC
and AGND.
USING PRECISION ENABLE AND POWER GOOD
VREF = 0.80V
The LM26420's precision enable and power good pins ad-
dress many of the sequencing requirements required today's
challenging applications. Each output can be controlled inde-
pendently and have independent power goods. This allows
for a multitude of ways to control each output. Typically, the
enables to each output are tied together to the input voltage
and the outputs will ratiometrically ramp up when the input
voltage reaches above UVLO rising threshold. There may be
instances where it is desired that the second output (VOUT2
)
does not turn on until the first output (VOUT1) has reached 90%
of the desired set-point. This achieved easily with an external
resistor divider attached from VOUT1 to EN2, see figure .
30069699
FIGURE 5. Programming VOUT
To determine the maximum allowed resistor tolerance , use
the following equation:
30069640
FIGURE 7. VOUT1 controlling VOUT2 with resistor divider.
where TOL is the set point accuracy of the regulator, Φ is the
tolerance of VFB
.
If it is not desired to have a resistor divider to control VOUT2
with VOUT1, then the PG1 can be connected to the EN2 pin to
control VOUT2, see figure below. RPG1 is a pull up resistor on
the range of 10kΩ to 100kΩ, 50kΩ is the suggested value.
greater. This will turn on VOUT2 when VOUT1 is approximately
90% of the programmed output. NOTE, this will also turn off
VOUT2 when VOUT1 is outside the +/-10% of the programmed
output.
Example:
VOUT = 2.5V, with a set point accuracy of +/- 3.5%.
Choose 1% resistors. If R2 = 10kΩ, then R1 is 21.25kΩ.
VINC FILTERING COMPONENTS
Additional filtering is required between VINC and AGND in
order to prevent high frequency noise on VIN from disturbing
the sensitive circuitry connected to VINC. A small RC filter can
be used on the VINC pin as shown below.
30069697
FIGURE 8. PG1 controlling VOUT2
.
Another example might be that the output is not to be turned
on until the input voltage reaches 90% of desired voltage set-
point. This verifies that the input supply is stable before turn-
ing on the output. Select REN1 and REN2 such that the the
voltage at the EN pin is greater than 1.12V when reaching the
90% desired set-point.
30069638
FIGURE 6. RC filter on VINC
In general, RF is typically between 1Ω and 10Ω so that the
steady state voltage drop across the resistor due to the VINC
bias current does not affect the UVLO level. CF can range
from 0.22 µF to 1.0 µF in X7R or X5R dielectric, where the RC
www.national.com
16
fold-back which is set to approximately 150kHz for the Y ver-
sion and 300kHz for the X version. Frequency fold back helps
reduce the thermal stress in the IC by reducing the switching
losses and to prevent runaway of the inductor current when
the output is shorted to ground.
It is important to note that when recovering from a over-cur-
rent condition the converter does not go through the soft-start
process. There may be an over shoot due to the sudden re-
moval of the over-current fault. The reference voltage at the
non-inverting input of the error amplifier always sits at 0.8V
during the over-current condition, therefore when the fault is
removed the converter bring the FB voltage back to 0.8V as
quickly as possible. The over-shoot depend on whether there
is a load on the output after the removal of the over-current
fault, the size of the inductor, and the amount of capacitance
on the output. The small the inductor and the larger the ca-
pacitance on the output the small the overshoot. Note, over-
current protection for each output is independent.
30069696
FIGURE 9. VIN controlling VOUT
The LM26420's power good feature is design with hysterysis
in order to insure no false power good flags are asserted dur-
ing large transient. Once power good is asserted high, it will
not be pulled low until the output voltage exceeds +/-14% of
the setpoint for a during of ~7.5µS (typ.), see figure below.
PCB LAYOUT CONSIDERATIONS
When planning layout there are a few things to consider when
trying to achieve a clean, regulated output. The most impor-
tant consideration is the close coupling of the GND connec-
tions of the input capacitor and the PGND pin. These ground
ends should be close to one another and be connected to the
GND plane with at least two through-holes. Place these com-
ponents as close to the IC as possible. Next in importance is
the location of the GND connection of the output capacitor,
which should be near the GND connections of VIND and
PGND. There should be a continuous ground plane on the
bottom layer of a two-layer board except under the switching
node island. The FB pin is a high impedance node and care
should be taken to make the FB trace short to avoid noise
pickup and inaccurate regulation. The feedback resistors
should be placed as close as possible to the IC, with the GND
of R1 placed as close as possible to the GND of the IC. The
VOUT trace to R2 should be routed away from the inductor and
any other traces that are switching. High AC currents flow
through the VIN, SW and VOUT traces, so they should be as
short and wide as possible. However, making the traces wide
increases radiated noise, so the designer must make this
trade-off. Radiated noise can be decreased by choosing a
shielded inductor. The remaining components should also be
placed as close as possible to the IC. Please see Application
Note AN-1229 for further considerations and the LM26420
demo board as an example of a four-layer layout.
30069660
FIGURE 10. Power Good Hysterysis Operation
OVER-CURRENT PROTECTION
When the switch current reaches the current limit value, it im-
mediately is turned off. This effectively reduces the duty cycle
and therefore the output voltage dips and continues to droop
until the output load matches the peak current limit inductor
current. As the FB voltage drops below 480mV the operating
frequency begins to decrease until it hits full on frequency
17
www.national.com
PCOND_TOP = (IOUT2 x RDSON_TOP x D)
PCOND_BOT = (IOUT2 x RDSON_BOT x (1-D))
PCOND = PCOND_TOP + PCOND_BOT
Calculating Efficiency, and Junction
Temperature
The complete LM26420 DC/DC converter efficiency can be
calculated in the following manner.
Switching losses are also associated with the internal FETs.
They occur during the switch on and off transition periods,
where voltages and currents overlap resulting in power loss.
The simplest means to determine this loss is to empirically
measuring the rise and fall times (10% to 90%) of the switch
at the switch node.
Switching Power Loss is calculated as follows:
Or
PSWR = 1/2(VIN x IOUT x FSW x TRISE
)
PSWF = 1/2(VIN x IOUT x FSW x TFALL
PSW = PSWR + PSWF
)
Calculations for determining the most significant power loss-
es are shown below. Other losses totaling less than 2% are
not discussed.
Another loss is the power required for operation of the internal
circuitry:
PQ = IQ x VIN
Power loss (PLOSS) is the sum of two basic types of losses in
the converter: switching and conduction. Conduction losses
usually dominate at higher output loads, whereas switching
losses remain relatively fixed and dominate at lower output
loads. The first step in determining the losses is to calculate
the duty cycle (D):
IQ is the quiescent operating current, and is typically around
8.4mA (IQVINC = 4.7mA + IQVIND=3.7mA) for the 550 kHz fre-
quency option.
Due to Dead-Time-Control Logic in the converter, there is a
small delay (~4nS) between the turn ON and OFF of the TOP
and BOTTOM FET. During this time, the body diode of the
BOTTOM FET is conducting with a voltage drop of VBDIODE
(~.65V). This allows the inductor current to circulate to the
output, until the BOTTOM FET is turned ON an the inductor
current passes through the FET. There is a small amount of
power loss due to this body diode conducting and it can be
calculated as follows:
VSW_TOP is the voltage drop across the internal PFET when it
is on, and is equal to:
PBDIODE = 2x(VBDIODE x IOUT x FSW x TBDIODE
Typical Application power losses are:
)
VSW_TOP = IOUT x RDSON_TOP
VSW_BOT is the voltage drop across the internal NFET when it
is on, and is equal to:
PLOSS = ΣPCOND + PSW + PBDIODE + PIND + PQ
PINTERNAL = ΣPCOND + PSW+ PBDIODE + PQ
VSW_BOT = IOUT x RDSON_BOT
Power Loss Tabulation
If the voltage drop across the inductor (VDCR) is accounted
for, the equation becomes:
VIN
IOUT
5.0V
2.0A
VOUT
POUT
1.2V
2.4W
FSW
550kHz
0.65V
8.4mA
1.5nS
1.5nS
VBDIODE
IQ
PBDIODE
PQ
5.7mW
42mW
TRISE
TFALL
RDSON_TOP
RDSON_BOT
INDDCR
D
PSWR
4.1mW
4.1mW
81mW
Another significant external power loss is the conduction loss
in the output inductor. The equation can be simplified to:
PSWF
PCOND_TOP
PCOND_BOT
PIND
75mΩ
55mΩ
20mΩ
0.262
86.2%
PIND = IOUT2 x RDCR
167mW
80mW
The LM26420 conduction loss is mainly associated with the
two internal FETs:
PLOSS
384mW
304mW
PINTERNAL
η
These calculations assume a junction temperature of 25°C.
The RDSON values will be larger due to internal heating and
therefore the internal power loss (PINTERNAL) must be first cal-
culated to estimate the rise in junction temperature.
If the inductor ripple current is fairly small, the conduction
losses can be simplified to:
www.national.com
18
Thermal Definitions
TJ = Chip junction temperature
TA = Ambient temperature
RθJC = Thermal resistance from chip junction to device case
RθJA = Thermal resistance from chip junction to ambient air
Heat in the LM26420 due to internal power dissipation is re-
moved through conduction and/or convection.
Therefore:
Tj = (RΦJC x PINTERNAL) + TC
From the previous example:
Tj = 20°C/W x 0.304W + TC
Conduction: Heat transfer occurs through cross sectional ar-
eas of material. Depending on the material, the transfer of
heat can be considered to have poor to good thermal con-
ductivity properties (insulator vs. conductor).
Method 2: Thermal Shutdown Temperature Determina-
tion
The second method, although more complicated, can give a
very accurate silicon junction temperature.
Heat Transfer goes as:
Silicon → package → lead frame → PCB
Convection: Heat transfer is by means of airflow. This could
be from a fan or natural convection. Natural convection occurs
when air currents rise from the hot device to cooler air.
The first step is to determine RθJA of the application. The
LM26420 has over-temperature protection circuitry. When the
silicon temperature reaches 165°C, the device stops switch-
ing. The protection circuitry has a hysteresis of about 15°C.
Once the silicon temperature has decreased to approximately
150°C, the device will start to switch again. Knowing this, the
RθJA for any application can be characterized during the early
stages of the design one may calculate the RθJA by placing
the PCB circuit into a thermal chamber. Raise the ambient
temperature in the given working application until the circuit
enters thermal shutdown. If the SW-pin is monitored, it will be
obvious when the internal FETs stop switching, indicating a
junction temperature of 165°C. Knowing the internal power
dissipation from the above methods, the junction tempera-
ture, and the ambient temperature RθJA can be determined.
Thermal impedance is defined as:
Thermal impedance from the silicon junction to the ambient
air is defined as:
The PCB size, weight of copper used to route traces and
ground plane, and number of layers within the PCB can great-
ly effect RθJA. The type and number of thermal vias can also
make a large difference in the thermal impedance. Thermal
vias are necessary in most applications. They conduct heat
from the surface of the PCB to the ground plane. Five to eight
thermal vias should be placed under the exposed pad to the
ground plane if the LLP package is used. Up to 12 thermal
vias should be used in the eTSSOP-20 package for optimum
heat transfer from the device to the ground plane.
Once this is determined, the maximum ambient temperature
allowed for a desired junction temperature can be found.
An example of calculating RθJA for an application using the
National Semiconductor LM26420 LLP demonstration board
is shown below.
The four layer PCB is constructed using FR4 with 1 oz copper
traces. The copper ground plane is on the bottom layer. The
ground plane is accessed by eight vias. The board measures
3.0cm x 3.0cm. It was placed in an oven with no forced airflow.
The ambient temperature was raised to 152°C, and at that
temperature, the device went into thermal shutdown.
Thermal impedance also depends on the thermal properties
of the application's operating conditions (VIN, VOUT, IOUT etc),
and the surrounding circuitry.
Method 1: Silicon Junction Temperature Determination
From the previous example:
To accurately measure the silicon temperature for a given
application, two methods can be used. The first method re-
quires the user to know the thermal impedance of the silicon
junction to top case temperature.
PINTERNAL = 304mW
Some clarification needs to be made before we go any further.
RθJC is the thermal impedance from all six sides of an IC
package to silicon junction.
RΦJC is the thermal impedance from top case to the silicon
junction.
If the junction temperature was to be kept below 125°C, then
the ambient temperature could not go above 112°C.
In this data sheet we will use RΦJC so that it allows the user
to measure top case temperature with a small thermocouple
attached to the top case.
Tj - (RθJA x PINTERNAL) = TA
RΦJC is approximately 20°C/Watt for the 16-pin LLP package
with the exposed pad. Knowing the internal dissipation from
the efficiency calculation given previously, and the case tem-
perature, which can be empirically measured on the bench
we have:
125°C - (42.8°C/W x 304mW) = 112.0°C
19
www.national.com
LLP Package
30069668
FIGURE 11. Internal LLP Connection
For certain high power applications, the PCB land may be modified to a "dog bone" shape (see Figure 6). By increasing the size
of ground plane, and adding thermal vias, the RθJA for the application can be reduced.
30069606
FIGURE 12. 20-Lead eTSSOP PCB Dog Bone Layout
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20
LM26420X Design Example 1
30069607
FIGURE 13. LM26420X (2.2MHz): VIN = 5V, VOUT1 = 1.2V @ 2.0A and VOUT2 = 2.5V @ 2.0A
Bill of Materials
Part ID
U1
Part Value
2A Buck Regulator
15µF, 6.3V, 1206, X5R
33µF, 6.3V, 1206, X5R
22µF, 6.3V, 1206, X5R
0.47µF, 10V, 0805, X7R
1.0µH, 7.9A
Manufacturer
NSC
Part Number
LM26420X
C3, C4
C1
TDK
C3216X5R0J156M
C3216X5R0J336M
C3216X5R0J226M
VJ0805Y474KXQCW1BC
RLF7030T-1R0M6R4
RLF7030T-1R5M6R1
CRCW060310K0F
CRCW06034K99F
CRCW060649K9F
CRCW060321K5F
CRCW06034R99F
TDK
C2
TDK
C5
Vishay
TDK
L1
L2
1.5µH, 6.5A
TDK
R3, R4
R1
Vishay
Vishay
Vishay
Vishay
Vishay
10.0kΩ, 0603, 1%
4.99kΩ, 0603, 1%
49.9kΩ, 0603, 1%
21.5kΩ, 0603, 1%
4.99Ω, 0603, 1%
R5, R6
R2
R7
21
www.national.com
LM26420X Design Example 2
30069628
FIGURE 14. LM26420X (2.2MHz): VIN = 5V, VOUT1 = 1.8V @ 2.0A and VOUT2 = 0.8V @ 2.0A
Bill of Materials
Part ID
U1
Part Value
2A Buck Regulator
15µF, 6.3V, 1206, X5R
33µF, 6.3V, 1206, X5R
22µF, 6.3V, 1206, X5R
0.47µF, 10V, 0805, X7R
1.0µH, 7.9A
Manufacturer
NSC
Part Number
LM26420X
C3, C4
C1
TDK
C3216X5R0J156M
C3216X5R0J336M
C3216X5R0J226M
VJ0805Y474KXQCW1BC
RLF7030T-1R0M6R4
LPS4414-701ML
TDK
C2, C6
C5
TDK
Vishay
TDK
L1
L2
0.7µH, 3.7A
Coilcraft
Vishay
Vishay
Vishay
Vishay
R3, R4
R5, R6
R1
CRCW060310K0F
CRCW060649K9F
CRCW060312K7F
CRCW06034R99F
10.0kΩ, 0603, 1%
49.9kΩ, 0603, 1%
12.7kΩ, 0603, 1%
4.99Ω, 0603, 1%
R7, R2
www.national.com
22
LM26420X Design Example 3
30069603
FIGURE 15. LM26420X (2.2MHz): VIN = 5V, VOUT1 = 3.3V @ 2.0A and VOUT2 = 1.8V @ 2.0A
Bill of Materials
Part ID
U1
Part Value
2A Buck Regulator
15µF, 6.3V, 1206, X5R
22µF, 6.3V, 1206, X5R
33µF, 6.3V, 1206, X5R
0.47µF, 10V, 0805, X7R
1.0µH, 7.9A
Manufacturer
NSC
Part Number
LM26420X
C3, C4
C1
TDK
C3216X5R0J156M
C3216X5R0J226M
C3216X5R0J336M
VJ0805Y474KXQCW1BC
RLF7030T-1R0M6R4
CRCW060310K0F
CRCW060312K7F
CRCW060649K9F
CRCW060331K6F
CRCW06034R99F
TDK
C2
TDK
C5
Vishay
TDK
L1, L2
R3, R4
R2
Vishay
Vishay
Vishay
Vishay
Vishay
10.0kΩ, 0603, 1%
12.7kΩ, 0603, 1%
49.9kΩ, 0603, 1%
31.6kΩ, 0603, 1%
4.99Ω, 0603, 1%
R5, R6
R1
R7
23
www.national.com
LM26420Y Design Example 4
30069607
FIGURE 16. LM26420Y (550kHz): VIN = 5V, VOUT1 = 1.2V @ 2.0A and VOUT2 = 2.5V @ 2.0A
Bill of Materials
Part ID
U1
Part Value
2A Buck Regulator
22µF, 6.3V, 1206, X5R
33µF, 6.3V, 1206, X5R
47µF, 6.3V, 1206, X5R
0.47µF, 10V, 0805, X7R
3.3µH, 3.28A
Manufacturer
NSC
Part Number
LM26420Y
C3, C4
C1, C6, C7
C2
TDK
C3216X5R0J226M
C3216X5R0J336M
C3216X5R0J476M
VJ0805Y474KXQCW1BC
MSS7341-332NL
MSS7341-502NL
CRCW060310K0F
CRCW06034K99F
CRCW060649K9F
CRCW060321K5F
CRCW06034R99F
TDK
TDK
C5
Vishay
Coilcraft
Coilcraft
Vishay
Vishay
Vishay
Vishay
Vishay
L1
L2
5.0µH, 2.82A
R3, R4
R1
10.0kΩ, 0603, 1%
4.99kΩ, 0603, 1%
49.9kΩ, 0603, 1%
21.5kΩ, 0603, 1%
4.99Ω, 0603, 1%
R5, R6
R2
R7
www.national.com
24
LM26420Y Design Example 5
30069628
FIGURE 17. LM26420Y (550kHz): VIN = 5V, VOUT1 = 1.8V @ 2.0A and VOUT2 = 0.8V @ 2.0A
Bill of Materials
Part ID
Part Value
2A Buck Regulator
22µF, 6.3V, 1206, X5R
47µF, 6.3V, 1206, X5R
0.47µF, 10V, 0805, X7R
5.0µH, 2.82A
Manufacturer
NSC
Part Number
LM26420Y
U1
C3, C4
TDK
C3216X5R0J226M
C3216X5R0J476M
VJ0805Y474KXQCW1BC
MSS7341-502NL
MSS7341-332NL
CRCW060310K0F
CRCW060649K9F
CRCW060312K7F
CRCW06034R99F
C1, C2, C6, C7, C8
TDK
C5
L1
Vishay
Coilcraft
Coilcraft
Vishay
Vishay
Vishay
Vishay
L2
3.3µH, 3.28A
R3, R4
R5, R6
R1
10.0kΩ, 0603, 1%
49.9kΩ, 0603, 1%
12.7kΩ, 0603, 1%
4.99Ω, 0603, 1%
R7, R2
25
www.national.com
LM26420Y Design Example 6
30069603
FIGURE 18. LM26420Y (550kHz): VIN = 5V, VOUT1 = 3.3V @ 2.0A and VOUT2 = 1.8V @ 2.0A
Bill of Materials
Part ID
U1
Part Value
2A Buck Regulator
22µF, 6.3V, 1206, X5R
47µF, 6.3V, 1206, X5R
0.47µF, 10V, 0805, X7R
5.0µH, 2.82A
Manufacturer
NSC
Part Number
LM26420Y
C3, C4
C1, C2, C6
C5
TDK
C3216X5R0J226M
C3216X5R0J476M
VJ0805Y474KXQCW1BC
MSS7341-502NL
CRCW060310K0F
CRCW060312K7F
CRCW060649K9F
CRCW060331K6F
CRCW06034R99F
TDK
Vishay
Coilcraft
Vishay
Vishay
Vishay
Vishay
Vishay
L1, L2
R3, R4
R2
10.0kΩ, 0603, 1%
12.7kΩ, 0603, 1%
49.9kΩ, 0603, 1%
31.6kΩ, 0603, 1%
4.99Ω, 0603, 1%
R5, R6
R1
R7
www.national.com
26
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead eTSSOP Package
NS Package Number MXA20A
16-Lead LLP Package
NS Package Number SQB16A
27
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