LM2722 [NSC]
High Speed Synchronous/Asynchronous MOSFET Driver; 高速同步/异步MOSFET驱动器
| 型号： | LM2722 |
| 厂家： | 
National Semiconductor |
| 描述： | High Speed Synchronous/Asynchronous MOSFET Driver |
| 文件： | 总8页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2001
LM2722
High Speed Synchronous/Asynchronous MOSFET Driver
average current. Input UVLO (Under-Voltage-Lock-Out)
forces both driver outputs low to ensure proper power-up
General Description
The LM2722, part of the LM2726 family, is designed to be
and power-down operation. The gate drive bias voltage
used with multi-phase controllers. This part differs from the
needed by the high side MOSFET is obtained through an
LM2726 by changing the functionality of the SYNC_EN pin
external bootstrap. Minimum pulse width is as low as 55ns.
from a whole chip enable to a low side MOSFET enable. As
a result, the SYNC_EN pin now provides control between
Synchronous and Asynchronous operations. Having this
Features
n Synchronous or Asynchronous Operation
n Adaptive shoot-through protection
n Input Under-Voltage-Lock-Out
n Typical 20ns internal delay
control can be advantageous in portable systems since
Asynchronous operations can be more efficient at very light
loads.
The LM2722 drives both top and bottom MOSFETs in a
push-pull structure simultaneously. It takes a logic level
PWM input and splits it into two complimentary signals with
n Plastic 8-pin SO package
a
typical 20ns dead time in between. The built-in
Applications
cross-conduction protection circuitry prevents the top and
bottom FETs from turning on simultaneously. The
cross-conduction protection circuitry detects both the driver
outputs and will not turn on a driver until the other driver
output is low. With a bias voltage of 5V, the peak sourcing
and sinking current for each driver of the LM2722 is typically
3A. In an SO-8 package, each driver is able to handle 50mA
n Driver for LM2723 Intel Mobile Northwood CPU core
power supply.
n High Current DC/DC Power Supplies
n High Input Voltage Switching Regulators
n Fast Transient Microprocessors
Typical Application
20028901
Note: National is an Intel Mobile Voltage Positioning (IMVP) licensee.
© 2001 National Semiconductor Corporation
DS200289
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Connection Diagram
8-Lead Small Outline Package
20028902
Top View
Ordering Information
Order Number
Package Type
LM2722M
LM2722MX
NSC Package Drawing
M08A
Supplied As
95 Units/Rail
2500 Units/Reel
LM2722
Pin Description
Pin
Name
Function
Top driver return. Should be connected to the common node of top
1
SW
HG
and bottom FETs
2
Top gate drive output
Bootstrap. Accepts a bootstrap voltage for powering the high-side
3
CBOOT
driver
4
5
6
7
8
PWM_IN
SYNC_EN
VCC
Accepts a 5V-logic control signal
Low gate Enable
Connect to +5V supply
Bottom gate drive output
Ground
LG
GND
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2
Block Diagram
20028904
3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
−65˚ to 150˚C
ESD Susceptibility
Human Body Model (Note 3)
Soldering Time, Temperature
1kV
10sec., 300˚C
VCC
7.5V
42V
CBOOT
Operating Ratings (Note 1)
CBOOT to SW
SW to PGND
Junction Temperature
Power Dissipation
(Note 2)
8V
VCC
4V to 7V
36V
Junction Temperature Range
−40˚ to 125˚C
+150˚C
720mW
Electrical Characteristics
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA
=
TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
POWER SUPPLY
Iq_op
Parameter
Condition
Min
Typ
Max
300
Units
Operating Quiescent
Current
PWM_IN = 0V
µA
190
TOP DRIVER
Peak Pull-Up Current
Test Circuit 1, Vbias = 5V, R
= 0.1Ω
3.0
1.0
A
Ω
A
Pull-Up Rds_on
ICBOOT = IHG = 0.7A
Test Circuit 2, Vbias = 5V, R
= 0.1Ω
Peak Pull-down Current
−3.2
Pull-down Rds_on
Rise Time
ISW = IHG = 0.7A
0.5
17
12
23
Ω
t4
t6
t3
t5
Timing Diagram, CLOAD
3.3nF
=
ns
ns
ns
Fall Time
Pull-Up Dead Time
Pull-Down Delay
Timing Diagram
Timing Diagram, from
PWM_IN Falling Edge
27
ns
BOTTOM DRIVER
Peak Pull-Up Current
Test Circuit 3, Vbias = 5V, R
= 0.1Ω
3.2
1.0
3.2
A
Ω
A
Pull-up Rds_on
IVCC = ILG = 0.7A
Test Circuit 4, Vbias = 5V, R
= 0.1Ω
Peak Pull-down Current
Pull-down Rds_on
Rise Time
IGND = ILG = 0.7A
0.5
17
14
28
Ω
t8
t2
t7
t1
Timing Diagram, CLOAD
3.3nF
=
ns
ns
ns
Fall Time
Pull-up Dead Time
Pull-down Delay
Timing Diagram
Timing Diagram, from
PWM_IN Rising Edge
13
ns
LOGIC
Vuvlo_up
Power On Threshold
VCC rises from 0V toward
5V
4
3.7
3.0
0.7
V
V
V
Vuvlo_dn
Under-Voltage-Lock-Out
Threshold
2.5
0.8
Vuvlo_hys
Under-Voltage-Lock-Out
Hysteresis
VIH_EN
VIL_EN
SYNC_EN Pin High Input
SYNC_EN Pin Low Input
2.4
V
V
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4
Electrical Characteristics (Continued)
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA
=
TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
Ileak_EN
Parameter
SYNC_EN Pin Leakage
Current
Condition
EN = 5V
EN = 0V
Min
−2
Typ
Max
2
Units
µA
−2
2
ton_min
Minimum Positive Input
Pulse Width
55
55
(Note 4)
ns
V
toff_min
Minimum Negative Input
Pulse Width
(Note 5)
VIH_PWM
VIL_PWM
PWM_IN High Level Input
Voltage
When PWM_IN pin goes
high from 0V
2.4
PWM_IN Low Level Input
Voltage
When PWM_IN pin goes
low from 5V
0.8
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates
correctly. Operating Ratings do not imply guaranteed performance limits.
Note 2: Maximum allowable power dissipation is a function of the maximum junction temperature, T
, the junction-to-ambient thermal resistance, θ , and the
JA
JMAX
ambient temperature, T . The maximum allowable power dissipation at any ambient temperature is calculated using: P
= (T
-T ) / θ . The junction-to-
JMAX A JA
A
MAX
ambient thermal resistance, θ , for the LM2722, it is 172˚C/W. For a T
of 150˚C and T of 25˚C, the maximum allowable power dissipation is 0.7W.
A
JA
JMAX
Note 3: ESD machine model susceptibility is 100V.
Note 4: If after a rising edge, a falling edge occurs sooner than the specified value, the IC may intermittently fail to turn on the bottom gate when the top gate is
off. As the falling edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.
Note 5: If after a falling edge, a rising edge occurs sooner than the specified value, the IC may intermittently fail to turn on the top gate when the bottom gate is
off. As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.
Timing Diagram
20028903
5
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Test Circuits
20028906
20028905
Test Circuit 2
Test Circuit 1
20028907
20028908
Test Circuit 3
Test Circuit 4
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6
Typical Waveforms
20028915
20028913
FIGURE 3. When Input Goes Low
FIGURE 1. Switching Waveforms of Test Circuit
20028916
20028914
FIGURE 4. Minimum Positive Pulse
FIGURE 2. When Input Goes High
Application Information
Minimum Pulse Width
IC may intermittently fail to turn on the bottom FET. As the
falling edge occurs sooner and sooner, the driver will start to
ignore the pulse and produce no output. This will result in the
toff inductor current taking a path through a diode provided
for non-synchronous operation. The circuit will resume syn-
chronous operation when the rising PWM pulses exceed
55ns in duration.
In order for the shoot-through prevention circuitry in the
LM2722 to work properly, the pulses into the PWM_IN pin
must be longer than 55ns. The internal logic waits until the
first FET is off plus 20ns before turning on the opposite FET.
If, after a falling edge, a rising edge occurs sooner than the
specified time, toff_min, the IC may intermittently fail to turn on
the top gate when the bottom gate is off. As the rising edge
occurs sooner and sooner, the driver may start to ignore the
pulse and produce no output. This condition results in the
PWM_IN pin in a high state and neither FET turned on. To
get out of this state, the PWM_IN pin must see a low signal
for greater than 55ns, before the rising edge.
High Input Voltages or High Output Currents
At input voltages above twice the output voltage and at
higher power levels, the designer may find snubber networks
and gate drive limiting useful in reducing EMI and preventing
injurious transients. A small resistor, 1Ω to 5Ω, between the
driver outputs and the MOSFET gates will slightly increase
the rise time and fall time of the output stage and reduce
switching noise. The trade-off is 1% to 2% in efficiency.
This will also assure that the gate drive bias voltage has
been restored by forcing the top FET source and Cboot to
ground first. Then the internal circuitry is reset and normal
operation will resume.
A series R-C snubber across in parallel with the bottom FET
can also be used to reduce ringing. Values of 10nF and 10Ω
to 100Ω are a good starting point.
Conversely, if, after a rising edge, a falling edge occurs
sooner than the specified miniumum pulse width, ton_min, the
7
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Physical Dimensions inches (millimeters)
unless otherwise noted
8-Lead Small Outline Package
NS Package Number M08A
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