LM3151MHX-2.5 [NSC]
IC SWITCHING CONTROLLER, 250 kHz SWITCHING FREQ-MAX, PDSO14, TSSOP-14, Switching Regulator or Controller;
| 型号： | LM3151MHX-2.5 |
| 厂家： | 
National Semiconductor |
| 描述： | IC SWITCHING CONTROLLER, 250 kHz SWITCHING FREQ-MAX, PDSO14, TSSOP-14, Switching Regulator or Controller 开关 光电二极管 |
| 文件： | 总21页 (文件大小：512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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August 26, 2009
LM3151/LM3152/LM3153
SIMPLE SWITCHER® CONTROLLER, High Input Voltage
Synchronous Step-Down
General Description
Features
The LM3151/2/3 SIMPLE SWITCHER® Controller is an easy
to use and simplified step down power controller capable of
providing up to 12A of output current in a typical application.
Operating with an input voltage range from 6V-42V, the
LM3151/2/3 features a fixed output voltage of 3.3V, and fea-
tures switching frequencies of 250 kHz, 500 kHz, and 750
kHz. The synchronous architecture provides for highly effi-
cient designs. The LM3151/2/3 controller employs a Constant
On-Time (COT) architecture with a proprietary Emulated Rip-
ple Mode (ERM) control that allows for the use of low ESR
output capacitors, which reduces overall solution size and
output voltage ripple. The Constant On-Time (COT) regula-
tion architecture allows for fast transient response and re-
quires no loop compensation, which reduces external com-
ponent count and reduces design complexity.
PowerWise® step-down controller
■
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■
■
■
■
■
■
■
■
■
■
6V to 42V Wide input voltage range
Fixed output voltage of 3.3V
Fixed switching frequencies of 250 kHz/500 kHz/750 kHz
No loop compensation required
Fully WEBENCH® enabled
Low external component count
Constant On-Time control
Ultra-Fast transient response
Stable with low ESR capacitors
Output voltage pre-bias startup
Valley current limit
Programmable soft-start
■
Fault protection features such as thermal shutdown, under-
voltage lockout, over-voltage protection, short-circuit protec-
tion, current limit, and output voltage pre-bias startup allow for
a reliable and robust solution.
The LM3151/2/3 SIMPLE SWITCHER® concept provides for
an easy to use complete design using a minimum number of
external components and National’s WEBENCH® online de-
sign tool. WEBENCH® provides design support for every step
of the design process and includes features such as external
component calculation with a new MOSFET selector, electri-
cal simulation, thermal simulation, and Build-It boards for
prototyping.
Typical Applications
Telecom
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Networking Equipment
Routers
Security Surveillance
Power Modules
■
Typical Application
30053201
SIMPLE SWITCHER® is a registered trademark of National Semiconductor Corporation
© 2009 National Semiconductor Corporation
300532
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Connection Diagram
30053202
eTSSOP-14
Ordering Information
Input
Voltage
Range
NSC Package
Drawing
Output
Voltage
Switching
Frequency
Order Number
LM3151MH-3.3
LM3151MHE-3.3
LM3151MHX-3.3
LM3152MH-3.3
LM3152MHE-3.3
LM3152MHX-3.3
LM3153MH-3.3
LM3153MHE-3.3
LM3153MHX-3.3
Package Type
Supplied As
94 Units per Anti-Static
Tube
250 Units in Tape and
Reel
eTSSOP-14
MXA14A
MXA14A
MXA14A
6V - 42V
6V - 33V
8V - 18V
3.3V
250KHz
500KHz
750KHz
2500 Units in Tape and
Reel
94 Units per Anti-Static
Tube
250 Units in Tape and
Reel
eTSSOP-14
eTSSOP-14
3.3V
3.3V
2500 Units in Tape and
Reel
94 Units per Anti-Static
Tube
250 Units in Tape and
Reel
2500 Units in Tape and
Reel
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2
Pin Descriptions
Pin
Name
Description
Function
Supply Voltage for Nominally regulated to 5.95V. Connect a 1 µF to 2.2 µF decoupling capacitor from this
1
VCC
FET Drivers
pin to ground.
Supply pin to the device. Nominal input range is 6V to 42V. See ordering information
for Vin limitations.
2
3
VIN
EN
Input Supply Voltage
To enable the IC apply a logic high signal to this pin greater than 1.26V typical or leave
floating. To disable the part, ground the EN pin.
Enable
Internally connected to the resistor divider network which sets the fixed output voltage.
This pin also senses the output voltage faults such a over-voltage and short circuit
conditions.
4
FB
Feedback
Ground for all internal bias and reference circuitry. Should be connected to PGND at a
single point.
5,9
6
SGND
SS
Signal Ground
Soft-Start
An internal 7.7 µA current source charges an external capacitor to provide the soft-start
function.
Internally not electrically connected. These pins may be left unconnected or connected
to ground.
7,8
10
11
N/C
SW
Not Connected
Switch Node
Switch pin of controller and high-gate driver lower supply rail. A boost capacitor is also
connected between this pin and BST pin
High-Side Gate
Drive
Gate drive signal to the high-side NMOS switch. The high-side gate driver voltage is
supplied by the differential voltage between the BST pin and SW pin.
HG
High-gate driver upper supply rail. Connect a 0.33 µF-0.47 µF capacitor from SW pin to
this pin. An internal diode charges the capacitor during the high-side switch off-time. Do
not connect to an external supply rail.
Connection for
Bootstrap Capacitor
12
BST
Gate drive signal to the low-side NMOS switch. The low-side gate driver voltage is
supplied by VCC.
13
14
EP
LG
PGND
EP
Low-Side Gate Drive
Power Ground
Synchronous rectifier MOSFET source connection. Tie to power ground plane. Should
be tied to SGND at a single point.
Exposed die attach pad should be connected directly to SGND. Also used to help
dissipate heat out of the IC.
Exposed Pad
3
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Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN
6V to 42V
−40°C to + 125°C
0V to 5V
Junction Temperature Range (TJ)
EN
VIN to GND
-0.3V to 47V
-3V to 47V
SW to GND
BST to SW
BST to GND
All Other Inputs to GND
ESD Rating (Note 2)
Storage Temperature Range
-0.3V to 7V
-0.3V to 52V
-0.3V to 7V
2kV
-65°C to +150°C
Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the
junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Unless otherwise stated the following conditions apply: VIN = 18V.
Symbol
Start-Up Regulator, VCC
VCC
Parameter
Conditions
Min
Typ
Max
Units
CVCC = 1 µF, 0 mA to 40 mA
IVCC = 2 mA, Vin = 5.5V
IVCC = 30 mA, Vin = 5.5V
VCC = 0V
5.65
5.95
40
6.25
V
VIN - VCC
VIN - VCC Dropout Voltage
mV
330
100
5.1
IVCCL
VCC Current Limit (Note 3)
65
mA
V
VCC Under-voltage Lockout threshold
(UVLO)
4.75
5.40
VCCUVLO
VCC Increasing
VCC Decreasing
VCC-UVLO-HYS
tCC-UVLO-D
IIN
VCC UVLO Hysteresis
VCC UVLO Filter Delay
Input Operating Current
475
3
mV
µs
3.6
32
5.2
55
No Switching
VEN = 0V
mA
Input Operating Current, Device
Shutdown
IIN-SD
µA
GATE Drive
IQ-BST
RDS-HG-Pull-Up
RDS-HG-Pull-Down
RDS-LG-Pull-Up
RDS-LG-Pull-Down
Soft-Start
ISS
VBST – VSW = 6V
2
5
Boost Pin Leakage
nA
Ω
IHG Source = 200 mA
IHG Sink = 200 mA
ILG Source = 200 mA
ILG Sink = 200 mA
HG Drive Pull–Up On-Resistance
HG Drive Pull–Down On-Resistance
LG Drive Pull–Up On-Resistance
LG Drive Pull–Down On-Resistance
3.4
3.4
2
Ω
Ω
Ω
VSS = 0V
5.9
7.7
9.5
SS Pin Source Current
mA
µA
ISS-DIS
200
SS Pin Discharge Current
Current Limit
VCL
175
200
225
Current Limit Voltage Threshold
mV
ON/OFF Timer
tON-MIN
200
370
ON Timer Minimum Pulse Width
OFF Timer Minimum Pulse Width
ns
ns
tOFF
525
Enable Input
VEN
VEN Rising
VEN Falling
1.14
1.20
120
1.26
EN Pin Input Threshold Trip Point
EN Pin threshold Hysteresis
V
VEN-HYS
mV
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4
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Boost Diode
IBST = 2 mA
0.7
1
V
V
Vf
Forward Voltage
IBST = 30 mA
Thermal Characteristics
Thermal Shutdown
Rising
Falling
165
15
°C
°C
TSD
Thermal Shutdown Hysteresis
4 Layer JEDEC Printed Circuit
Board, 9 Vias, No Air Flow
40
θJA
θJC
Junction to Ambient
°C/W
°C/W
2 Layer JEDEC Printed Circuit
Board. No Air Flow
140
4
Junction to Case
No Air Flow
3.3V Output Option
Symbol
Parameter
Conditions
Min
3.234
3.83
Typ
3.3
4.00
42
33
18
6
Max
3.366
4.17
Units
VOUT
Output Voltage
V
V
VOUT-OV
Output Voltage Over-Voltage Threshold
LM3151-3.3
VIN-MAX
Maximum Input Voltage (Note 4)
Minimum Input Voltage (Note 4)
LM3152-3.3
V
V
LM3153-3.3
LM3151-3.3
VIN-MIN
LM3152-3.3
6
LM3153-3.3
8
250
LM3151-3.3, RON = 115 kΩ
500
750
730
400
330
566
fS
Switching Frequency
LM3152-3.3, RON = 51 kΩ
LM3153-3.3, RON = 32 kΩ
LM3151-3.3, RON = 115 kΩ
LM3152-3.3, RON = 51 kΩ
LM3153-3.3, RON = 32 kΩ
kHz
tON
On-Time
ns
RFB
FB Resistance to Ground
kΩ
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test Method is per JESD-22-A114.
Note 3: VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
Note 4: The input voltage range is dependent on minimum on-time, off-time, and therefore frequency, and is also affected by optimized MOSFET selection.
5
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Simplified Block Diagram
30053203
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6
Typical Performance Characteristics
Boost Diode Forward Voltage vs. Temperature
Quiescent Current vs. Temperature
30053240
30053242
Soft-Start Current vs. Temperature
VCC Current Limit vs. Temperature
30053243
30053247
VCC Dropout vs. Temperature
VCC vs. Temperature
30053248
30053249
7
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VCL vs. Temperature
On-Time vs. Temperature (250 kHz)
30053282
30053283
On-Time vs. Temperature (500 kHz)
On-Time vs. Temperature (750 kHz)
30053284
30053286
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1) Minimum off time as specified in the electrical characteris-
tics table
Theory of Operation
The LM3151/2/3 synchronous step-down SIMPLE SWITCH-
ER® Controller employs a Constant On-Time (COT) archi-
tecture which is a derivative of the hysteretic control scheme.
COT relies on a fixed switch on-time to regulate the output.
The on-time of the high-side switch is set internally by resistor
RON. The LM3151/2/3 automatically adjusts the on-time in-
versely with the input voltage to maintain a constant frequen-
cy. Assuming an ideal system and VIN is much greater than
1V, the following approximations can be made:
2) The error comparator sampled voltage falls below 0.6V
Over-Voltage Comparator
The over-voltage comparator is provided to protect the output
from over-voltage conditions due to sudden input line voltage
changes or output loading changes. The over-voltage com-
parator continuously monitors the attenuated FB voltage ver-
sus a 0.72V internal reference. If the voltage at FB rises above
0.72V the on-time pulse is immediately terminated. This con-
dition can occur if the input or the output load changes sud-
denly. Once the over-voltage protection is activated, the HG
and LG signals remain off until the attenuated FB voltage falls
below 0.72V.
The on-time, tON
:
Current Limit
Where K = 100 pC, and RON is specified in the electrical char-
acteristics table.
Current limit detection occurs during the off-time by monitor-
ing the current through the low-side switch. If during the off-
time the current in the low-side switch exceeds the user
defined current limit value, the next on-time cycle is immedi-
ately terminated. Current sensing is achieved by comparing
the voltage across the low-side switch against an internal ref-
erence value, VCL, of 200 mV. If the voltage across the low-
side switch exceeds 200 mV, the current limit comparator will
trigger logic to terminate the next on-time cycle. The current
limit ICL, can be determined as follows:
Control is based on a comparator and the on-timer, with the
output voltage feedback (FB) attenuated and then compared
with an internal reference of 0.6V. If the attenuated FB level
is below the reference, the high-side switch is turned on for a
fixed time, tON, which is determined by the input voltage and
the internal resistor, RON. Following this on-time, the switch
remains off for a minimum off-time, tOFF, as specified in the
Electrical Characteristics table or until the attenuated FB volt-
age is less than 0.6V. This switching cycle will continue while
maintaining regulation. During continuous conduction mode
(CCM), the switching frequency depends only on duty cycle
and on-time. The duty cycle can be calculated as:
Where IOCL is the user-defined average output current limit
value, RDS(ON)max is the resistance value of the low-side FET
at the expected maximum FET junction temperature, VCL is
the internal current limit reference voltage and Tj is the junc-
tion temperature of the LM3151/2/3.
Where the switching frequency of a COT regulator is:
Figure 1 illustrates the inductor current waveform. During nor-
mal operation, the output current ripple is dictated by the
switching of the FETs. The current through the low-side
switch, Ivalley, is sampled at the end of each switching cycle
and compared to the current limit threshold voltage, VCL. The
valley current can be calculated as follows:
Typical COT hysteretic controllers need a significant amount
of output capacitor ESR to maintain a minimum amount of
ripple at the FB pin in order to switch properly and maintain
efficient regulation. The LM3151/2/3 however utilizes propri-
etary, Emulated Ripple Mode Control Scheme (ERM) that
allows the use of ceramic output capacitors without additional
equivalent series resistance (ESR) compensation. Not only
does this reduce the need for output capacitor ESR, but also
significantly reduces the amount of output voltage ripple seen
in a typical hysteretic control scheme. The output ripple volt-
age can become so low that it is comparable to voltage-mode
and current-mode control schemes.
Where IOUT is the average output current and ΔIL is the peak-
to-peak inductor ripple current.
If an overload condition occurs, the current through the low-
side switch will increase which will cause the current limit
comparator to trigger the logic to skip the next on-time cycle.
The IC will then try to recover by checking the valley current
during each off-time. If the valley current is greater than or
equal to ICL, then the IC will keep the low-side FET on and
allow the inductor current to further decay.
Regulation Comparator
The output voltage is sampled through the FB pin and then
divided down by two internal resistors and compared to the
internal reference voltage of 0.6V by the error comparator. In
normal operation, an on-time period is initiated when the sam-
pled output voltage at the input of the error comparator falls
below 0.6V. The high-side switch stays on for the specified
on-time, causing the sampled voltage on the error comparator
input to rise above 0.6V. After the on-time period, the high-
side switch stays off for the greater of the following:
Throughout the whole process, regardless of the load current,
the on-time of the controller will stay constant and thereby the
positive ripple current slope will remain constant. During each
on-time the current ramps up an amount equal to:
9
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the inductor current is forced to decay following any overload
conditions.
The valley current limit feature prevents current runaway con-
ditions due to propagation delays or inductor saturation since
30053212
FIGURE 1. Inductor Current - Current Limit Operation
An internal switch grounds the SS pin if VCC is below the
under-voltage lockout threshold, if a thermal shutdown oc-
curs, or if the EN pin is grounded. By using an externally
controlled switch, the output voltage can be shut off by
grounding the SS pin.
Short-Circuit Protection
The LM3151/2/3 will sense a short-circuit on the output by
monitoring the output voltage. When the attenuated feedback
voltage has fallen below 60% of the reference voltage, Vref
x
0.6 (≈0.36V), short-circuit mode of operation will start. During
short-circuit operation, the SS pin is discharged and the out-
put voltage will fall to 0V. The SS pin voltage, VSS, is then
ramped back up at the rate determined by the SS capacitor
and ISS until VSS reaches 0.7V. During this re-ramp phase, if
the short-circuit fault is still present the output current will be
equal to the set current limit. Once the soft-start voltage
reaches 0.7V the output voltage is sensed again and if the
attenuated VFB is still below Vref x 0.6 then the SS pin is dis-
charged again and the cycle repeats until the short-circuit fault
is removed.
During startup the LM3151/2/3 will operate in diode emulation
mode, where the low-side gate LG will turn off and remain off
when the inductor current falls to zero. Diode emulation mode
allows for start up into a pre-biased output voltage. When soft-
start is greater than 0.7V, the LM3151/2/3 will remain in
continuous conduction mode. During diode emulation mode
at current limit the low-gate will remain off when the inductor
current is off.
The soft start time should be greater than the rise time spec-
ified by,
tSS ≥ (VOUT x COUT) / (IOCL - IOUT
)
Soft-Start
Enable/Shutdown
The soft-start (SS) feature allows the regulator to gradually
reach a steady-state operating point, which reduces start-up
stresses and current surges. At turn-on, while VCC is below
the under-voltage threshold, the SS pin is internally grounded
and VOUT is held at 0V. The SS capacitor is used to slowly
ramp VFB from 0V to it's final output voltage as programmed
by the internal resistor divider. By changing the soft-start ca-
pacitor value, the duration of start-up can be changed ac-
cordingly. The start-up time can be calculated using the
following equation:
The EN pin can be activated by either leaving the pin floating
due to an internal pull up resistor to VIN or by applying a logic
high signal to the EN pin of 1.26V or greater. The LM3151/2/3
can be remotely shut down by taking the EN pin below 1.02V.
Low quiescent shutdown is achieved when VEN is less than
0.4V. During low quiescent shutdown the internal bias circuit-
ry is turned off.
The LM3151/2/3 has certain fault conditions that can trigger
shutdown, such as over-voltage protection, current limit, un-
der-voltage lockout, or thermal shutdown. During shutdown,
the soft-start capacitor is discharged. Once the fault condition
is removed, the soft-start capacitor begins charging, allowing
the part to start up in a controlled fashion. In conditions where
there may be an open drain connection to the EN pin, it may
be necessary to add a 1000 pF bypass capacitor to this pin.
This will help decouple noise from the EN pin and prevent
false disabling.
Where tSS is measured in seconds, Vref = 0.6V and ISS is the
soft-start pin source current, which is typically 7.7 µA (refer to
electrical characteristics table).
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10
c. Target Switching Frequency
Thermal Protection
2. Determine which IC Controller to Use
The LM3151/2/3 should be operated such that the junction
temperature does not exceed the maximum operating junc-
tion temperature. An internal thermal shutdown circuit, which
activates at 165°C (typical), takes the controller to a low-pow-
er reset state by disabling the buck switch and the on-timer,
and grounding the SS pin. This feature helps prevent catas-
trophic failures from accidental device overheating. When the
junction temperature falls back below 150°C the SS pin is re-
leased and normal operation resumes.
The desired input voltage range will determine which version
of the LM3151/2/3 controller will be chosen. The higher
switching frequency options allow for physically smaller in-
ductors but efficiency may decrease.
3. Determine Inductor Required Using Figure 2
To use the nomograph below calculate the inductor volt-mi-
crosecond constant ET from the following formula:
Design Guide
The design guide provides the equations required to design
with the LM3151/2/3 SIMPLE SWITCHER® Controller.
WEBENCH® design tool can be used with or in place of this
section for a more complete and simplified design process.
Where fS is in kHz units. The intersection of the Load Current
and the Volt-microseconds lines on the chart below will de-
termine which inductors are capable for use in the design. The
chart shows a sample of parts that can be used. The offline
calculator tools and WEBENCH® will fully calculate the re-
quirements for the components needed for the design.
1. Define Power Supply Operating Conditions
a. Maximum and Minimum DC Input voltage
b. Maximum Expected Load Current during normal operation
30053252
FIGURE 2. Inductor Nomograph
11
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TABLE 1. Inductor Selection Table
Inductor Designator
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
L32
L33
L34
L35
L36
L37
L38
L39
L40
L41
L42
L43
L44
L45
L46
L47
L48
Inductance (µH)
Current (A)
7-9
Part Name
Vendor
47
33
7-9
SER2817H-333KL
SER2814H-223KL
7447709150
COILCRAFT
COILCRAFT
WURTH
22
7-9
15
7-9
10
7-9
RLF12560T-100M7R5
B82477-G4682-M
B82477-G4472-M
DR1050-3R3-R
MSS1048-222
TDK
6.8
4.7
3.3
2.2
1.5
1
7-9
EPCOS
7-9
EPCOS
7-9
COOPER
COILCRAFT
BOURNS
COILCRAFT
COILCRAFT
7-9
7-9
SRU1048-1R5Y
DO3316P-102
7-9
0.68
33
7-9
DO3316H-681
9-12
9-12
9-12
9-12
9-12
9-12
9-12
9-12
9-12
9-12
9-12
9-12
12-15
12-15
12-15
12-15
12-15
12-15
12-15
12-15
12-15
12-15
12-15
12-15
15-
22
SER2918H-223
SER2814H-153KL
7447709100
COILCRAFT
COILCRAFT
WURTH
15
10
6.8
4.7
3.3
2.2
1.5
1
SPT50H-652
COILCRAFT
COILCRAFT
COILCRAFT
COOPER
SER1360-472
MSS1260-332
DR1050-2R2-R
DR1050-1R5-R
DO3316H-102
COOPER
COILCRAFT
0.68
0.47
22
SER2817H-223KL
COILCRAFT
15
10
SER2814L-103KL
7447709006
COILCRAFT
WURTH
6.8
4.7
3.3
2.2
1.5
1
7447709004
WURTH
MLC1245-152
DO3316H-681
DR73-R33-R
COILCRAFT
COILCRAFT
COOPER
0.68
0.47
0.33
22
15
15-
SER2817H-153KL
SER2814H-103KL
COILCRAFT
COILCRAFT
10
15-
6.8
4.7
3.3
2.2
1.5
1
15-
15-
SER2013-472ML
SER2013-362L
COILCRAFT
COILCRAFT
15-
15-
15-
HA3778-AL
COILCRAFT
EPCOS
15-
B82477-G4102-M
0.68
0.47
0.33
15-
15-
15-
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12
4. Determine Output Capacitance
Typical hysteretic COT converters similar to the LM3151/2/3
require a certain amount of ripple that is generated across the
ESR of the output capacitor and fed back to the error com-
parator. Emulated Ripple Mode control built into the
LM3151/2/3 will recreate a similar ripple signal and thus the
requirement for output capacitor ESR will decrease compared
to a typical Hysteretic COT converter. The emulated ripple is
generated by sensing the voltage signal across the low-side
FET and is then compared to the FB voltage at the error com-
parator input to determine when to initiate the next on-time
period.
COmin = 70 / (fs2 x L)
The maximum ESR allowed to prevent over-voltage protec-
tion during normal operation is:
ESRmax = (80 mV x L) / ETmin
30053281
ETmin is calculated using VIN-MIN
FIGURE 3. Typical MOSFET Gate Charge Curve
The minimum ESR must meet both of the following criteria:
See following design example for estimated power dissipation
calculation.
ESRmin ≥ (15 mV x L) / ETmax
6. Calculate Input Capacitance
ESRmin ≥ [ETmax / (VIN - VOUT)]/ CO
The main parameters for the input capacitor are the voltage
rating, which must be greater than or equal to the maximum
DC input voltage of the power supply, and its rms current rat-
ing. The maximum rms current is approximately 50% of the
maximum load current.
ETmax is calculated using VIN-MAX
.
Any additional parallel capacitors should be chosen so that
their effective impedance will not negatively attenuate the
output ripple voltage.
5. MOSFET Selection
The high-side and low-side FETs must have a drain to source
(VDS) rating of at least 1.2 x VIN.
The gate drive current from VCC must not exceed the mini-
mum current limit of VCC. The drive current from VCC can be
calculated with:
Where, ΔVIN-MAX is the maximum allowable input ripple volt-
age. A good starting point for the input ripple voltage is 5% of
VIN.
IVCCdrive = Qgtotal x fS
Where, Qgtotal is the combined total gate charge of the high-
side and low-side FETs.
When using low ESR ceramic capacitors on the input of the
LM3151/2/3 a resonant circuit can be formed with the
impedance of the input power supply and parasitic impedance
of long leads/PCB traces to the LM3151/2/3 input capacitors.
It is recommended to use a damping capacitor under these
circumstances, such as aluminum electrolytic that will prevent
ringing on the input. The damping capacitor should be chosen
to be approximately 5 times greater than the parallel ceramic
capacitors combination. The total input capacitance should
be greater than 10 times the input inductance of the power
supply leads/pcb trace. The damping capacitor should also
be chosen to handle its share of the rms input current which
is shared proportionately with the parallel impedance of the
ceramic capacitors and aluminum electrolytic at the
LM3151/2/3 switching frequency.
Use the following equations to calculate the current limit, ICL
,
as shown in Figure 1.
Tj is the junction temperature of the LM3151/2/3.
The plateau voltage of the FET VGS vs Qg curve, as shown in
Figure 3 must be less than VCC - 750 mV.
The CBYP capacitor should be placed directly at the VIN pin.
The recommended value is 0.1 µF.
7. Calculate Soft-Start Capacitor
Where tSS is the soft-start time in seconds and Vref = 0.6V.
13
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8. CVCC, and CBST and CEN
high-side FET. It is charged during the SW off-time. The rec-
ommended value for CBST is 0.47 µF. The EN bypass capac-
itor, CEN, recommended value is 1000 pF when driving the EN
pin from open drain type of signal.
CVCC should be placed directly at the VCC pin with a recom-
mended value of 1 µF to 2.2 µF. For input voltage ranges that
include voltages below 8V a 1 µF capacitor must be used for
CVCC. CBST creates a voltage used to drive the gate of the
Design Example
30053261
FIGURE 4. Design Example Schematic
1. Define Power Supply Operating Conditions
a. VOUT = 3.3V
b. VIN-MIN = 6V, VIN-TYP = 12V, VIN-MAX = 24V
c. Typical Load Current = 12A, Max Load Current = 15A
d. Soft-Start time tSS = 5 ms
For this design the chosen ripple current ratio, r = 0.3, repre-
sents the ratio of inductor peak-to-peak current to load current
Iout. A good starting point for ripple ratio is 0.3 but it is ac-
ceptable to choose r between 0.25 to 0.5. The nomographs
in this datasheet all use 0.3 as the ripple current ratio.
2. Determine which IC Controller to Use
The LM3151 and LM3152 allow for the full input voltage
range. However, from buck converter basic theory, the higher
switching frequency will allow for a smaller inductor. There-
fore, the LM3152-3.3 500 kHz part is chosen so that a smaller
inductor can be used.
3. Determine Inductor Required
Irmsco = 1A
a. ET = (24-3.3) x (3.3/24) x (1000/500) = 5.7 V µs
tON = (3.3V/12V) / 500 kHz = 550 ns
b. From the inductor nomograph a 12A load and 5.7 V µs cal-
culation corresponds to a L44 type of inductor.
Minimum output capacitance is:
COmin = 70 / (fS2 x L)
c. Using the inductor designator L44 in Table 1 the Coilcraft
HA3778-AL 1.65 µH inductor is chosen.
COmin = 70 / (500 kHz2 x 1.65 µH) = 169 µF
4. Determine Output Capacitance
The voltage rating on the output capacitor should be greater
than or equal to the output voltage. As a rule of thumb most
capacitor manufacturers suggests not to exceed 90% of the
capacitor rated voltage. In the case of multilayer ceramics the
capacitance will tend to decrease dramatically as the applied
voltage is increased towards the capacitor rated voltage. The
capacitance can decrease by as much as 50% when the ap-
plied voltage is only 30% of the rated voltage. The chosen
capacitor should also be able to handle the rms current which
is equal to:
The maximum ESR allowed to prevent over-voltage protec-
tion during normal operation is:
ESRmax = (80 mV x L) / ET
ESRmax = (80 mV x 1.65 µH) / 5.7 V µs
ESRmax = 23 mΩ
The minimum ESR must meet both of the following criteria:
ESRmin ≥ (15 mV x L) / ET
www.national.com
14
tion temperature rise above ambient temperature and θJA
30°C/W, can be estimated by:
=
ESRmin ≥ [ET / (VIN - VOUT)] / CO
ESRmin ≥ (15 mV x 1.65 µH) / 5.7 V µs = 4.3 mΩ
Pdmax = 125°C / 30°C/W = 4.1W
The system calculated Pdh of 0.674W is much less than the
FET Pdmax of 4.1W and therefore the RJK0305DPB max al-
lowable power dissipation criteria is met.
ESRmin ≥ [5.7 V µs / (12 - 3.3)] / 169 µF = 3.9 mΩ
Based on the above criteria two 150 µF polymer aluminum
capacitors with a ESR = 12 mΩ each for a effective ESR in
parallel of 6 mΩ was chosen from Panasonic. The part num-
ber is EEF-UE0J151P.
Low-Side MOSFET
Primary loss is conduction loss given by:
Pdl = Iout2 x RDS(ON) x (1-D) = 122 x 0.01 x (1-0.275) = 1W
5. MOSFET Selection
The LM3151/2/3 are designed to drive N-channel MOSFETs.
For a maximum input voltage of 24V we should choose N-
channel MOSFETs with a maximum drain-source voltage,
VDS, greater than 1.2 x 24V = 28.8V. FETs with maximum
VDS of 30V will be the first option. The combined total gate
charge Qgtotal of the high-side and low-side FET should satisfy
the following:
Pdl is also less than the Pdmax specified on the RJK0305DPB
MOSFET datasheet.
However, it is not always necessary to use the same MOS-
FET for both the high-side and low-side. For most applications
it is necessary to choose the high-side MOSFET with the low-
est gate charge and the low-side MOSFET is chosen for the
lowest allowed RDS(ON). The plateau voltage of the FET VGS
vs Qg curve must be less than VCC - 750 mV.
Qgtotal ≤ IVCCL / fs
Qgtotal ≤ 65 mA / 500 kHz
Qgtotal ≤ 130 nC
The current limit, IOCL, is calculated by estimating the RDS
(ON) of the low-side FET at the maximum junction temperature
of 100°C. Then the following calculation of IOCL is:
IOCL = ICL + ΔIL / 2
Where IVCCL is the minimum current limit of VCC, over the
temperature range, specified in the electrical characteristics
table. The MOSFET gate charge Qg is gathered from reading
ICL = 200 mV / 0.014 = 14.2A
IOCL = 14.2A + 3.6 / 2 = 16A
the VGS vs Qg curve of the MOSFET datasheet at the VGS
=
6. Calculate Input Capacitance
5V for the high-side, M1, MOSFET and VGS = 6V for the low-
side, M2, MOSFET.
The input capacitor should be chosen so that the voltage rat-
ing is greater than the maximum input voltage which for this
example is 24V. Similar to the output capacitor, the voltage
rating needed will depend on the type of capacitor chosen.
The input capacitor should also be able to handle the input
rms current which is approximately 0.5 x IOUT. For this exam-
ple the rms input current is approximately 0.5 x 12A = 6A.
The Renesas MOSFET RJK0305DPB has a gate charge of
10 nC at VGS = 5V, and 12 nC at VGS = 6V. This combined
gate charge for a high-side, M1, and low-side, M2, MOSFET
12 nC + 10 nC = 22 nC is less than 130 nC calculated
Qgtotal
.
The calculated MOSFET power dissipation must be less than
the max allowed power dissipation, Pdmax, as specified in the
MOSFET datasheet. An approximate calculation of the FET
power dissipated Pd, of the high-side and low-side FET is
given by:
The minimum capacitance with a maximum 5% input ripple
ΔVIN-MAX = (0.05 x 12) = 0.6V:
CIN = [12 x 0.275 x (1-0.275)] / [500 kHz x 0.6] = 8 µF
To handle the large input rms current 2 ceramic capacitors
are chosen at 10 µF each with a voltage rating of 50V and
case size of 1210, that can handle 3A of rms current each. A
100 µF aluminum electrolytic is chosen to help dampen input
ringing.
High-Side MOSFET
CBYP = 0.1 µF ceramic with a voltage rating greater than max-
imum VIN
7. Calculate Soft-Start Capacitor
The soft start-time should be greater than the input voltage
rise time and also satisfy the following equality to maintain a
smooth transition of the output voltage to the programmed
regulation voltage during startup.
tSS ≥ (VOUT x COUT) / (IOCL - IOUT
)
5 ms > (3.3V x 300 µF) / (1.2 x 12A - 12A)
5 ms > 0.412 ms
The max power dissipation of the RJK0305DPB is rated as
45W for a junction temperature that is 125°C higher than the
case temperature and a thermal resistance from the FET
junction to case, θJC, of 2.78°C/W. When the FET is mounted
onto the PCB, the PCB will have some additional thermal re-
sistance such that the total system thermal resistance of the
FET package and the PCB, θJA, is typically in the range of 30°
C/W for this type of FET package. The max power dissipation,
Pdmax, with the FET mounted onto a PCB with a 125°C junc-
The desired soft-start time, tSS, of 5 ms satisfies the equality
as shown above. Therefore, the soft-start capacitor, CSS, is
calculated as:
CSS = (7.7 µA x 5 ms) / 0.6V = 0.064 µF
15
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Let CSS = 0.068 µF, which is the next closest standard value.
This should be a ceramic cap with a voltage rating greater
than 10V.
8. CVCC, CEN, and CBST
CVCC = 1µF ceramic with a voltage rating greater than 10V
CEN = 1000 pF ceramic with a voltage rating greater than 10V
CBST = 0.47 µF ceramic with a voltage rating greater than 10V
Bill of Materials
Designator
CBST
Value
0.47 µF
0.1 µF
1000 pF
100 µF
10 µF
Parameters
Manufacturer
TDK
Part Number
C2012X7R1C474K
C2012X7R1H104K
C1608X7R1H102K
EEV-FK1J101P
Ceramic, X7R, 16V, 10%
Ceramic, X7R, 50V, 10%
Ceramic, X7R, 50V, 10%
AL, EEV-FK, 63V, 20%
Ceramic, X5R, 35V, 10%
AL, UE, 6.3V, 20%
CBYP
TDK
CEN
TDK
CIN1
Panasonic
Taiyo Yuden
Panasonic
CIN2, CIN3
COUT1, COUT2
CSS
GMK325BJ106KN-T
EEF-UE0J151R
0603YC683KAT2A
C0805C105K4RACTU
HA3778-AL
150 µF
0.068 µF
1 µF
Ceramic, 16V, 10%
CVCC
Ceramic, X7R, 16V, 10%
Kemet
Coilcraft Inc.
L1
1.65 µH
30V
Shielded Drum Core, A, 2.53 mΩ
8 nC, RDS(ON) @4.5V = 10 mΩ
M1, M2
Renesas
RJK0305DB
U1
National Semiconductor
LM3152MH-3.3
www.national.com
16
going to be the largest heat generating devices in the design,
and as such, care should be taken to remove the heat. On
multi layer boards using exposed-pad packages for the FET’s
such as the power-pak SO-8, vias should be used under the
FETs to the same plane on the interior layers to help dissipate
the heat and cool the FETs. For the typical single FET Power-
Pak type FETs the high-side FET DAP is Vin. The Vin plane
should be copied to the other interior layers to the bottom layer
for maximum heat dissipation. Likewise, the DAP of the low-
side FET is connected to the SW node and it’s shape should
be duplicated to the interior layers down to the bottom layer
for maximum heat dissipation.
PCB Layout Considerations
It is good practice to layout the power components first, such
as the input and output capacitors, FETs, and inductor. The
first priority is to make the loop between the input capacitors
and the source of the low side FET to be very small and tie
the grounds of each directly to each other and then to the
ground plane through vias. As shown in the figure below,
when the input cap ground is tied directly to the source of the
low side FET, parasitic inductance in the power path, along
with noise coupled into the ground plane, are reduced.
The switch node is the next item of importance. The switch
node should be made only as large as required to handle the
load current. There are fast voltage transitions occurring in
the switch node at a high frequency, and if the switch node is
made too large it may act as an antennae and couple switch-
ing noise into other parts of the circuit. For high power designs
it is recommended to use a multi-layer board. The FET’s are
See the Evaluation Board application note AN-1900 for an
example of a typical multilayer board layout, and the Demon-
stration Board Reference Design App Note for a typical 2 layer
board layout. Each design allows for single sided component
mounting.
30053258
FIGURE 5. Schematic of Parasitics
30053280
FIGURE 6. PCB Placement of Power Stage
17
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead eTSSOP Package
NS Package Number MXA14A
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18
Notes
19
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