LM3431MH [NSC]
3-Channel Constant Current LED Driver with Integrated Boost Controller; 3通道恒流LED驱动器，集成升压控制器
| 型号： | LM3431MH |
| 厂家： | 
National Semiconductor |
| 描述： | 3-Channel Constant Current LED Driver with Integrated Boost Controller |
| 文件： | 总24页 (文件大小：539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 20, 2007
LM3431/LM3431A
3-Channel Constant Current LED Driver with Integrated
Boost Controller
General Description
The LM3431 is a 3-channel linear current controller combined
with a boost switching controller ideal for driving LED back-
light panels in space critical applications. The LM3431 drives
3 external NPN transistors or MOSFETs to deliver high ac-
curacy constant current to 3 LED strings. Output current is
adjustable to drive strings in excess of 200 mA. The LM3431
can be expanded to drive as many as 6 LED strings.
Features
3-channel programmable LED current
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High accuracy linear current regulation
Analog and digital PWM dimming control
Up to 25kHz dimming frequency
>100:1 contrast ratio
Integrated Boost controller
The boost controller drives an external NFET switch for step-
up regulation from input voltages between 5V and 36V. The
LM3431 features LED cathode feedback to minimize regula-
tor headroom and optimize efficiency.
5V-36V input voltage range
Adjustable switching frequency up to 1MHz
LED short and open protection
Selectable fault shutdown or automatic restart
A DIM input pin controls LED brightness from analog or digital
control signals. Dimming frequencies up to 25 kHz are pos-
sible with a contrast ratio of 100:1. Contrast ratios greater than
1000:1 are possible at lower dimming frequencies.
Programmable fault delay
Programmable cycle by cycle current limit
Output Over Voltage Protection
The LM3431 eliminates audible noise problems by maintain-
ing constant output voltage regulation during LED dimming.
Additional features include LED short and open protection,
fault delay/error flag, cycle by cycle current limit, and thermal
shutdown for both the IC and LED array. The enhanced
LM3431A features reduced offset voltge for higher accuracy
LED current.
No Audible Noise
Enable pin
LED Over-Temperature shutdown input
Thermal Shutdown
■
TSSOP-28 exposed pad package
■
Applications
Automotive Infotainment Displays
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Small to Medium Format Displays
Typical Application Circuit
30041101
© 2008 National Semiconductor Corporation
300411
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Connection Diagram
30041102
Top View
28 Lead Plastic Exposed Pad TSSOP
Ordering Information
Order Number
LM3431MHX
LM3431MH
Operating Temp Range
Package Type
TSSOP-28
TSSOP-28
TSSOP-28
TSSOP-28
Package Drawing
MXA28A
Supplied As
Tape and Reel of 2500 Units
Rail of 48 Units
-40°C to 125°C
-40°C to 125°C
-40°C to 125°C
-40°C to 125°C
MXA28A
LM3431AMHX
LM3431AMH
MXA28A
Tape and Reel of 2500 Units
Rail of 48 Units
MXA28A
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Pin Descriptions
Pin #
Pin Name
VIN
Description
1
2
3
4
5
6
Power supply input.
PGND
VCC
LG
Power ground pin. Connect to ground.
Internal reference voltage output. Bypass to PGND with a minimum 4.7 µF capacitor.
Boost controller gate drive output. Connect to the NFET gate.
CS
Boost controller current sense pin. Connect to the top side of the boost current sense resistor.
ILIM
Boost controller current limit adjust pin. Connect a resistor from this pin to the Boost current sense resistor
to set the current limit threshold.
7
8
9
MODE/F
FF
Dimming mode selection pin. Pull high for digital PWM control. Or connect to a capacitor to GND to set
the internal dimming frequency.
Feedforward pin. Connect to a resistor to ground to control the output voltage over/undershoot during
PWM dimming.
RT
Frequency adjust pin. Connect a resistor from this pin to ground to set the operating frequency of the
boost controller.
10
11
12
13
14
REF
REFIN
COMP
SGND
AFB
Reference voltage. Use this pin to provide the REFIN voltage.
This pin sets the LED current feedback voltage. Connect to a resistor divider from the REF pin.
Output of the error amplifier. Connect to the compensation network.
Signal ground pin. Connect to ground.
Anode feedback pin. The boost controller voltage feedback during LED off time. Connect this pin to a
resistor divider from the output voltage.
15
16
17
SS/SH
DLY
Soft-start and sample-hold pin. Connect a capacitor from this pin to ground to set the soft-start time.
Fault delay pin. Connect a capacitor from this pin to ground to set the delay time for shutdown.
CFB
Cathode feedback pin. The boost controller voltage feedback. Connect through a diode to the bottom
cathode of each LED string.
18
19
SC
LED short circuit detection pin. Connect through a diode to the bottom cathode of each string.
LEDOFF
A dual function pin. The LEDOFF signal controls external drivers during PWM dimming. Or connect to
ground to enable automatic fault restart.
20
21
22
23
24
25
26
27
SNS3
NDRV3
SNS2
NDRV2
SNS1
NDRV1
THM
Current feedback for channel 3. Connect to the top of the channel 3 current sense resistor.
Base drive for the channel 3 current regulator. Connect to the NPN base or NFET gate.
Current feedback for channel 2.
Base drive for the channel 2 current regulator.
Current feedback for channel 1.
Base drive for the channel 1 current regulator.
LED thermal monitor input pin. When pulled below 1.2V, device enters standby mode.
DIM
PWM dimming input pin. Accepts a digital PWM or analog voltage level input to control LED current duty
cycle.
28
EN
Enable pin. Connect to VIN through a resistor divider to set an external UVLO threshold. Pull low to
shutdown.
EP
Exposed pad. Connect to SGND.
3
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CS
VCC
-0.3V to 7V
-0.3V to 7V
-65°C to +150°C
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
Soldering Dwell Time, Temp.
20sec, 240°C
75sec, 219°C
ꢀꢀInfrared
ꢀꢀVapor Phase
ESD Rating (Note 2)
Human Body Model
Voltages from the indicated
pins to SGND:
VIN
EN
DIM
MODE/F
REFIN
THM
DLY
SNSx
NDRVx
CFB
-0.3V to 37V
-0.3V to 10V
-0.3V to 7V
-0.3V to 7V
-0.3V to 7V
-0.3V to 7V
-0.3V to 7V
-0.3V to 7V
-0.3V to 7V
-0.3V to 7V
-0.3V to 40V
-0.3V to 7V
2 kV
Operating Ratings (Note 1)
VIN
4.5V to 36V
-40°C to +125°C
Junction Temp. Range
Thermal Resistance (θJA
(Note 3)
TSSOP-28 (0.5W)
Power Dissipation (Note 4)
TSSOP-28
)
32°C/W
3.1W
SC
AFB
Electrical Characteristics Specifications in standard type are for TJ = 25°C only, and limits in boldface type
apply over the junction temperature (TJ) range of -40°C to +125°C. Unless otherwise stated, VIN = 12V. Minimum and Maximum
limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ
= 25°C, and are provided for reference purposes only. (Note 5)
Symbol
System
Parameter
Conditions
Min
Typ
Max Units
IQ
Operating VIN Current (Note 6)
Standby mode VIN current
Shutdown mode VIN Current
VCC voltage
DIM = 5V
4.0
3.7
15
4.85
mA
mA
uA
V
IQ_SB
EN = 1V
IQ_SD
VCC
EN = 0V, Vin = 36V
Iload = 25 mA, Vin = 5.5 to 36V
23
4.80
5
5.24
VCCILIM
UVLO
VCC current limit
72
mA
V
UVLO threshold
VIN rising, measured at VCC
4.36
0.28
0.75
4.50
hysteresis
V
VEN_ST
VEN
Enable pin Standby threshold
Enable pin On threshold
hysteresis
EN rising
EN rising
V
1.185 1.230 1.275
V
115
165
mV
Linear Current Controller
VREF Reference Voltage
IREFIN
IREF < 300 µA
2.45
2.5
14
2.55
80
V
nA
REFIN input bias current
Line regulation
REFIN = 300 mV
5.5V < VIN < 36V
0.0001
3.7
6
%/V
V
ΔVREF / ΔVIN
VNDRV
NDRVx drive voltage capability
NDRVx drive sink current
NDRVx drive source current
SNSx input bias current
SNSx amp offset voltage
SNSx amp offset voltage
INDRVx = 5 mA
INDRV_SK
INDRV_SC
ISNS
NDRVX = 0.9V
4
8
mA
mA
µA
NDRVX = 0.9V
10
15
20
30
+5
+3
5.5
SNSx = 300 mV
20
VOS
REFIN = 300 mV (LM3431)
REFIN = 300 mV (LM3431A)
REFIN = 300 mV, 25°C (LM3431)
-5
-3
mV
mV
mV
VOS
VOS_DELTA
Ch. To Ch. offset voltage mismatch
(Note 7)
VOS_DELTA
VOS_DELTA
VOS_DELTA
Ch. To Ch. offset voltage mismatch
(Note 7)
REFIN = 300 mV, -40°C to +125°C
(LM3431)
6
3.5
4
mV
mV
mV
Ch. To Ch. offset voltage mismatch
(Note 7)
REFIN = 300 mV, 25°C (LM3431A)
Ch. To Ch. offset voltage mismatch
(Note 7)
REFIN = 300 mV, -40°C to +125°C
(LM3431A)
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Symbol
bw
Parameter
Conditions
At unity gain
DIM low
Min
Typ
2
Max Units
SNSx amp bandwidth
LEDOFF voltage
DIM threshold
hysteresis
MHz
V
VLEDOFF
VDIM
5
MODE/F > 4V
1.9
0.8
0.4
2.3
V
V
TDIM
Minimum internal DIM pulse width
(Note 8)
µs
DIMDLY_R
DIMDLY_F
THMODE/F
IMODE/F
DIM to NDRV delay time
DIM to NDRV delay time
MODE/F threshold
DIM rising
100
90
ns
ns
V
DIM falling
For Digital Dimming control
3.8
40
MODE/F source/sink current
MODE/F minimum voltage
MODE/F peak voltage
uA
V
VMODE_L
VMODE_H
Protection
Analog dimming mode
Analog dimming mode
0.37
2.5
V
VSC_SHORT
VSC_OPEN
IDLY_SC
IDLY_SK
VDLY
SC high threshold
LED short circuit fault, SC rising
LED open circuit fault, SC rising
DLY = 1.0V
5.7
3.16
39
6
6.2
3.87
73
V
V
SC open clamp voltage
DLY source current
3.50
57
µA
µA
V
DLY sink current
DLY = 1.0V
1.8
2.8
350
1.6
1.23
9.6
40
DLY threshold voltage
DLY reset threshold voltage
DLY blank time
DLY rising
2.40
1.19
3.16
1.27
VDLY_reset
TDLY_BLK
VTHM
DLY falling
mV
µs
V
DIM rising
THM threshold
ITHM
THM hysteresis current
ILIM max source current
AFB overvoltage threshold
AFB undervoltage threshold
Thermal shutdown threshold
THM = 1V
µA
µA
V
IILIM
COMP = 2.0V
31
46
VAFB_max
VAFB_UVP
TSD
1.87
0.73
2.0
0.85
160
2.22
0.98
AFB falling
V
°C
Boost controller
VCFB
CFB voltage
DIM high
DIM high
1.60
35
1.71
50
1.82
65
V
µA
ICFB
CFB source current
CFB temperature coefficient
CFB Line regulation
SS/SH source current
SS/SH voltage
CFBTC
-2.6
0.001
19
mV/°C
%/V
µA
5.5V < VIN < 36V
At EN going high
At end of soft-start cycle
RRT = 34.8 kΩ
ΔVCFB / ΔVIN
ISS/SH
13
24
VSS_END
VRT
1.80
1.85
1.22
700
200
1.90
V
RT voltage
V
FSW
Switching Frequency
Minimum Switching Frequency
Maximum Switching Frequency
651
180
900
749
220
kHz
RRT = 34.8 kΩ
RRT = 130 kΩ
1000 1100
RRT = 22.6 kΩ
Ton_min
DMAX
Minimum on time
170
85
230
ns
%
Maximum duty cycle
80
ILIMgm
Vslope
ICOMP_SC
ICOMP_SK
EAgm
ILIM amplifier transconductance
Slope compensation
COMP to ILIM gain
85
umho
mV
Peak voltage per cycle
75
COMP source current
COMP sink current
VCOMP = 1.2V, AFB = 0.5V
VCOMP =1.2V, AFB = 1.5V
CFB to COMP gain, DIM high
Source Current = 200 mA, VIN = 5.5V
Sink Current = 200 mA
155
150
230
6.4
2.2
0.35
0.70
µA
µA
Error amplifier transconductance
Gate Drive On Resistance
umho
RLG
Ω
Ω
A
A
ILG
Driver Output Current
Source, LG = 2.5V, VIN = 5.5V
Sink, LG = 2.5V
5
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Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 3: The Thermal Resistance specifications are based on a JEDEC standard 4-layer pcb. θJA will vary with board size and copper area.
Note 4: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal resistance, θJA
and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX – TA)/θJA. The
maximum power dissipation is determined using TA = 25°C, and TJ_MAX = 125°C.
,
Note 5: All room temperature limits are 100% production tested. All limits at temperature extremes are guaranteed through correlation using standard Statistical
Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Note 6: IQ specifies the current into the VIN pin and applies to non-switching operation.
Note 7: VOS_DELTA specifies the maximum absolute difference between the offset of any pair of SNS amplifiers.
Note 8: The minimum DIM pulse width is an internal signal. Any pulse width may be applied to the DIM pin or generated via analog dimming mode. A pulse width
less than 0.4 µs will be internally extended to 0.4 µs.
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Typical Performance Characteristics Unless otherwise specified the following conditions apply: VIN
=
12V, TJ = 25°C.
VREF vs. Temperature
CFB Voltage vs. Temperature
30041104
30041105
SNS 1, 2, 3 VOS vs Temperature (LM3431 or LM3431A)
Delta VOS Max vs Temperature (LM3431 or LM3431A)
30041107
30041106
IQ_SB vs Temperature
IQ_SD vs Temperature
30041108
30041109
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Normalized Switching Frequency
vs. Temperature (700 kHz)
Efficiency vs. Input Voltage
LED Current = 140 mA x 3, LED Vf = 25V
30041110
30041111
Line Transient Response
Dimming Transient Response
30041112
30041113
LED Ripple Current
NDRV Waveforms
30041115
30041114
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Block Diagram
30041116
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30041117
FIGURE 1. Typical Application Schematic
Operation Description
The LM3431 combines a boost controller and 3 constant cur-
rent regulator controllers in one device. To simplify the de-
scription, these two blocks will be described separately as
Boost Controller and LED Current Regulator. All descriptions
and component numbers refer to the Figure 1 schematic. The
LED bottom cathode nodes (VC1 – VC4) are referred to sim-
ply as the cathode.
Maximum duty cycle is limited to 85% typically.
As input voltage approaches the nominal output voltage, duty
cycle and switch on time are reduced. When the on time
reaches minimum, pulse skipping will occur. This increases
the output ripple voltage and can cause regulator saturation
and poor LED current regulation. If input voltage equals or
exceeds the set output voltage, switching will stop and the
output voltage will become unregulated. This will force an in-
crease in the LED cathode voltage and NPN regulator power
dissipation. Although this condition can be tolerated, it is not
recommended.
Boost Controller
The LM3431 is a current-mode, PWM boost controller. Al-
though the LM3431 may be operated in either continuous or
discontinuous conduction mode, the following guidelines are
designed for continuous conduction operation. This mode of
operation gives lower output ripple and better LED current
regulation.
Therefore, input voltage should be restricted to keep on time
above the minimum (see Switching Frequency section) and
at least 1V below the set output voltage.
In continuous conduction mode (when the inductor current
never reaches zero), the boost regulator operates in two cy-
cles. In the first cycle of operation, the NFET is turned on and
current ramps up and is storing energy in the inductor. During
this cycle, diode D1 is reverse biased and load current is sup-
plied by the output capacitors - C8 and C9 in Figure 1.
ENABLE and UVLO
The EN pin is a dual function pin combining both enable and
programmable undervoltage lockout (UVLO). The shutdown
threshold is 0.75V. When EN is pulled below this threshold,
the LM3431 will shutdown and IQ will be reduced to 15 µA
typically. The typical EN pin UVLO threshold is 1.23V. When
the EN voltage is above this threshold, the LM3431 will begin
softstart. Below the UVLO threshold, the LM3431 will remain
in standby mode. A resistor divider, shown as R1 and R2 in
Figure 1, can be used to program the UVLO threshold at the
EN pin. This feature is used to shutdown the IC at an input
voltage higher than the internal VCC UVLO threshold of 4.4V.
The EN UVLO should be set just below the minimum input
voltage for the application.
In the second cycle, the NFET is off and the diode is forward
biased. Inductor current is transferred to the load and output
capacitor. The ratio of these two cycles determines the output
voltage and is expressed as D or D’:
where D is the duty cycle of the switch.
The internal UVLO is monitored at the VCC pin. When VCC
is below the threshold of 4.4V, the LM3431 is in standby mode
(See VCC section).
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SOFT-START
The SS/SH pin is a dual function softstart and sample/hold
pin. The SH function is described in sections below. When the
EN pin is pulled above the programmable UVLO threshold
and VCC rises above the internal UVLO threshold, the SS/SH
pin begins sourcing current. This charges the SS cap (C6)
and the SS pin voltage in turn controls the output voltage
ramp-up, sensed via the AFB pin. The softstart capacitor is
calculated as shown below, where 20 µA is the typical soft-
start source current:
The AFB resistors also set the output over-voltage (OVP)
threshold. The OVP threshold is monitored during both LED
on and LED off states and protects against any over voltage
condition, including all LEDs open (See Open LED
section).The OVP threshold at Vout can be calculated as fol-
lows:
Because OVP has a fixed 2.0V threshold sensed at AFB, a
larger value for R19 will increase the OVP threshold of the
output voltage. During an open LED fault, the output voltage
will increase by 2.6V typically (see LED Protection section).
Therefore, at least this much headroom above the nominal
output voltage is required to avoid a false OVP error. Note
that because of the high output voltage setting at the end of
softstart, a brief open LED error may occur during the short
time it takes for the cathode voltage to drop to its nominal
level. Figure 2 shows a typical startup waveform, where both
Vout and the SS/SH voltage reach their peak before the LED
current turns on. Once LED current starts, SS/SH and Vout
drop to the nominal operating point.
The LED current regulators are held off until softstart is com-
pleted. During softstart, current limit is active and the CFB pin
is monitored for a cathode short fault (See LED protection
section). When the SS/SH voltage reaches 1.85V, the current
regulators are activated, LED current begins flowing, and out-
put voltage control is transferred to the CFB pin. Typical
startup is shown below in Figure 2.
While the LEDs are on, the AFB voltage is sampled to the SS/
SH pin. During LED-off time, this SS/SH voltage is used as
the reference voltage to regulate the output. This allows the
output voltage to remain stable between on and off dimming
cycles, even though there may be wide variation in the LED
string forward voltage. The SS/SH pin has a maximum volt-
age of 1.9V. Therefore, the AFB voltage when the LEDs are
on must be below this limit for proper regulation. This will be
ensured by setting the AFB resistors as described above.
During LED-off cycles, there is minimal loading on the output,
which forces the boost controller into pulse skipping mode. In
this mode, switching is stopped completely, or for multiple cy-
cles until the AFB feedback voltage falls below the SS/SH
reference level.
30041121
FIGURE 2. Typical Startup Waveforms
(From power-on, DIM = high)
SWITCHING FREQUENCY
OUTPUT VOLTAGE, OVP, and SH
The switching frequency can be set between 200 kHz and 1
MHz with a resistor from the RT pin to ground. The frequency
setting resistor (R6 in Figure 1) can be determined according
to the following empirically derived equation:
The LM3431 boost controls the LED cathode voltage in order
to drive the LED strings with sufficient headroom at optimum
efficiency. When the LED strings are on, voltage is regulated
to 1.7V (typical) at the CFB pin, which is one diode Vf above
the LED cathode voltage. Therefore, when the LED strings
are on, the output voltage (LED anodes, shown as VA in Fig-
ure 1) will vary according to the Vf of the LED string, while the
LED cathode voltage will be regulated via the CFB pin.
-1.06
RT = 35403 x fSW
Where the fSW is in kHz and the RT result is in kohm.
The AFB pin is used to regulate the output voltage when the
LED strings are off, which is during startup and dimming off
cycles. During LED-off times, the cathode voltage is not reg-
ulated.
AFB should set the initial output voltage to at least 1.0V (CFB
voltage minus one diode drop) above the maximum LED
string forward voltage. This ensures that there is enough
headroom to drive the LED strings at startup and keeps the
SS/SH voltage below its maximum. The AFB pin voltage at
the end of softstart is 1.85V typically, which determines the
ratio of the feedback resistors according to the following equa-
tion:
11
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Where IOUT is the sum of all LED string currents at 100% dim-
ming. IL(AVE) will be highest at the minimum input voltage.
Then determine the minimum L based on ΔiL with the follow-
ing equation:
A good starting point is to set ΔiL to 150% of the minimum IL
and calculate using that value. The maximum recom-
(AVE)
mended ΔiL is 200% of IL(AVE) to maintain continuous current
in normal operation. In general a smaller inductor (higher rip-
ple current) will give a better dimming response due to the
higher dI/dt. This is shown graphically below.
30041124
FIGURE 3. Switching Frequency vs RT
For a given application, the maximum switching frequency is
limited by the minimum on time. When the LM3431 reaches
its minimum on-time, pulse skipping will occur and output rip-
ple will increase. To avoid this, set the operating frequency
below the following maximum setting:
INDUCTOR SELECTION
Figure 4 shows how the inductor current, IL, varies during a
switching cycle.
30041129
FIGURE 5. Inductor Current During Dimming
The resulting peak to peak inductor current is:
And the resulting peak inductor current is:
Peak inductor current will occur at minimum VIN.
30041126
The inductor must be rated to handle both the average current
and peak current, which is the same as the peak switch cur-
rent. As switching frequency increases, less inductance is
required. However, some minimum inductance value is re-
quired to ensure stability at duty cycles greater than 50%. The
minimum inductance required for stability can be calculated
as:
FIGURE 4. Inductor Current, SW Voltage, and VOUT
The important quantities in determining a proper inductance
value are IL(AVE) (the average inductor current) and ΔiL (the
peak to peak inductor current ripple). If ΔiL is larger than 2 x
IL(AVE), the inductor current will drop to zero for a portion of the
cycle and the converter will operate in discontinuous conduc-
tion mode. If ΔiL is smaller than 2 x IL, the inductor current will
stay above zero and the converter will operate in continuous
conduction mode.
To determine the minimum L, first calculate the IL(AVE) at both
minimum and maximum input voltage:
Where R3 is the sense resistor determined in the next section.
Although the inductor must be large enough to meet both the
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stability and the ΔiL requirements, a value close to minimum
LO threshold and allow operation at input voltages as low as
4.5V. It may also be necessary to add additional VIN and VCC
capacitance for low VIN operation.
will typically give the best performance.
CURRENT SENSING
DIODE SELECTION
Switch current is sensed via the sense resistor, R3, while the
switch is on and the inductor is charging. The sensed current
is used to control switching and to monitor current limit. To
optimize the control signal, a typical sense voltage between
50mV and 200mV is recommended. The sense resistor can
therefore be calculated by the following equation:
The average current through D1 is the average load current
(total LED current), and the peak current through the diode is
the peak inductor current. Therefore, the diode should be rat-
ed to handle more than the peak inductor current which was
calculated earlier. The diode must also be capable of handling
the peak reverse voltage, which is equal to the output voltage
(LED Anode voltage). To improve efficiency, a low Vf Schottky
diode is recommended. Diode power loss is calculated as:
PDIODE = Vf x IOUT
Since IL(AVE) will vary with input voltage, R3 should be deter-
mined based on the full input voltage range, although the
resulting value may extend somewhat outside the recom-
mended range.
NFET SELECTION
The drive pin of the LM3431 boost switcher, LG, must be
connected to the gate of an external NFET. The NFET drain
is connected to the inductor and the source is connected to
the sense resistor. The LG pin will drive the gate at 5V typi-
cally.
CURRENT LIMIT
Current limit occurs when the voltage across the sense re-
sistor (measured at the CS pin) equals the current limit thresh-
old voltage. The current limit threshold is set by R4. This value
can be calculated as follows:
The critical parameters for selection of a MOSFET are:
1. Maximum drain current rating, ID(MAX)
2. Maximum drain to source voltage, VDS(MAX)
3. On-resistance, RDS(ON)
4. Total gate charge, Qg
In the on-state, the switch current is equal to the inductor cur-
rent. Therefore, the maximum drain current, ID, must be rated
higher than the current limit setting. The average switch cur-
rent (ID(AVE)) is given in the equation below:
Where 40 µA is the typical ILIM source current in current limit
and ILlim is the peak (not average) inductor current which
triggers current limit.
ID(AVE) = IL(AVE) x D
To avoid false triggering, current limit should be set safely
above the peak inductor current level. However, the current
limit resistor also has some effect on the control loop as seen
in the block diagram. For this reason, R4 should not be set
much higher than necessary. When current limit is activated,
the NFET will be turned off immediately until the next cycle.
Current limit will typically result in a drop in output and cathode
voltage. This will cause the COMP pin voltage to increase to
maximum, which will trigger a fault and start the DLY pin
source current (see LED Protection section). The LM3431 will
continue to operate in current limit with reduced on-time until
the DLY pin has reached its threshold. However, the current
limit cannot reduce the on-time below the minimum specifi-
cation.
The off-state voltage of the NFET is approximately equal to
the output voltage plus the diode Vf. Therefore, VDS(MAX) of
the NFET must be rated higher than the maximum output
voltage. The power losses in the NFET can be separated into
conduction losses and switching losses. The conduction loss,
Pcond, is the I2R loss across the NFET. The maximum con-
duction loss is given by:
2
PCOND = RDS(ON) x DMAX x IL(AVE)
where DMAX is the maximum duty cycle for the given applica-
tion and RDS(ON) is the on resistance at high temperature. The
switching losses can be roughly calculated by the following
equation:
In a boost switcher, there is a direct current path between
input and output. Therefore, although the LM3431 will shut-
down in a shorted output condition, there are no means to limit
the current flowing from input to output.
Where tON and tOFF are the NFET turn-on and turn-off times.
Note that if the maximum duty cycle of 85% (typical) is
reached, the LM3431 will behave as though current limit has
occurred.
Power is also consumed in the LM3431 in the form of gate
charge losses, Pg. These losses can be calculated using the
formula:
VCC
Pg = fSW x Qg x VIN
The VCC pin is the output of the internal voltage regulator. It
must be bypassed to PGND with a minimum 4.7 µF ceramic
capacitor. Although VCC is capable of supplying up to 72 mA,
external loads will increase the power dissipation and tem-
perature rise within the LM3431. See the TSD section for
more detail. Above 72 mA, the VCC voltage will drop due to
current limit. Since the UVLO threshold is monitored at this
pin, UVLO may be enabled by a VCC over current event.
where Qg is the NFET total gate charge. Pg adds to the total
power dissipation of the LM3431 (See TSD section).
Fast switching FETs can cause noise spikes at the SW node
which may affect performance. To reduce these spikes a drive
resistor up to 10Ω can be placed between LG and the NFET
gate.
For input voltages between 4.5V and 5.5V, connect VCC to
VIN through a 4.7Ω resistor. This will hold VCC above the UV-
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INPUT CAPACITOR SELECTION
Because the inductor is at the input of a boost converter, the
input current waveform is continuous and triangular. The in-
ductor ensures that the input capacitor sees relatively low
ripple currents. The rms current in the input capacitor is given
by:
The input capacitor must be capable of handling this rms cur-
rent. Input ripple voltage increases with increasing ESR as
well as decreasing input capacitance. A typical value of 10 µF
will work well for most applications. For low input voltages,
additional input capacitance may be required to prevent trip-
ping the UVLO. Additionally, a ceramic capacitor of 1 µF or
larger should be placed close to the VIN pin to prevent noise
from interfering with normal device operation.
Where RL is the load resistance corresponding to LED cur-
rent, and Kf is calculated as shown:
OUTPUT CAPACITOR SELECTION
The output capacitor in a boost converter provides all the out-
put current when the switch is on and the inductor is charging.
As a result, the output capacitor sees relatively large ripple
currents. The output capacitor must be capable of handling
more than the rms current, which can be estimated as:
Since the control-to-output response will shift with input volt-
age, the compensation should be calculated at both the min-
imum and maximum input voltage.
The zero created by the ESR of the output capacitor, fz1, is
generally at a very high frequency if the ESR is small. If low
ESR capacitors are used fz1 can be neglected and if high ESR
capacitors are used, CC2 can be added (see below).
Additionally, the ESR of the output capacitor affects the output
ripple and has an effect on transient response during dim-
ming. For low output ripple voltage, low ESR ceramic capac-
itors are recommended. Although not a critical parameter,
excessive output ripple can affect LED current.
A current mode control boost regulator has an inherent right
half plane zero, RHPz. This has the effect of a zero in the gain
plot, causing a +20dB/decade increase, but has the effect of
a pole in the phase, subtracting 90° in the phase plot. This
can cause instability if the control loop is influenced by this
zero. To ensure the RHP zero does not cause instability, the
control loop must be designed to have a bandwidth of less
than one third the frequency of the RHP zero. The regulator
also has a double pole, fpn, at one half the switching frequen-
cy. The control loop bandwidth must be lower than 1/5 of fpn.
A typical control-to-output gain response is shown in Figure
6 below.
The output capacitance requirement is somewhat arbitrary
and depends mostly on dimming frequency. Although a min-
imum value of 4 µF is recommended, at lower dimming fre-
quencies, the longer LED-off times will typically require more
capacitance to reduce output voltage transients.
When ceramic capacitors are used, audible noise may be
generated during LED dimming. Audible noise increases with
the amplitude of output voltage transients. To minimize this
noise, use the smallest case sizes and if possible, use a larger
number of capacitors in parallel to reduce the case size of
each. Output transients are also minimized via the FF pin
(See Setting FF section). Setting the dimming frequency
above 18 kHz or below 500 Hz will also help eliminate the
audible effects of output voltage transients.
When selecting an output capacitor, always consider the ef-
fective capacitance at the output voltage, which can be less
than 50% of the capacitance specified at 0V. Use this effective
capacitance value for the compensation calculations below.
COMPENSATION
Once the output capacitor is selected, the control loop char-
acteristics and compensation can be determined. The COMP
pin is provided to ensure stable operation and optimum tran-
sient performance over a wide range of applications. The
following equations define the control-to-output or power
stage of the loop:
30041140
FIGURE 6. Typical Control-to-Output Bode Plot
Once the control-to-output response has been determined,
the compensation components are selected. A series combi-
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14
nation of Rc and Cc is recommended for the compensation
network, shown as R9 and C4 in the typical application circuit.
The series combination of Rc and Cc introduces a pole-zero
pair according to the following equations:
where RO is the output impedance of the error amplifier, ap-
proximately 500 kΩ. The initial value of RC is determined
based on the required crossover frequency from the following
equations using the maximum input voltage:
30041143
FIGURE 7. Typical Compensation and Total Loop Bode
Plots
When using an output capacitor with a high ESR value, an-
other pole, fpc2, may be introduced to cancel the zero created
by the ESR. This is accomplished by adding another capaci-
tor, CC2, shown as C13 in the Figure 1. The pole should be
placed at the same frequency as fz1. This pole can be calcu-
lated as:
Where B is the mid-frequency compensation gain (in v/v), R4
is the current limit setting resistor, Acm is the control-output
DC gain, and the gm values are given in the electrical char-
acteristic table. Fcross is the maximum allowable crossover
frequency, based on the calculated values of fpn and RHPz.
Any Rc value lower than the value calculated above can be
used and will ensure a low enough crossover frequency. Rc
should set the B value typically between 0.01v/v and 0.1v/v
(-20db to -40db). Larger values of RC will give a higher loop
bandwidth.
To ensure this equation is valid, and that CC2 can be used
without negatively impacting the effects of RC and CC, fpc2
must be at least 10 times greater than fzc.
LED Current Regulator
SETTING LED CURRENT
However, because the dynamic response of the LM3431 is
enhanced by the FF pin (See Setting FF section) the RC value
can be set conservatively. The typical range for RC is between
300ohm and 3 kΩ. Next, select a value for Cc to set the com-
pensation zero, fzc, to a frequency greater or equal to the
maximum calculated value of fp1 (fzc cancels the power pole,
fp1). Since an fzc value of up to a half decade above fp1 is
acceptable, choose a standard capacitor value smaller than
calculated. Confirm that fpc, the dominant low frequency pole
in the control loop, is less than 100 Hz and below fp1. The
typical range for CC is between 10 nF and 100 nF. The com-
pensation zero-pole pair is shown graphically below, along
with the total control loop, which is the sum of the compen-
sation and output-control response. Since the calculated
crossover frequency is an approximation, stability should al-
ways be verified on the bench.
LED current is independently regulated in each of 3 strings by
regulating the voltage at the SNS pins. Each SNS pin is con-
nected to a sense resistor, shown in the typical application
schematic as R10 - R13. The sense resistor value is calcu-
lated as follows:
Where ILED is the current in each LED string, REFIN is the
regulated voltage at the REFIN pin, and INDRV is the NPN
base drive current. If using NFETs, INDRV can be ignored. A
minimum REFIN voltage of 100 mV is required, and 200mV
to 300mV is recommended for most applications. The REFIN
voltage is set with a resistor divider connected to the REF pin,
shown as R7 and R8 in the typical application schematic. The
resistor values are calculated as follows:
The sum of R7 and R8 should be approximately 100k to avoid
excessive loading on the REF pin.
15
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NDRV
operate in analog mode, connect a capacitor from MODE/F
to ground, shown as C5 in the typical application (without the
pull-up resistor installed). The dimming frequency is set ac-
cording to the following equation:
The NDRV pins drive the base of the external NPN or N-
channel MOSFET current regulators. Each pin is capable of
driving up to 15 mA of base current typically. Therefore, NPN
devices with sufficient gain must be selected. The required
NDRV current can be calculated from the following equation,
where β is the NPN transistor gain.
In analog mode, the MODE/F pin will generate a triangle wave
with a peak of 2.5V and minimum of 0.37V. The DIM pin volt-
age is compared to the MODE/F voltage to create an internal
PWM dimming signal whose duty cycle is proportional to the
DIM voltage. When the DIM voltage is above 2.5V, the duty
cycle is 100%. Duty cycle will vary linearly with DIM voltage
as shown in Figure 8. Typical analog dimming waveforms are
shown below in Figure 9.
If NFETs are used, the NDRV current can be ignored. NPN
transistors should be selected based on speed and power
handling capability. A fast NPN with short rise time will give
the best dimming response. However, if the rise time is too
fast, some ringing may occur in the LED current. This ringing
can be improved with a resistor in series with the NDRV pins.
The NPNs must be able to handle a power equal to ILED x NPN
voltage. Note that the NPN voltage can be as high as approx-
imately 5.5V in a fault condition. The NDRV pins have a
limited slew rate capability which can increase the turn-on
delay time when driving NFETs. This delay increases the
minimum dimming on-time and can affect the dimming lin-
earity at high dimming frequencies. Low VGS threshold NFETs
are recommended to ensure that they will turn fully on within
the required time. At dimming frequencies above 10 kHz,
NPN transistors are recommended for the best performance.
CFB AND SC DIODES
The bottom of each LED string is connected to the CFB and
SC pins through diodes as shown in Figure 1. The CFB pin
receives voltage feedback from the lowest cathode voltage.
The other string cathode voltages will vary above the regu-
lated CFB voltage. The actual cathode voltage on these
strings will depend on the LED forward voltages. This ensures
that the lowest cathode voltage (highest Vf) will be regulated
with enough headroom for the NPN regulator. The SC pin
monitors for LED fault conditions and limits the maximum
cathode voltage (See LED Protection section). In this way,
each LED string’s cathode is maintained within a window be-
tween minimum headroom and fault condition.
30041149
FIGURE 8. Analog Mode Dimming Duty Cycle vs. DIM
voltage
Both the CFB and SC diodes must be rated to at least 100
µA, and the CFB diode should have a reverse voltage rating
higher than VOUT. With these requirements in mind, it is best
to use the smallest possible case size in order to minimize
diode capacitance which can slow the LED current rise and
fall times.
DIMMING
The LM3431 is compatible with both analog and digital LED
dimming signals. The MODE/F pin is used to select analog or
digital mode. When MODE/F is pulled above 3.8V, digital
mode is enabled and a PWM signal up to 25 kHz can be ap-
plied to the DIM pin. In this mode, the LED current regulators
will be active when DIM is above 2V (typical) and inactive
when DIM is pulled below 1.1V (typical). Although any pulse
width may be used at the DIM pin, 0.4 µs is the minimum LED
on time (in either digital or analog mode). This limits the min-
imum dimming duty cycle at high dimming frequencies. For
example, at 20 kHz, the dimming duty cycle is limited to 0.8%
minimum. At lower dimming frequencies, the dimming duty
cycle can be much lower and the minimum depends on the
application conditions including the FF setting (see Setting FF
section). In analog dimming mode, the MODE/F pin is used
to set the PWM dimming frequency, and duty cycle is con-
trolled by varying the analog voltage level at the DIM pin. To
30041150
FIGURE 9. Analog Dimming Mode Waveforms
In PWM dimming, the average LED current is equal to the set
LED current (ILED) multiplied by the dimming duty cycle. The
average LED current tracks the dimming ratio with exception-
al linearity. However, the accuracy of average LED current
depends somewhat on the rise and fall times of the external
current regulators. This becomes more apparent with short
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on-times. To ensure good linearity, select NPN regulators
with short and similar rise and fall times.
In practice the FF pin also has a small effect on the control
loop response. As a final step, switching stability at 100%
dimming duty should be re-verified once the Rff value has
been selected. At the optimal Rff setting, output voltage tran-
sients will be minimized and the cathode voltage will be stable
across the range of input voltage and dimming duty cycle.
SETTING FF
To minimize voltage transients during LED dimming, the out-
put voltage is regulated via the AFB pin during LED off times.
However, because the control loop has a limited response
time, voltage transients can never be completely eliminated.
If these transients are large enough, LED current will be af-
fected and ceramic output capacitors may generate audible
noise. The FF pin speeds up the loop response time, and thus
minimizes output voltage transients during dimming.
The ideal cathode response illustrated in Figure 10 may not
be achievable over the entire input voltage range. However,
LED current will not be affected as long as the cathode voltage
remains above the regulator saturation voltage and below the
open LED fault threshold (See Open LED section).
A wide input voltage range will cause a wider variation in the
feedforward effect, thus making duty cycles less than 1%
more difficult to achieve. For any given application there is a
minimum achievable dimming duty cycle. Below this duty cy-
cle, the cathode voltage will begin to drift higher, eventually
appearing as an open LED fault (See LED Protection section).
A resistor connected from FF to ground, Rff, sets the FF cur-
rent which is injected into the control loop at the rising and
falling edge of the dimming signal. In this way, the FF pin cre-
ates a correction signal before the control loop can respond.
A smaller FF resistor will generate a larger correction signal.
The minimum recommended Rff value is 10k.
During an LED open fault condition, cathode voltage over-
shoot will tend to increase. If Rff is not set appropriately, high
overshoots may be detected as an LED short fault and lead
to shutdown.
Since the amount of FF correction required for a given appli-
cation depends on many factors, it is best to determine a FF
resistor value through bench testing. Use the following pro-
cedure to determine an optimal Rff value:
LED PROTECTION
An Rff value of approximately 20k is a good starting point. A
20 kΩ potentiometer in series with a 10 kΩ resistor works well
for bench testing.
Fault Modes and Fault Delay
The LM3431 provides 3 types of protection against several
types of potential faults. The table below summarizes the fault
protections and groups the fault responses into three types
(the auto-restart option is described in the next section).
The dimming frequency must be selected before setting Rff.
Confirm that boost switching operation is stable at 100% dim-
ming duty cycle.
Adjust Rff until the COMP pin voltage is between 0.8V and
0.9V. Next, monitor the cathode voltage response at a low
dimming duty cycle while adjusting Rff until the overshoot and
undershoot is minimal or there is a slight overshoot.
Fault Mode Summary
fault
mechanism action
response
type
1 LED
open
SC > 3.1V
DLY
charges
continue to
regulate
Check the cathode voltage response at the lowest input volt-
age and lowest dimming duty cycle and adjust Rff if neces-
sary. This is typically the worst case condition.
1
1 LED
short
SC > 3.1V
DLY
charges
continue to
regulate
The curves in Figure 10 below show the variation in cathode
voltage with different Rff settings. Notice that at the ideal set-
ting, both the cathode voltage and COMP voltage are flat. For
clarity, the 3 cathode voltage curves in this figure have been
offset; all FF settings will result in the cathode voltage settling
at 1.2V typically.
All LEDs AFB > 2.0V
open
DLY
charges
Shutdown or
auto-restart
Output
over-
voltage
AFB > 2.0V
DLY
charges
Shutdown or
auto-restart
multiple
LED short
SC > 6.0V
DLY
charges
Shutdown or
auto-restart
2
Multiple AFB < 0.85V
LED
short,
DLY
charges
Shutdown or
auto-restart
VIN<6V
Cathode CFB low at
DLY
charges
Shutdown or
auto-restart
short
startup
Current
limit
COMP at
max
DLY
charges
Shutdown or
auto-restart
UVLO
VCC or EN No DLY
stand by
stand by
stand by
low
flag
TSD
IC over
temperature
No DLY
flag
3
30041151
THM
THM < 1.2V No DLY
flag
FIGURE 10. FF Setting Example
Once an Rff value has been set, check the cathode voltage
over the input voltage range and dimming duty range. Some
further adjustment may be necessary.
When Type 1 or Type 2 faults occur, the DLY pin begins
sourcing current (57 µA typical). A capacitor connected from
DLY to ground (C7) sets the DLY voltage ramp and shutdown
delay time. For a Type 1 fault, the LM3431 will continue to
17
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regulate, although the DLY pin remains high. In this condition,
the DLY pin will charge to a maximum of 3.6V (typical).
will not reach 3.6V, but will start discharging from the shut
down threshold of 2.8V. When the DLY pin voltage falls to 350
mV (typical) the LM3431 will restart from softstart mode. In
this way, the DLY capacitor controls the restart delay time. If
the LEDOFF pin is used to control additional LED strings (see
LEDOFF section), then the automatic restart feature cannot
be enabled.
In case of a Type 2 fault, when the DLY voltage reaches 2.8V
(typical), the LM3431 will shut down and the DLY pin will re-
main at 3.6V.
For evaluation and debugging purposes, Type 2 shutdown
can be disabled by grounding the DLY pin. It is not recom-
mended to leave the DLY pin open.
In the case of an output over-voltage fault (all LEDs open),
DLY will not discharge until the AFB voltage falls below the
OVP threshold. Figure 12 below shows an OVP fault with au-
to-restart activated. The output voltage increases when all
LEDs are opened, causing DLY to charge. DLY remains at
2.8V until Vout falls below the OVP threshold. When DLY dis-
charges to 350 mV, softstart begins. In auto-restart mode, the
LM3431 will re-start continually until the fault is removed. In
this example, the fault is removed and normal operation con-
tinues after one attempted re-start.
For any fault other than a cathode short, the DLY pin will dis-
charge (sinking 1.8 µA) when the fault is removed before
shutdown occurs. Since most fault conditions can only be
sensed during the LED-on dimming period, the DLY pin will
not charge during LED-off times. When the LEDs are off, DLY
is in a high impedance state and its voltage will remain con-
stant. If a fault is removed during the LED-off period, DLY will
begin discharging at the next LED-on cycle. If the fault is not
removed, DLY will continue charging at the next LED-on cy-
cle. Therefore, the DLY charging time is controlled by both the
DLY capacitor and the dimming duty cycle. The time for the
DLY pin to charge to the shutdown threshold can be calcu-
lated as shown:
Where DDIM is the dimming duty cycle. Figure 11 below shows
the DLY pin charging during dimming due to a Type 1 fault:
30041154
FIGURE 12. OVP and Auto-Restart
Open LED
If any LED string fails open, the boost regulator will sense a
low voltage at the CFB pin. This will cause the output voltage
to increase, causing the other LED string cathode voltages to
also increase. When the SC pin voltage rises to 3.1V, a Type
1 fault will be triggered and the DLY pin will begin sourcing
current. In this mode, the SC voltage will be clamped at 3.5V
(typical) and the regulators will continue to operate. At this
higher cathode voltage, power dissipation will increase in the
external NPN regulators. Power dissipation will also increase
in the LM3431 since any open string will cause the NDRV pin
to source its maximum current. A one LED open fault condi-
tion is shown in Figure 11 above. The open LED causes the
cathode voltage to increase, and DLY charges during each
LED on cycle while current continues to be regulated in the
other LED strings.
30041153
FIGURE 11. DLY Charging, 1 LED Open Fault
When the LED string turns on, there is a 1.6 µs typical blank-
ing time for fault detection. This ensures that the LED cathode
voltage will reach its regulation point and faults will not be
falsely triggered. However, faults can not be detected during
short dimming cycles of less than 1.6 µs.
If all LED strings fail open, the same action will cause the out-
put voltage to increase. However, in this case, SC will be held
low and cannot sense the failure. Instead, this failure mode is
sensed by AFB. When AFB reaches its over-voltage thresh-
old of 2.0V (typical), a Type 2 fault will be triggered, the DLY
pin will begin sourcing current, and the LM3431 will shut
down.
When a Type 3 fault occurs, DLY does not charge. The
LM3431 will enter standby mode and restart from softstart
when the fault condition is removed.
Fault Shutdown and Automatic Restart
In normal operation, the LM3431 must be powered off or put
into standby via the EN pin to restart after a fault shutdown.
However, the LEDOFF pin can be connected to GND to en-
able the automatic restart feature. During startup, the LED-
OFF voltage is monitored and if grounded, auto-restart mode
is enabled.
Unlike the SC and CFB fault detection, the AFB pin is always
monitored. Therefore, DLY charging time will not be affected
by the dimming duty cycle and any over-voltage condition will
cause DLY to charge.
In auto-restart mode, the DLY pin will be discharged by a 1.8
µA sink current after a Type 2 shutdown. In this mode, DLY
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18
Shorted LED
and provides over-temperature protection for both the IC and
LEDs.
If an LED fails short circuit, the SC voltage will increase. When
SC reaches 3.1V, the same Type 1 fault as an open LED will
be triggered. Current in the affected string will continue to be
regulated, with the cathode clamped at one diode Vf above
3.5V. As in the case of 1 LED open, the power dissipation will
increase in the external NPN regulator of the shorted string.
THM
The THM pin is designed to monitor for over-temperature
conditions at the LED array. This is done with a negative TC
thermistor mounted at the LED panel. The THM circuit is a
resistor divider from a reference voltage to ground, shown in
Figure 14 as R17 and Rth. As the thermistor temperature in-
creases, the THM pin voltage will decrease. When THM drops
to 1.23V (typical), a Type 3 fault is triggered and the LM3431
will enter standby until the thermistor temperature decreases
and THM voltage increases. Thermistors are typically speci-
fied by their resistance at 25°C, and by their beta constant
which describes the temperature coefficient. The resistance
value at the desired shutdown temperature can be calculated
from the beta constant or found in the thermistor datasheet
table. Once the shutdown temperature resistance is known,
the R17 value can be calculated as shown below.
However, if enough LEDs or an entire string are shorted, the
SC pin will rise to the short circuit threshold of 6.0V. This will
cause a Type 2 fault, and the LM3431 will shut down when
the DLY threshold is reached.
When an LED string is shorted, the LM3431 will attempt to
reduce the SC voltage to 3.5V. As a result, switching will stop,
and the cathode voltage will be brought to the minimum level,
which is Vin. If Vin is less than approximately 6V and the DLY
time is long enough, SC will fall below the 6V short circuit fault
threshold. In this case, the shorted string fault will be detected
as an AFB under-voltage (UVP) fault.
When AFB falls below 0.85V (typical) a Type 2 fault will be
triggered. As is the case with OVP detection, the AFB UVP
threshold is monitored during both LED on and LED off cycles.
A UVP fault will cause DLY to charge, unaffected by the dim-
ming duty cycle. Figure 13 below shows the sudden cathode
voltage increase due to an LED string short. DLY begins
charging and charges continuously when an AFB under-volt-
age is detected, eventually causing a shutdown.
where Rth@T is the thermistor resistance at the desired shut-
down temperature. Although VCC is shown in the typical
application schematic, any regulated voltage source can be
used in its place, including VREF
.
In shutdown, THM sinks 10 µA to create some hysteresis. An
R17 value of at least 20 kΩ is recommended to create suffi-
cient hysteresis. Larger values of R17 (and Rth) will generate
larger hysteresis.
If more hysteresis is required, a resistor can be added in se-
ries with THM as shown below:
30041155
FIGURE 13. LED String Short Fault and UVP Detection
30041157
Shorted Cathode
At the end of softstart, the CFB voltage is monitored. In normal
startup, the LED strings are off and CFB voltage increases
with the output voltage. If the CFB voltage stays below ap-
proximately 1.9V, a cathode short to ground condition is
detected and a Type 2 fault is triggered. At the end of soft-
start, the DLY pin will begin sourcing current and it will con-
tinue sourcing until the shutdown threshold is reached, even
if the short condition is removed.
FIGURE 14. THM Circuit with Hysteresis
The THM hysteresis can be determined by calculating the
restart threshold as shown below. If RHYS is not installed, cal-
culate Rth@restart using an RHYS value of 0Ω.
When a cathode short occurs, the LEDs in the affected string
will be driven on during the soft-start and DLY periods. There-
fore, the DLY and soft-start time should be set short enough
for the LED string to withstand the burst of unregulated cur-
rent.
Where 10 µA is the THM sink current, and Rth@restart is the
thermistor resistance at the restart temperature. Refer to the
manufacturer datasheet to find the restart temperature at the
calculated resistance or use the beta constant to calculate the
restart temperature.
THERMAL CONSIDERATIONS
To optimize performance under all conditions, the LM3431
controls the temperature coefficients of critical parameters
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During startup (and re-start), the THM monitor is active.
Therefore, the thermistor temperature must be below the
restart threshold for the LM3431 to startup.
the external driver. While the LED strings are on, the LEDOFF
signal is low, allowing normal regulation. If LEDOFF is used
to add additional channels, it cannot be used to enable auto-
restart mode.
TSD
All additional channels must also be connected through
diodes to the SC and CFB pins as shown in the typical appli-
cation schematic. The op-amp used to drive the additional
channel current regulator must be fast enough to drive the
regulator fully on within the DLY blanking time. A slew rate of
5V/µsec is typically sufficient. Also, the op-amp output must
be capable of completely turning off the NPN regulator, which
requires a drive voltage no greater than the REFIN voltage.
A rail-to-rail type op-amp is recommended.
If the LM3431 internal junction temperature increases above
160°C TSD is activated. This is a Type 3 fault condition. De-
vice temperature rise is determined by internal power dissi-
pation primarily in the LG and NDRVx drivers. The power
dissipation can be estimated as follows:
PD = PIQ + PNDRV + PVCC + PG
ꢀ
PIQ = VIN x IQ
Finally, the R14 resistor should be large enough to limit VCC
current during the LED-off cycle. A value of at least 1k is rec-
ommended. Any additional channels will have a longer turn-
on delay time than channels 1-3. An additional delay time of
250 ns is typical. The added delay can affect dimming linearity
at on times less than 1 µs.
Where IQ is 4.0 mA typically.
PNDRV = (VIN - REFIN - Vbe) x INDRV x DDIM x #Strings
Where REFIN+Vbe is the NDRV voltage and INDRV was cal-
culated previously in the NDRV section. For the case of open
LEDs, INDRV on the open string will be at the maximum of 15
mA. The LM3431 power dissipation will be highest in open
LED conditions at 100% dimming duty. If NFETs are used for
regulation, PNDRV will be a function of dimming frequency and
can be calculated as:
LED CURRENT ACCURACY
LED string current accuracy is affected by factors both inter-
nal and external to the LM3431. For any single string the
maximum deviation from ideal is simply the sum of the sense
resistor, offset error, REF voltage, REFIN resistor divider ac-
curacy, and bipolar gain variation:
PNDRV_FET = f dim x Qg x VIN
ꢀ
PVCC = (VIN - VCC) x IVCC
Where IVCC is any current being drawn from the VCC pin, such
as external op-amp power, or THM voltage divider.
The LG power dissipation, PG is given in the NFET section.
Temperature rise can then be calculated as:
Where AR10 is the sense resistor % accuracy, 2% is the REF
voltage accuracy, AR7 and AR8 are the REFIN setting resistors
% accuracy, 5 mV is the maximum SNS amp offset voltage
(use 3 mV for LM3431A), β is the gain of NPN transistor, and
Δβ is the specified range of gain in the NPN. The string-to-
string accuracy is the maximum difference in current between
any two strings. It is best calculated using the RSS method:
TRISE = PD x θJA
Where θJA is typically 32°C/W and varies with pcb copper area
(Refer to the PCB Layout section).
Although the TSD threshold is 160°C, the LM3431 may not
operate within specification at temperatures above the maxi-
mum rating of 125°C. Power dissipation should be limited to
ensure that device temperature stays within this limit.
TEMPERATURE COEFFICIENTS
Where 6 mV is the maximum SNS amp delta offset voltage
(VOS_DELTA over temperature, use 4 mV for LM3431A) and we
are assuming the sense resistors have the same accuracy
rating. If FETs are used, the β term can be ignored in both
equations. The LED current in each string will be within
±Acc_single% of the set current. And the difference between
any two strings will be within ±Acc_s-s% of each other.
Several device specifications are designed to vary with tem-
perature. To maintain optimum headroom control and mini-
mum NPN power dissipation, CFB regulation has a tempco
of -2.6 mV/°C. This is matched to the typical tempco of the
small signal diodes used for the cathode feedback connec-
tion. Although the CFB voltage will vary with temperature, the
cathode voltage will remain stable. The SS/SH pin rises to
1.85V typically during soft start. This voltage has a tempco of
approximately -2.2 mV/°C, which is designed to follow the
tempco of the LED strings. At then end of soft start, the anode
voltage will be greater than the maximum LED forward volt-
age, regardless of operating temperature. To avoid false
errors, the AFB overvoltage threshold has a tempco of -1.4
mV/°C. Of course, these temperature monitoring features are
most effective with the LM3431 mounted within the same am-
bient temperature as the LEDs.
PCB LAYOUT
Good PCB layout is critical in all switching regulator designs.
A poor layout can cause EMI problems, excess switching
noise, and improper device operation. The following key
points should be followed to ensure a quality layout.
Traces carrying large AC currents should be as wide and
short as possible to minimize trace inductance and associat-
ed noise spikes.
These areas, shown hatched in Figure 15, are:
LEDOFF: ADDING ADDITIONAL CHANNELS
- The connection between the output capacitor and diode
Although the LM3431 has three internal current controllers,
more channels can easily be added. A fourth LED string is
shown in Figure 1 connected to VC4.
- The PGND area between the output capacitor, R3 sense
resistor, and bulk input capacitor
- The switch node
For additional channels, the sense resistor should be the
same value as the main three channels. During startup and
dimming off time, LEDOFF rises to 5V, which quickly turns off
The current sensing circuitry in current mode controllers can
be easily affected by switching noise. Although the LM3431
imposes 170ns of blanking time at the beginning of every cy-
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20
cle to ignore this noise, some may remain after the blanking
time. Following the important guidelines below will help min-
imize switching noise and its effect on current sensing.
sensing. This area, shown as LGND in Figure 15, should be
somewhat separated from SGND and must provide enough
copper area for the total LED current.
As shown in Figure 15, ground the output capacitor as close
as possible to the bottom of the sense resistor. This connec-
tion should be somewhat isolated from the rest of the PGND
plane (place no ground plane vias in this area). The VOUT side
of the output capacitor should be placed close to the diode.
If driving more than 3 channels, the layout of the additional
channels should be within a minimal area with short trace
lengths. This will help to reduce ringing and delay times. Con-
nections to the LED array should be as short as possible. Less
than 25 cm is recommended. Longer lead lengths can cause
excessive ringing or oscillation.
The SW node (the node connecting the diode anode, induc-
tor, and FET drain) should be kept as small as possible. This
node is one of the main sources for radiated EMI. Sensitive
traces should not be routed in the area of the SW node or
inductor.
A large, continuous ground plane should be placed as an in-
ner or bottom layer for thermal dissipation. This plane should
be considered as a PGND area and not used for SGND con-
nections. To optimize thermal performance, multiple vias
should be placed directly below the exposed pad to increase
heat flow into the ground plane. The recommended number
of vias is 10-12 with a hole diameter between 0.20 mm and
0.33 mm. See Application Note AN-1520 for more informa-
tion.
The CS pin is sensitive to noise. Be sure to route this trace
away from the inductor and the switch node. The CS, LG, and
ILIM traces should be kept as short as possible. As shown
below, R4 must be grounded close to the ground side of R3.
The VCC capacitor should be placed as close as possible to
the IC and grounded close to the PGND pin. Take care in
routing any other VCC traces away from noise sources and
use decoupling capacitors when using VCC as an external
voltage supply.
A ceramic input capacitor must be connected as close as
possible to the VIN pin and grounded close to the PGND pin.
An isolated ground area shown as SGND is recommended
for small signal ground connections. The SGND plane should
connect to both the exposed pad (EP) and SGND pin. The
SGND and PGND ground planes should be connected to their
respective pins and both pins should be connected only
through the exposed pad, EP.
Components connecting all of the following pins should be
placed close to the device and grounded to the SGND plane:
REF, REFIN, AFB, COMP, RT, FF, MODE/F, and SS/SH.
These components and their traces should not be routed near
the switch node or inductor. The LED current sense resistors
should be grounded to the SGND plane for accurate current
30041161
FIGURE 15. Example PCB Layout
21
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Physical Dimensions inches (millimeters) unless otherwise noted
eTSSOP-28 Package
28 Lead Exposed Pad TSOP Package
NS Package Number MXA28A
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22
Notes
23
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相关型号：
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