LM3503ITLX-44 [NSC]
Dual-Display Constant Current LED Driver with Analog Brightness Control; 双显示屏恒流LED驱动器，提供模拟亮度控制
| 型号： | LM3503ITLX-44 |
| 厂家： | 
National Semiconductor |
| 描述： | Dual-Display Constant Current LED Driver with Analog Brightness Control |
| 文件： | 总20页 (文件大小：1062K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2005
LM3503
Dual-Display Constant Current LED Driver with Analog
Brightness Control
>
n
80% Peak Efficiency
General Description
n Output Voltage Protection Options: 16V, 25V, 35V & 44V
n Input Under-Voltage Protection
n Internal Soft Start Eliminates Inrush Current
n 1 MHz Constant-Switching Frequency
n Analog Brightness Control
The LM3503 is a white LED driver for lighting applications.
For dual display backlighting applications, the LM3503 pro-
vides a complete solution. The LM3503 contains two internal
white LED current bypass FET (Field Effect Transistor)
switches. The white LED current can be adjusted with a DC
voltage from a digital to analog converter or RC filtered PWM
(pulse-width-modulated) signal at the Cntrl pin.
n Wide Input Voltage Range: 2.5V to 5.5V
n Low Profile Packages: 1 mm Height
<
— 10 Bump MicroSMD
— 16 Pin LLP
With no external compensation, cycle-by-cycle current limit,
output over-voltage protection, input under-voltage protec-
tion, and dynamic white LED current control capability, the
LM3503 offers superior performance over other step-up
white LED drivers.
Applications
n Dual-Display Display Backlighting in Portable devices
n Cellular Phones and PDAs
Features
n Drives up to 4, 6, 8 or 10 White LEDs for Dual Display
Backlighting
Typical Application
20128662
© 2005 National Semiconductor Corporation
DS201286
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Connection Diagrams
10-Bump Thin MicroSMD Package (TLP10)
16-Lead Thin Leadless Leadframe Package (SQA16A)
20128603
Top View
20128602
Top View
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2
Pin Descriptions/Functions
Bump #
A1
Pin #
Name
Cntrl
Fb
Description
White LED Current Control Connection
9
7
6
B1
Feedback Voltage Connection
C1
VOUT2
Drain Connections of the NMOS and PMOS Field Effect Transistor (FET) Switches
(Figure 1: N2 and P1). Connect 100nF at VOUT2 node if VOUT2 is not used
Over-Voltage Protection (OVP) and Source Connection of the PMOS FET Switch
(Figure 1: P1)
D1
4
VOUT1
D2
D3
C3
B3
A3
A2
2 and 3
Sw
Pgnd
Agnd
VIN
Drain Connection of the Power NMOS Switch (Figure 1: N1)
Power Ground Connection
15 and 16
14
13
12
10
1
Analog Ground Connection
Input Voltage Connection
En2
En1
NC
NMOS FET Switch Control Connection
PMOS FET Switch Control Connection
No Connection
5
NC
No Connection
8
NC
No Connection
11
DAP
NC
No Connection
DAP
Die Attach Pad (DAP), to be soldered to the printed circuit board’s ground plane for
enhanced thermal dissipation.
Cntrl (Bump A1): White LED current control pin. Use this
pin to control the feedback voltage with an external DC
voltage. The feedback voltage is given as VFb = (0.156) *
(VCntrl) for the control voltage range of 0V ≤ VCntrl ≤ 3.5V.
VIN (Bump B3): Input voltage connection pin. The CIN ca-
pacitor should be as close to the device as possible, be-
tween the VIN pin and ground plane.
En2 (Bump A3): Enable pin for the internal NMOS FET
switch (Figure 1: N2) during device operation. When VEn2 is
≥ 1.4V, the internal NMOS FET switch turns off and the SUB
display is turned on. The En2 pin has an internal pull down
circuit, thus the internal NMOS FET switch is normally in the
on state of operation with the SUB display turned off. When
VEn2 is ≤ 0.3V, the internal NMOS FET switch turns on and
the SUB display is turned off. If both VEn1 and VEn2 are ≤
0.3V the LM3503 will shutdown. If VOUT2 is not used, En2
must be floating or grounded and En1 used to enable the
device.
Fb (Bump B1):Output voltage feedback connection.
VOUT2 (Bump C1):Drain connections of the internal PMOS
and NMOS FET switches (Figure 1: P1 and N2). It is recom-
mended to connect 100nF at VOUT2 if VOUT2 is not used for
LM3503-35V & LM3503-44V versions.
VOUT1(Bump D1):
Source connection of the internal PMOS FET switch (Figure
1: P1) and OVP sensing node. The output capacitor must be
connected as close to the device as possible, between the
VOUT1 pin and ground plane. Also connect the Schottky
diode as close as possible to the VOUT1 pin to minimize trace
resistance and EMI radiation.
En1 (Bump A2): Enable pin for the internal PMOS FET
switch (Figure 1: P1) during device operation. When VEn1 is
≤ 0.3V, the internal PMOS FET switch turns on and the MAIN
display is turned off. When VEn1 is ≥ 1.4V, the internal PMOS
FET switch turns off and the MAIN display is turned on. If
both VEn1 and VEn2 are ≤ 0.3V the LM3503 will shutdown.
The En1 pin has an internal pull down circuit, thus the
internal PMOS FET switch is normally in the on state of
operation with the MAIN display turned off. If VOUT2 is not
used, En2 must be grounded and En1 use to enable the
device.
Sw (Bump D2):
Drain connection of the internal power NMOS FET switch
(Figure 1: N1). Minimize the metal trace length and maxi-
mize the metal trace width connected to this pin to reduce
EMI radiation and trace resistance.
Pgnd (Bump D3): Power ground pin. Connect directly to the
ground plane.
Agnd (Bump C3):Analog ground pin. Connect the analog
ground pin directly to the Pgnd pin.
3
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Ordering Information
Voltage
Option
Order Number
Package
Marking
Supplied As
16
LM3503ITL-16
LM3503ITLX-16
LM3503SQ-16
LM3503SQX-16
LM3503ITL-25
LM3503ITLX-25
LM3503SQ-25
LM3503SQX-25
LM3503ITL-35
LM3503ITLX-35
LM3503SQ-35
LM3503SQX-35
LM3503ITL-44
LM3503ITLX-44
LM3503SQ-44
LM3503SQX-44
SBHB
250 Units, Tape-and-Reel
3000 Units, Tape-and-Reel
1000 Units, Tape-and-Reel
4500 Units, Tape-and-Reel
250 Units, Tape-and-Reel
3000 Units, Tape-and-Reel
1000 Units, Tape-and-Reel
4500 Units, Tape-and-Reel
250 Units, Tape-and-Reel
3000 Units, Tape-and-Reel
1000 Units, Tape-and-Reel
4500 Units, Tape-and-Reel
250 Units, Tape-and-Reel
3000 Units, Tape-and-Reel
1000 Units, Tape-and-Reel
4500 Units, Tape-and-Reel
16
16
16
25
25
25
25
35
35
35
35
44
44
44
44
SBHB
L00045B
L00045B
SBJB
SBJB
L00046B
L00046B
SBKB
SBKB
L00047B
L00047B
SDNB
SDNB
L00053B
L00053B
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4
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Rating (Note 2)
Human Body Model:
Machine Model:
2 kV
200V
VIN Pin
Sw Pin
Fb Pin
−0.3V to +5.5V
−0.3V to +48V
−0.3V to +5.5V
−0.3V to +5.5V
−0.3V to +48V
−0.3V to VOUT1
−0.3V to +5.5V
−0.3V to +5.5V
Internally Limited
Operating Conditions (Notes 1, 6)
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
Supply Voltage, VIN Pin
En1 and En2 Pins
−40˚C to +125˚C
−40˚C to +85˚C
2.5V to 5.5V
0V to 5.5V
Cntrl Pin
V
OUT1Pin
VOUT2 Pin
Cntrl Pin
0V to 3.5V
En1
En2
Thermal Properties (Note 4)
Continuous Power Dissipation
Maximum Junction Temperature
Junction-to-Ambient Thermal Resistance (θJA
)
(TJ-MAX
)
+150˚C
Micro SMD Package
65˚C/W
49˚C/W
Storage Temperature Range
−65˚C to +150˚C
Leadless Leadframe Package
Electrical Characteristics (Notes 6, 7) Limits in standard typeface are for TJ = +25˚C. Limits in bold type-
face apply over the full operating junction temperature range (−40˚C ≤ TJ ≤ +125˚C). Unless otherwise specified,VIN = 2.5V.
Symbol
VIN
Parameter
Input Voltage
Conditions
Min
Typ
Max
5.5
1
3
3
Units
V
2.5
IQ
Non-Switching
Switching
Cntrl = 1.6V
0.5
1.9
mA
mA
µA
V
Fb = 0V, Sw Is Floating
En1 = En2 = 0V
Cntrl = 3.5V
Shutdown
0.1
VFb
ICL
Feedback Voltage
NMOS Power Switch
Current Limit
0.5
250
400
450
450
0.55
400
600
750
750
0.6
650
800
1050
1050
16, Fb = 0V
25, Fb = 0V
mA
35, Fb = 0V
44,FB = 0V
IFb
Feedback Pin Output Fb = 0.25V, Cntrl = 1.6V
Bias Current
64
1
500
1.2
nA
FS
Switching Frequency
0.8
MHz
RDS(ON)
NMOS Power Switch
ON Resistance
ISw = 500 mA, (Note 8)
0.55
5
1.1
10
5
Ω
Ω
Ω
(Figure 1: N1)
RPDS(ON) PMOS ON Resistance IPMOS = 20 mA, En1 = 0V, En2 = 1.5V
Of VOUT1/VOUT2
Switch (Figure 1: P1)
RNDS(ON) NMOS ON Resistance INMOS = 20 mA, En1 = 1.5V, En2 = 0V
Of VOUT2/Fb Switch
2.5
(Figure 1: N2)
DMAX
Maximum Duty Cycle Fb = 0V
90
95
8
%
ICNTRL
Cntrl Pin Bias Current Cntrl = 2.5V
14
5
µA
(Note 3)
Cntrl = 0V
0.1
ISw
IV
Sw Pin Leakage
Current (Note 3)
VOUT1 Pin Leakage
Current (Note 3)
Sw = 42V, En1 = En2 =0V
0.01
µA
µA
VOUT1 = 14V, En1 = En2 = 0V (16)
VOUT1 = 23V, En1 = En2 = 0V (25)
VOUT1 = 32V, En1 = En2 = 0V (35)
VOUT1 = 42V, En1 = En2 = 0V (44)
0.1
0.1
0.1
0.1
3
3
3
3
OUT1(OFF)
5
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Electrical Characteristics (Notes 6, 7) Limits in standard typeface are for TJ = +25˚C. Limits in bold
typeface apply over the full operating junction temperature range (−40˚C ≤ TJ ≤ +125˚C). Unless otherwise specified,VIN
=
2.5V. (Continued)
Symbol
IV
Parameter
VOUT1 Pin Bias
Current (Note 3)
Conditions
Min
Typ
40
Max
80
100
100
140
Units
VOUT1 = 14V, En1 = En1 = 1.5V (16)
VOUT1 = 23V, En1 = En2 = 1.5V (25)
VOUT1 = 32V, En1 = En2 = 1.5V (35)
VOUT1 = 42V, En1 = En2 = 1.5V (44)
Fb = En1 = En2 = 0V, VOUT2 = VOUT1 = 42V
OUT1(ON)
50
µA
50
85
IV
VOUT2Pin Leakage
Current (Note 3)
Under-Voltage
Protection
OUT2
0.1
3
µA
V
UVP
OVP
On Threshold
2.4
2.3
15.5
15
2.5
Off Threshold
2.2
Over-Voltage
On Threshold (16)
Off Threshold (16)
On Threshold (25)
Off Threshold (25)
On Threshold (35)
Off Threshold (35)
On Threshold (44)
Off Threshold (44)
14.5
14.0
22.5
21.5
32.0
31.0
40.5
39.0
16.5
16.0
25.5
24.5
35.0
34.0
43.5
42.0
Protection (Note 5)
24
23
V
34
33
42
41
VEn1
PMOS FET Switch
and Device Enabling
Threshold (Figure 1:
P1)
Off Threshold
On Threshold
0.8
0.8
0.3
V
V
1.4
1.4
VEn2
NMOS FET Switch
and Device Enabling
Threshold (Figure 1:
N2)
Off Threshold
On Threshold
0.8
0.8
0.3
IEn1
IEn2
En1 Pin Bias Current En1 = 2.5V
(Note 3) En1 = 0V
En2 Pin Bias Current En2 = 2.5V
(Note 3) En2 = 0V
7
14
14
µA
µA
0.1
7
0.1
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Electrical characteristic specifications do not apply when
operating the device outside of its rated operating conditions.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin.
Note 3: Current flows into the pin.
Note 4: The maximum allowable power dissipation is a function of the maximum junction temperature, T
), the junction-to-ambient thermal resistance, θ , and
JA
J(MAX
the ambient temperature, T . See Thermal Properties for the thermal resistance. The maximum allowable power dissipation at any ambient temperature is calculated
A
using: P
= (T
)–T )/ θ . Exceeding the maximum allowable power dissipation will cause excessive die temperature. For more information on this topic,
D(MAX)
J(MAX A JA
please refer to Application Note 1187(An1187): Leadless Leadframe Package (LLP) and Application Note 1112(AN1112) for microSMD chip scale package.
Note 5: The on threshold indicates that the LM3503 is no longer switching or regulating LED current, while the off threshold indicates normal operation.
Note 6: All voltages are with respect to the potential at the GND pin.
Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 8: NMOS Power On Resistance measured at I = 250mA for sixteen voltage version.
SW
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Block Diagram
20128604
FIGURE 1. Block Diagram
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work is active for dual display applications. En1 controls the
main display (MAIN) segment of the single string white LED
network between pins VOUT1 and VOUT2. En2 controls the
sub display (SUB) segment of the single string white LED
network between the VOUT2 and Fb. If both VEn1 and VEn2
are ≤ 0.3V, the LM3503 will shutdown, for further description
of the En1 and En2 operation, see Figure 3. During shut-
down the output capacitor discharges through the string of
white LEDs and feedback resistor to ground. The LED cur-
rent can be dynamically controlled by a DC voltage on the
Cntrl pin. When VCntrl = 0V the white LED current may not be
equal to zero because of offsets within the LM3503 internal
circuitry. To guarantee zero white LED current the LM3503
must be in shutdown mode operation.
Detailed Description of Operation
The LM3503 utilizes an asynchronous current mode pulse-
width-modulation (PWM) control scheme to regulate the
feedback voltage over specified load conditions. The DC/DC
converter behaves as a controlled current source for white
LED applications. The operation can best be understood by
referring to the block diagram in Figure 1 for the following
operational explanation. At the start of each cycle, the oscil-
lator sets the driver logic and turns on the internal NMOS
power device, N1, conducting current through the inductor
and reverse biasing the external diode. The white LED cur-
rent is supplied by the output capacitor when the internal
NMOS power device, N1, is turned on. The sum of the error
amplifier’s output voltage and an internal voltage ramp are
compared with the sensed power NMOS, N1, switch voltage.
Once these voltages are equal, the PWM comparator will
then reset the driver logic, thus turning off the internal NMOS
power device, N1, and forward biasing the external diode.
The inductor current then flows through the diode to the
white LED load and output capacitor. The inductor current
recharges the output capacitor and supplies the current for
the white LED load. The oscillator then sets the driver logic
again repeating the process. The output voltage of the error
amplifier controls the current through the inductor. This volt-
age will increase for larger loads and decrease for smaller
loads limiting the peak current in the inductor and minimizing
EMI radiation. The duty limit comparator is always opera-
tional, it prevents the internal NMOS power switch, N1, from
being on for more than one oscillator cycle and conducting
large amounts of current. The light load comparator allows
the LM3503 to properly regulate light/small white LED load
currents, where regulation becomes difficult for the
LM3503’s primary control loop. Under light load conditions,
the LM3503 will enter into a pulse skipping pulse-frequency-
mode (PFM) of operation where the operational frequency
will vary with the load. As a result of PFM mode operation,
the output voltage ripple magnitude will significantly in-
crease.
The LM3503 has dedicated protection circuitry active during
normal operation to protect the integrated circuit (IC) and
external components. Soft start circuitry is present in the
LM3503 to allow for slowly increasing the current limit to its
steady-state value to prevent undesired high inrush current
during start up. Thermal shutdown circuitry turns off the
internal NMOS power device, N1, when the internal semi-
conductor junction temperature reaches excessive levels.
The LM3503 has a under-voltage protection (UVP) compara-
tor that disables the internal NMOS power device when
battery voltages are too low, thus preventing an on state
where the internal NMOS power device conducts large
amounts of current. The over-voltage protection (OVP) com-
parator prevents the output voltage from increasing beyond
the protection limit when the white LED string network is
removed or if there is a white LED failure. OVP allows for the
use of low profile ceramic capacitors at the output. The
current through the internal NMOS power device, N1, is
monitored to prevent peak inductor currents from damaging
the IC. If during a cycle (cycle=1/switching frequency) the
peak inductor current exceeds the current limit for the
LM3503, the internal NMOS power device will be turned off
for the remaining duration of that cycle.
The LM3503 has two control pins, En1 and En2, used for
selecting which segment of a single white LED string net-
20128605
FIGURE 2. Operational Characteristics Table
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Typical Performance Characteristics (See Typical Application Circuit : L=DO1608C-223 and
D=B150-13. Efficiency: η = POUT/ PIN = [(VOUT – VFb ) * IOUT] / [VIN * IIN]. TA = +25˚C, unless otherwise stated.)
IQ (Non-Switching) vs VIN
Switching Frequency vs Temperature
20128606
20128607
IQ (Switching) vs VIN
IQ (Switching) vs Temperature
20128608
20128609
10 LED Efficiency vs LED Current
8 LED Efficiency vs LED Current
20128611
20128610
9
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Typical Performance Characteristics (See Typical Application Circuit : L=DO1608C-223 and
D=B150-13. Efficiency: η = POUT/ PIN = [(VOUT – VFb ) * IOUT] / [VIN * IIN]. TA = +25˚C, unless otherwise stated.) (Continued)
6 LED Efficiency vs LED Current
4 LED Efficiency vs LED Current
20128612
20128613
Cntrl Pin Current vs Cntrl Pin Voltage
Maximum Duty Cycle vs Temperature
20128614
20128615
En1 Pin Current vs En1 Pin Voltage
En2 Pin Current vs En2 Pin Voltage
20128663
20128664
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10
Typical Performance Characteristics (See Typical Application Circuit : L=DO1608C-223 and
D=B150-13. Efficiency: η = POUT/ PIN = [(VOUT – VFb ) * IOUT] / [VIN * IIN]. TA = +25˚C, unless otherwise stated.) (Continued)
VOUT1 Pin Current vs VOUT1Pin Voltage
Power NMOS RDS(ON) (Figure 1: N1) vs VIN
20128618
20128619
NMOS RDS(ON) (Figure 1: N2) vs VIN
PMOS RDS(ON) (Figure 1: P1) vs VIN
20128621
20128620
Feedback Voltage vs Cntrl Pin Voltage
Current Limit (LM3503-16) vs Temperature
20128655
20128622
11
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Typical Performance Characteristics (See Typical Application Circuit : L=DO1608C-223 and
D=B150-13. Efficiency: η = POUT/ PIN = [(VOUT – VFb ) * IOUT] / [VIN * IIN]. TA = +25˚C, unless otherwise stated.) (Continued)
Current Limit (LM3503-16) vs VIN
Current Limit (LM3503-25) vs Temperature
20128659
20128657
Current Limit (LM3503-25) vs VIN
Current Limit (LM3503-35/44) vs Temperature
20128658
20128660
Current Limit (LM3503-35/44) vs VIN
Feedback Voltage (VCntrl = 0.8V) vs Temp
20128625
20128624
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Typical Performance Characteristics (See Typical Application Circuit : L=DO1608C-223 and
D=B150-13. Efficiency: η = POUT/ PIN = [(VOUT – VFb ) * IOUT] / [VIN * IIN]. TA = +25˚C, unless otherwise stated.) (Continued)
Feedback Voltage (VCntrl = 1.6V) vs Temp
VIN = 3.6V at 15mA & 4 Leds
20128650
20128626
Dimming Duty Cycle vs. LED Current
VIN = 3.6V at 15mA & 2 Leds
VIN=3.6V, 2LEDs on Main & Sub Display
20128653
20128661
13
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LED CURRENT
Application Information
The LED current is set using the following equation:
WHITE LED CURRENT SETTING
The white LED current is controlled by a DC voltage at the
Cntrl pin.
20128631
The relationship between the Cntrl pin voltage and Fb pin
voltage can be computed with the following:
To determine the maximum output current capability of the
device, it is best to estimate using equations on page 16 and
the minimum peak current limit of the device (see electrical
table). Note the current capability will be higher with less
LEDs in the application.
20128630
VCntrl: Cntrl Pin Voltage. Voltage Range: 0V ≤ VCntrl ≤ 3.5V.
VFb
:
Feedback Pin Voltage.
WHITE LED DIMMING
20128634
FIGURE 3. If VOUT2 is not used, En2 must be grounded
Equation #2:
Aside from varying the DC voltage at the Cntrl pin, white LED
dimming can be accomplished through the RC filtering of a
PWM signal. The PWM signal frequency should be at least a
decade greater than the RC filter bandwidth. Figure 3 is how
the LM3503 should be wired for PWM filtered white LED
dimming functionality. When using PWM dimming, it is rec-
ommended to add 1-2ms delay between the Cntrl signal and
the main Enable sginal (En1) to allow time for the output to
discharge. This will prevent potential flickering especially if
the Sub display is compose of 2 LEDs or less.
FRC
:
RC Filter Bandwidth Cutoff Frequency.
FPWM: PWM Signal Frequency.
R:
C:
Chosen Filter Resistor.
Chosen Filter Capacitor.
For example, using the above equations to determine the
proper RC values. Assume the following condition:VIN= 3.6V,
C=0.01µF and FPWM = 500Hz, then FRC= 50Hz by relation to
equation 2. By rearranging equation 1 to solve for R; R =
318.5K ohms (standard value, R = 316K).
The equations below are guidelines for choosing the correct
RC filter values in relation to the PWM signal frequency.
Equation #1:
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14
Application Information (Continued)
PWM Dimming Duty Cycle vs. LED Current
The results are based on the 2LEDs on Main display and 2LEDs on Sub display
Duty
(%)
10
200Hz
R = 787k ohms
0.78mA
500Hz
R =316k ohms
1.59mA
1KHz
R = 158kohms
2.23mA
10KHz
R=16.2k ohms
3.42mA
50KHz
R=3.16k ohms
3.58mA
100kHz
R=1.62k ohms
3.61mA
20
1.85mA
3.46mA
4.78mA
7.09mA
7.41mA
7.48mA
30
2.88mA
5.35mA
7.33mA
10.77mA
14.48mA
19.1mA
11.25mA
15.12mA
19.06mA
22.98mA
26.9mA
11.34mA
15.24mA
19.16mA
23.10mA
27.05mA
31.00mA
35.00mA
40
3.96mA
7.24mA
9.88mA
50
5.05mA
9.12mA
12.45mA
15.03mA
17.61mA
20.20mA
22.79mA
60
6.08mA
11.03mA
12.94mA
14.83mA
16.73mA
21.86mA
25.71mA
29.53mA
33.32mA
70
7.13mA
80
8.17mA
30.83mA
34.78mA
90
9.24mA
20128637
FIGURE 4. Inductor Current Waveform
CONTINUOUS AND DISCONTINUOUS MODES OF
OPERATION
the average inductor current, IL(avg), divided by half the
inductor ripple current, ∆iL. Using Figure 4, the following
equation can be used to compute R factor:
Since the LM3503 is a constant frequency pulse-width-
modulated step-up regulator, care must be taken to make
sure the maximum duty cycle specification is not violated.
The duty cycle equation depends on which mode of opera-
tion the LM3503 is in. The two operational modes of the
LM3503 are continuous conduction mode (CCM) and dis-
continuous conduction mode (DCM). Continuous conduction
mode refers to the mode of operation where during the
switching cycle, the inductor current never goes to and stays
at zero for any significant amount of time during the switch-
ing cycle. Discontinuous conduction mode refers to the
mode of operation where during the switching cycle, the
inductor current goes to and stays at zero for a significant
amount of time during the switching cycle. Figure 4 illus-
trates the threshold between CCM and DCM operation. In
Figure 4 the inductor current is right on the CCM/DCM
operational threshold. Using this as a reference, a factor can
be introduced to calculate when a particular application is in
CCM or DCM operation. R is a CCM/DCM factor we can use
to compute which mode of operation a particular application
is in. If R is ≥ 1, then the application is operating in CCM.
20128638
20128639
20128640
20128641
<
Conversely, if R is 1, the application is operating in DCM.
VIN
:
Input Voltage.
The R factor inequalities are a result of the components that
make up the R factor. From Figure 4, the R factor is equal to
VOUT
Eff:
:
Output Voltage.
Efficiency of the LM3503.
15
www.national.com
IOUT
:
White LED Current/Load Current.
Inductance Magnitude/Inductor Value.
Duty Cycle for CCM Operation.
Peak Inductor Current.
Application Information (Continued)
L:
Fs:
IOUT
L:
Switching Frequency.
D:
:
White LED Current/Load Current.
Inductance Magnitude/Inductor Value.
Duty Cycle for CCM operation.
Inductor Ripple Current.
IPEAK
:
∆iL:
Inductor Ripple Current.
D:
IL(avg): Average Inductor Current.
∆iL:
The cycle-by-cycle peak inductor current for DCM operation
can be computed with:
IL(avg): Average Inductor Current.
For CCM operation, the duty cycle can be computed with:
20128648
20128642
VIN
Fs:
L:
:
Input Voltage.
Switching Frequency.
Inductance Magnitude/Inductor Value.
Duty Cycle for DCM Operation.
D:
20128643
IPEAK: Peak Inductor Current.
The minimum inductance magnitude/inductor value for the
LM3503 can be calculated using the following, which is only
D:
VOUT: Output Voltage.
VIN Input Voltage.
Duty Cycle for CCM Operation.
>
valid when the duty cycle is 0.5:
:
For DCM operation, the duty cycle can be computed with:
20128649
D:
Duty Cycle.
1-D.
20128644
D’:
RDS(ON): NMOS Power Switch ON Resistance.
Fs:
VIN
L:
Switching Frequency.
:
Input Voltage.
20128645
Inductance Magnitude/Inductor Value.
This equation gives the value required to prevent subhar-
monic oscillations. The result of this equation and the induc-
tor ripple currents should be accounted for when choosing
an inductor value.
D:
Duty Cycle for DCM Operation.
VOUT: Output Voltage.
VIN
:
Input Voltage.
IOUT
Fs:
L:
:
White LED Current/Load Current.
Switching Frequency.
Some recommended Inductor manufactures included but
are not limited to:
Inductor Value/Inductance Magnitude.
DO1608C-223
Coilcraft
www.coilcraft.com
DT1608C-223
INDUCTOR SELECTION
In order to maintain inductance, an inductor used with the
LM3503 should have a saturation current rating larger than
the peak inductor current of the particular application. Induc-
tors with low DCR values contribute decreased power losses
and increased efficiency. The peak inductor current can be
computed for both modes of operation: CCM and DCM.
CAPACITOR SELECTION
Multilayer ceramic capacitors are the best choice for use
with the LM3503. Multilayer ceramic capacitors have the
lowest equivalent series resistance (ESR). Applied voltage
or DC bias, temperature, dielectric material type (X7R, X5R,
Y5V, etc), and manufacturer component tolerance have an
affect on the true or effective capacitance of a ceramic
capacitor. Be aware of how your application will affect a
particular ceramic capacitor by analyzing the aforemen-
tioned factors of your application. Before selecting a capaci-
tor always consult the capacitor manufacturer’s data curves
to verify the effective or true capacitance of the capacitor in
your application.
The cycle-by-cycle peak inductor current for CCM operation
can be computed with:
20128646
INPUT CAPACITOR SELECTION
20128647
The input capacitor serves as an energy reservoir for the
inductor. In addition to acting as an energy reservoir for the
inductor the input capacitor is necessary for the reduction in
input voltage ripple and noise experienced by the LM3503.
The reduction in input voltage ripple and noise helps ensure
VIN
:
Input Voltage.
Eff:
Fs:
Efficiency of the LM3503.
Switching Frequency.
www.national.com
16
Application Information (Continued)
Vishay
On
SS12(1A/20V)
SS14(1A/40V)
SS16(1A/60V)
MBRM120E
www.vishay.com
www.onsemi.com
the LM3503’s proper operation, and reduces the effect of the
LM3503 on other devices sharing the same supply voltage.
To ensure low input voltage ripple, the input capacitor must
have an extremely low ESR. As a result of the low input
voltage ripple requirement multilayer ceramic capacitors are
the best choice. A minimum capacitance of 2.0 µF is required
for normal operation, so consult the capacitor manufactur-
er’s data curves to verify whether the minimum capacitance
requirement is going to be achieved for a particular applica-
tion.
Semiconductor (1A/20V)
MBRS1540T3
(1.5A/40V)
MBR240LT
(2A/40V)
Central
CMSH1-40M
www.centralsemi.com
Semiconductor (1A/40V)
OUTPUT CAPACITOR SELECTION
The output capacitor serves as an energy reservoir for the
white LED load when the internal power FET switch (Figure
1: N1) is on or conducting current. The requirements for the
output capacitor must include worst case operation such as
when the load opens up and the LM3503 operates in over-
voltage protection (OVP) mode operation. A minimum ca-
pacitance of 0.5 µF is required to ensure normal operation.
Consult the capacitor manufacturer’s data curves to verify
whether the minimum capacitance requirement is going to
be achieved for a particular application.
SHUTDOWN AND START-UP
On startup, the LM3503 contains special circuitry that limits
the peak inductor current which prevents large current
spikes from loading the battery or power supply. The
LM3503 is shutdown when both En1 and En2 signals are
less than 0.3V. During shutdown the output voltage is a
diode drop below the supply voltage. When shutdown, the
softstart is reset to prevent inrush current at the next startup.
Some recommended capacitor manufacturers included but
are not limited to:
THERMAL SHUTDOWN
The LM3503 stops regulating when the internal semiconduc-
tor junction temperature reaches approximately 140˚C. The
internal thermal shutdown has approximately 20˚C of hyster-
esis which results in the LM3503 turning back on when the
internal semiconductor junction temperature reaches 120˚C.
When the thermal shutdown temperature is reached, the
softstart is reset to prevent inrush current when the die
temperature cools.
Taiyo-
GMK212BJ105MD
(0805/35V)
www.t-yuden.com
Yuden
muRata
GRM40-035X7R105K www.murata.com
(0805/50V)
TDK
C3216X7R1H105KT
(1206/50V)
www.tdktca.com
C3216X7R1C475K
(1206/16V)
UNDER VOLTAGE PROTECTION
The LM3503 contains protection circuitry to prevent opera-
tion for low input supply voltages. When Vin drops below
2.3V, typically, the LM3503 will no longer regulate. In this
mode, the output voltage will be one diode drop below Vin
and the softstart will be reset. When Vin increases above
2.4V, typically, the device will begin regulating again.
AVX
08053D105MAT
(0805/25V)
www.avxcorp.com
08056D475KAT
(0805/6.3V)
1206ZD475MAT
(1206/10V)
OVER VOLTAGE PROTECTION
The LM3503 contains dedicated ciruitry for monitoring the
output voltage. In the event that the LED network is discon-
nected from the LM3503, the output voltage will increase
and be limited to 15.5V(typ.) for the 16V version, 24V(typ.)
for the 25V version, 34V(typ.) for 35V version and 42V(typ.)
for the 44V version. (see electrical table for more details). In
the event that the network is reconnected regulation will
resume at the appropriate output voltage.
DIODE SELECTION
To maintain high efficiency it is recommended that the aver-
age current rating (IF or IO) of the selected diode should be
larger than the peak inductor current (ILpeak). At the minimum
the average current rating of the diode should be larger than
the maximum LED current. To maintain diode integrity the
peak repetitive forward current (IFRM) must be greater than
or equal to the peak inductor current (ILpeak). Diodes with low
forward voltage ratings (VF) and low junction capacitance
magnitudes (CJ or CT or CD) are conducive to high efficiency.
The chosen diode must have a reverse breakdown voltage
rating (VR and/or VRRM) that is larger than the output voltage
(VOUT). No matter what type of diode is chosen, Schottky or
not, certain selection criteria must be followed:
LAYOUT CONSIDERATIONS
All components, except for the white LEDs, must be placed
as close as possible to the LM3503. The die attach pad
(DAP) must be soldered to the ground plane.
The input bypass capacitor CIN, as shown in the Typical
Application Circuit,, must be placed close to the IC and
connect between the VIN and Pgnd pins. This will reduce
copper trace resistance which effects input voltage ripple of
the IC. For additional input voltage filtering, a 100 nF bypass
capacitor can be placed in parallel with CIN to shunt any high
frequency noise to ground. The output capacitor, COUT, must
be placed close to the IC and be connected between the
VOUT1 and Pgnd pins. Any copper trace connections for the
COUT capacitor can increase the series resistance, which
>
1. VR and VRRM VOUT
2. IF or IO ≥ ILOAD or IOUT
3. IFRM ≥ ILpeak
Some recommended diode manufacturers included but are
not limited to:
17
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Agnd pin should be tied directly to the Pgnd pin. Trace
connections made to the inductor should be minimized to
reduce power dissipation and increase overall efficiency
while reducing EMI radiation. For more details regarding
layout guidelines for switching regulators, refer to Applica-
tions Note AN-1149.
Application Information (Continued)
directly effects output voltage ripple and efficiency. The cur-
rent setting resistor, R1, should be kept close to the Fb pin to
minimize copper trace connections that can inject noise into
the system. The ground connection for the current setting
resistor network should connect directly to the Pgnd pin. The
www.national.com
18
Physical Dimensions inches (millimeters) unless otherwise noted
TLP10: 10-Bump Thin Micro SMD Package
X1 = 1.958 mm
X2 = 2.135 mm
X3 = 0.6 mm
NS Package Number TLP10
16-Lead Thin Leadless Leadframe Package
NS Package Number SQA16A
19
www.national.com
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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