LM3674MF-1.5 [NSC]

2MHz, 600mA Step-Down DC-DC Converter in SOT 23-5; 为2MHz ,采用SOT 23-5 600mA降压DC- DC转换器
LM3674MF-1.5
型号: LM3674MF-1.5
厂家: National Semiconductor    National Semiconductor
描述:

2MHz, 600mA Step-Down DC-DC Converter in SOT 23-5
为2MHz ,采用SOT 23-5 600mA降压DC- DC转换器

转换器 稳压器 开关式稳压器或控制器 电源电路 开关式控制器 光电二极管
文件: 总15页 (文件大小:1100K)
中文:  中文翻译
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January 2006  
LM3674  
2MHz, 600mA Step-Down DC-DC Converter in SOT 23-5  
General Description  
Features  
n 600mA max load current  
The LM3674 step-down DC-DC converter is optimized for  
powering low voltage circuits from a single Li-Ion cell battery  
and input voltage rails from 2.7V to 5.5V. It provides up to  
600mA load current, over the entire input voltage range.  
There are several fixed output voltages and adjustable out-  
put voltage versions.  
n Input voltage range from 2.7V to 5.5V  
n Available in fixed and adjustable output voltages ranging  
from 1.0V to 3.3V  
n
Operates from a single Li-Ion cell Battery  
n Internal synchronous rectification for high efficiency  
n Internal soft start  
n 0.01 µA typical shutdown current  
The device offers superior features and performance for  
mobile phones and similar portable systems. During PWM  
mode, the device operates at a fixed-frequency of 2 MHz  
(typ). Internal synchronous rectification provides high effi-  
ciency during PWM mode operation. In shutdown mode, the  
device turns off and reduces battery consumption to 0.01 µA  
(typ).  
n
2 MHz PWM fixed switching frequency (typ)  
n SOT23-5 package  
n Current overload protection and Thermal shutdown  
protection  
The LM3674 is available in SOT23-5 in leaded (PB) and  
lead-free (NO PB) versions. A high switching frequency of 2  
MHz (typ) allows use of only three tiny external surface-  
mount components, an inductor and two ceramic capacitors.  
Applications  
n Mobile phones  
n PDAs  
n MP3 players  
n Portable instruments  
n W-LAN  
n
Digital still cameras  
n Portable Hard disk drives  
Typical Application  
20167201  
FIGURE 1. Typical Application Circuit  
© 2006 National Semiconductor Corporation  
DS201672  
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Typical Application (Continued)  
20167230  
FIGURE 2. Typical Application Circuit  
Connection Diagram and Package Mark Information  
SOT23-5 Package  
NS Package Number MF05A  
20167202  
Note: The actual physical placement of the package marking will vary from part to part.  
FIGURE 3. Top View  
Pin Descriptions  
Pin #  
Name  
Description  
1
2
3
VIN  
Power supply input. Connect to the input filter capacitor ( Figure 1).  
GND  
EN  
Ground pin.  
<
Enable input. The device is in shutdown mode when voltage to this pin is 0.4V and  
>
enable when 1.0V. Do not leave this pin floating.  
4
5
FB  
Feedback analog input. Connect to the output filter capacitor for fixed voltage  
versions. For adjustable version external resistor dividers are required ( Figure 2).  
The internal resistor dividers are disabled for the adjustable version.  
Switching node connection to the internal PFET switch and NFET synchronous  
rectifier.  
SW  
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2
Ordering Information  
Voltage Option  
Order Number  
(Level 95)  
SPEC  
Supplied As  
(#/reel)  
1000  
Package Marking  
(V)  
1.2  
LM3674MF-1.2  
LM3674MFX-1.2  
LM3674MF-1.2  
LM3674MFX-1.2  
LM3674MF-1.5  
LM3674MFX-1.5  
LM3674MF-1.5  
LM3674MFX-1.5  
LM3674MF-1.8  
LM3674MFX-1.8  
LM3674MF-1.8  
LM3674MFX-1.8  
LM3674MF-ADJ  
LM3674MFX-ADJ  
LM3674MF-ADJ  
LM3674MFX-ADJ  
NO PB  
NO PB  
SLRB  
3000  
1000  
3000  
1.5  
1.8  
NO PB  
NO PB  
SLSB  
SLHB  
SLTB  
1000  
3000  
1000  
3000  
NO PB  
NO PB  
1000  
3000  
1000  
3000  
ADJ  
NO PB  
NO PB  
1000  
3000  
1000  
3000  
3
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Absolute Maximum Ratings (Note 1)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales Office/  
Distributors for availability and specifications.  
Operating Ratings (Notes 1, 2)  
Input Voltage Range (Note 11)  
2.7V to 5.5V  
Recommended Load Current  
0A to 600 mA  
Junction Temperature (TJ) Range  
Ambient Temperature (TA) Range  
−30˚C to +125˚C  
−30˚C to +85˚C  
VIN Pin: Voltage to GND  
EN, FB, SW Pin:  
−0.2V to 6.0V  
(GND−0.2V) to  
(VIN + 0.2V)  
Internally Limited  
+125˚C  
Thermal Properties  
Continuous Power Dissipation  
Junction Temperature (TJ-MAX  
Storage Temperature Range  
Maximum Lead Temperature  
(Soldering, 10 sec.)  
)
Junction-to-Ambient  
Thermal Resistance (θJA  
(SOT23-5) for a 2 layer  
board (Note 6)  
Junction-to-Ambient  
−65˚C to +150˚C  
260˚C  
)
Thermal Resistance (θJA  
(SOT23-5) for a 4 layer  
board (Note 6)  
)
250˚C/W  
130˚C/W  
ESD Rating (Note 3)  
Human Body model: All Pins  
Machine Model: All Pins  
2 kV  
200V  
Electrical Characteristics (Notes 2, 9, 10) Limits in standard typeface are for TJ = 25˚C. Limits in boldface  
type apply over the full operating junction temperature range (−30˚C TJ 125˚C). Unless otherwise noted, specifications  
apply to the LM3674 with VIN = EN = 3.6V  
Symbol  
Parameter  
Feedback Voltage (Note 12)  
Line Regulation  
Condition  
IO = 10mA  
Min  
-4  
Typ  
Max  
+4  
Units  
%
2.7V VIN 5.5V  
IO = 100 mA  
0.083  
0.0010  
%/V  
VFB  
Load Regulation  
100 mA IO 600 mA  
VIN = 3.6V  
%/mA  
VREF  
ISHDN  
IQ  
Internal Reference Voltage  
Shutdown Supply Current  
DC Bias Current into VIN  
(Note 7)  
0.5  
0.01  
300  
V
EN = 0V  
1
µA  
µA  
No load, device is not  
switching (FB=0V)  
ISW = 200mA  
600  
RDSON (P)  
RDSON (N)  
ILIM  
Pin-Pin Resistance for PFET  
Pin-Pin Resistance for NFET  
Switch Peak Current Limit  
Logic High Input  
380  
250  
500  
400  
mΩ  
mΩ  
mA  
V
ISW = 200mA  
Open Loop (Note 8)  
830  
1.0  
1020  
1200  
VIH  
VIL  
Logic Low Input  
0.4  
1
V
IEN  
Enable (EN) Input Current  
Internal Oscillator Frequency  
0.01  
2
µA  
FOSC  
PWM Mode  
1.6  
2.6  
MHz  
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the  
device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the  
Electrical Characteristics tables.  
Note 2: All voltages are with respect to the potential at the GND pin.  
Note 3: The Human body model is a 100 pF capacitor discharged through a 1.5 kresistor into each pin. The machine model is a 200 pF capacitor discharged  
directly into each pin (MIL-STD-883 3015.7). National Semiconductor recommends that all intergrated circuits be handled with appropriate precautions. Failure to  
observe proper ESD handling techniques can result in damage.  
Note 4: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T = 150˚C (typ.) and disengages at T  
=
J
J
130˚C  
Note 5: In Applications where high power dissipation and /or poor package resistance is present, the maximum ambient temperature may have to be derated.  
Maximum ambient temperature (T ) is dependent on the maximum operating junction temperature (T ), the maximum power dissipation of the device in  
A-MAX  
J-MAX  
the application (P  
) and the junction to ambient thermal resistance of the package (θ ) in the application, as given by the following equation: T  
= T  
-
D-MAX  
JA  
A-MAX  
J-MAX  
(θ x P  
). Refer to Dissipation ration table for P  
values at different ambient temperatures.  
JA  
D-MAX  
D-MAX  
Note 6: Junction to ambient thermal resistance is highly application and board layout dependent. In applications where high power dissipation exists, special care  
must be given to thermal dissipation issues in board design. Value specified here 250˚C/W is based on measurement results using a 2 layer, 4" X 3", 2 oz. Cu board  
as per JEDEC standards. The (θ ) is 130˚C/W if a 4 layer, 4" X 3", 2/1/1/2 oz. Cu board as per JEDEC standards is used.  
JA  
Note 7: For the ADJ version the resistor dividers should be selected such that at the desired output voltage, the voltage at the FB pin is 0.5V.  
Note 8: Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Electrical Characteristic table reflects open  
loop data (FB=0V and current drawn from SW pin ramped up until cycle by cycle current limit is activated). Closed loop current limit is the peak inductor current  
measured in the application circuit by increasing output current until output voltage drops by 10%.  
Note 9: Min and Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.  
Note 10: The parameters in the electrical characteristic table are tested at V = 3.6V unless otherwise specified. For performance over the input voltage range refer  
IN  
to datasheet curves.  
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4
Electrical Characteristics (Notes 2, 9, 10) Limits in standard typeface are for TJ = 25˚C. Limits in boldface  
type apply over the full operating junction temperature range (−30˚C TJ 125˚C). Unless otherwise noted, specifications  
apply to the LM3674 with VIN = EN = 3.6V (Continued)  
Note 11: Input voltage range recommended for ideal applications performance for the specified output voltages are given below  
<
OUT  
V
IN  
V
IN  
= 2.7V to 5.5V for 1.0V V  
1.8V  
= ( V  
+ V  
) to 5.5V for 1.8 V  
3.3V  
OUT  
OUT  
DROP OUT  
Where V  
= I  
* (R  
+ R  
)
INDUCTOR  
DROP OUT  
LOAD  
DSON (P)  
Note 12: Feedback voltage specification for ADJ include the tolerances of the resistor divider network. ADJ configured to 1.5V output.  
Dissipation Rating Table  
θJA  
TA 25˚C (Power Rating) TA = 60˚C (Power Rating) TA = 85˚C (Power Rating)  
250˚C/W (2 layer board)  
130˚C/W (4 layer board)  
400mW  
770mW  
260mW  
500mW  
160mW  
310mW  
5
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Block Diagram  
20167232  
FIGURE 4. Simplified Functional Diagram  
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6
Typical Performance Characteristics (unless otherwise stated: VIN = 3.6V, VOUT = 1.5V, TA = 25˚C)  
Quiescent Current vs. Supply Voltage  
(FB = 0V, No Switching)  
IQ Shutdown vs. Temp  
20167244  
20167205  
Feedback Bias Current vs. Temp  
Output Voltage vs. Supply Voltage  
20167265  
20167206  
Output Voltage vs. Temperature  
Output Voltage vs. Output Current  
20167298  
20167266  
7
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Typical Performance Characteristics (unless otherwise stated: VIN = 3.6V, VOUT = 1.5V, TA  
=
25˚C) (Continued)  
Efficiency vs. Output Current  
RDSON vs. Temperature  
(VOUT = 1.2V, L = 2.2uH, DCR = 200m)  
20167210  
20167267  
Efficiency vs. Output Current  
Efficiency vs. Output Current  
(VOUT = 1.5V, L = 2.2uH, DCR = 200m)  
(VOUT = 1.8V, L = 2.2uH, DCR = 200m)  
20167268  
20167269  
Efficiency vs. Output Current  
(VOUT = 3.3V, L = 2.2uH, DCR = 200m)  
Switching Frequency vs. Temperature  
20167216  
20167299  
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8
Typical Performance Characteristics (unless otherwise stated: VIN = 3.6V, VOUT = 1.5V, TA  
=
25˚C) (Continued)  
Open/Closed Loop Current Limit vs. Temperature  
Line Transient Response  
20167218  
20167297  
Start Up  
Load Transient  
(Output Current = 300mA)  
20167223  
20167247  
Start Up  
(Output Current = 10mA)  
20167224  
9
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stage is proportional to the input voltage. To eliminate this  
dependence, feed forward inversely proportional to the input  
voltage is introduced.  
Operation Description  
DEVICE INFORMATION  
While in PWM mode, the output voltage is regulated by  
switching at a constant frequency and then modulating the  
energy per cycle to control power to the load. At the begin-  
ning of each clock cycle the PFET switch is turned on and  
the inductor current ramps up until the comparator trips and  
the control logic turns off the switch.  
The LM3674, a high efficiency step down DC-DC switching  
buck converter, delivers a constant voltage from a single  
Li-Ion battery and input voltage rails from 2.7V to 5.5V to  
portable devices such as cell phones and PDAs. Using a  
voltage mode architecture with synchronous rectification, the  
LM3674 has the ability to deliver up to 600 mA depending on  
the input voltage, output voltage, ambient temperature and  
the inductor chosen.  
The current limit comparator can also turn off the switch in  
case the current limit of the PFET is exceeded. Then the  
NFET switch is turned on and the inductor current ramps  
down. The next cycle is initiated by the clock turning off the  
NFET and turning on the PFET.  
There are two modes of operation depending on the current  
required - PWM (Pulse Width Modulation), and shutdown.  
The device operates in PWM throughout the IOUT range.  
Shutdown mode turns off the device, offering the lowest  
current consumption (ISHUTDOWN = 0.01 µA typ).  
Additional features include soft-start, under voltage protec-  
tion, current overload protection, and thermal overload pro-  
tection. As shown in Figure 1, only three external power  
components are required for implementation.  
The part uses an internal reference voltage of 0.5V. It is  
recommended to keep the part in shutdown until the input  
voltage is 2.7V or higher.  
CIRCUIT OPERATION  
During the first portion of each switching cycle, the control  
block in the LM3674 turns on the internal PFET switch. This  
allows current to flow from the input through the inductor to  
the output filter capacitor and load. The inductor limits the  
current to a ramp with a slope of  
20167275  
Internal Synchronous Rectification  
While in PWM mode, the LM3674 uses an internal NFET as  
a synchronous rectifier to reduce rectifier forward voltage  
drop and associated power loss. Synchronous rectification  
provides a significant improvement in efficiency whenever  
the output voltage is relatively low compared to the voltage  
drop across an ordinary rectifier diode.  
by storing energy in a magnetic field. During the second  
portion of each cycle, the controller turns the PFET switch  
off, blocking current flow from the input, and then turns the  
NFET synchronous rectifier on. The inductor draws current  
from ground through the NFET to the output filter capacitor  
and load, which ramps the inductor current down with a  
slope of  
Current Limiting  
A current limit feature allows the LM3674 to protect itself and  
external components during overload conditions. PWM  
mode implements current limiting using an internal compara-  
tor that trips at 1020 mA (typ). If the output is shorted to  
ground the device enters a timed current limit mode where  
the NFET is turned on for a longer duration until the inductor  
current falls below a low threshold, ensuring inductor current  
has more time to decay, thereby preventing runaway.  
The output filter stores charge when the inductor current is  
high, and releases it when the inductor current is low,  
smoothing the voltage across the load.  
SOFT-START  
The LM3674 has a soft-start circuit that limits in-rush current  
during start-up. During start-up the switch current limit is  
increased in steps. Soft start is activated only if EN goes  
from logic low to logic high after Vin reaches 2.7V. Soft start  
is implemented by increasing switch current limit in steps of  
70mA, 140mA, 280mA, and 1020mA (typ. switch current  
limit). The start-up time thereby depends on the output ca-  
pacitor and load current demanded at start-up. Typical  
start-up times with 10µF output capacitor and 300mA load  
current is 350µs and with 10mA load current is 240µs.  
The output voltage is regulated by modulating the PFET  
switch on time to control the average current sent to the load.  
The effect is identical to sending a duty-cycle modulated  
rectangular wave formed by the switch and synchronous  
rectifier at the SW pin to a low-pass filter formed by the  
inductor and output filter capacitor. The output voltage is  
equal to the average voltage at the SW pin.  
PWM OPERATION  
During PWM ( Pulse Width Modulation) operation the con-  
verter operates as a voltage-mode controller with input volt-  
age feed forward. This allows the converter to achieve ex-  
cellent load and line regulation. The DC gain of the power  
LDO - LOW DROP OUT OPERATION  
The LM3674-ADJ can operate at 100% duty cycle (no  
switching, PMOS switch completely on) for low drop out  
support of the output voltage. In this way the output voltage  
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10  
VFB = Feedback Voltage (0.5V typ)  
R1 = Resistor from VOUT to FB ()  
R2 = Resistor from FB to GND ()  
Operation Description (Continued)  
will be controlled down to the lowest possible input voltage.  
When the device operates near 100% duty cycle, the output  
voltage supply ripple is slightly higher, approximately 25mV.  
For any output voltage greater than or equal to 1.0V a  
frequency zero must be added at 45KHz for stability. The  
formula is:  
The minimum input voltage needed to support the output  
voltage is  
ILOAD  
Load current  
For output voltages greater than or equal to 2.5V, a pole  
must also be placed at 45KHz as well. If the pole and zero  
are at the same frequency the formula for calculation of C2  
is:  
RDSON,PFET Drain to source resistance of PFET  
switch in the triode region  
RINDUCTOR Inductor resistance  
Application Information  
OUTPUT VOLTAGE SELECTION FOR ADJUSTABLE  
(LM3674-ADJ)  
The formula for location of zero and pole frequency created  
by adding C1,C2 are given below. It can be seen that by  
adding C1, a zero as well as a higher frequency pole is  
introduced.  
The output voltage of the adjustable parts can be pro-  
grammed through the resistor network connected from VOUT  
to FB the to GND. VOUT will be adjusted to make FB equal to  
0.5V. The resistor from FB to GND (R2) should be 200 kto  
keep the current drawn through this network small but large  
enough that it is not susceptible to noise. If R2 is 200K, and  
given the VFB is 0.5V, then the current through the resistor  
feedback network will be 2.5µA. The output voltage formula  
is:  
See the " LM3674-ADJ Configurations for " Various VOUT  
table.  
"
VOUT = Output Voltage (V)  
TABLE 1. Adjustable LM3674 Configurations for Various VOUT  
VOUT (V)  
1.0  
R1 (K)  
200  
R2 (K)  
200  
C1 (pF)  
18  
C2 (pF)  
None  
None  
None  
None  
None  
None  
None  
None  
None  
33  
L (µH)  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
2.2  
CIN (µF)  
4.7  
COUT (µF)  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
1.1  
191  
158  
18  
4.7  
1.2  
280  
200  
12  
4.7  
1.5  
357  
178  
10  
4.7  
1.6  
442  
200  
8.2  
8.2  
8.2  
6.8  
8.2  
8.2  
6.8  
4.7  
1.7  
432  
178  
4.7  
1.8  
464  
178  
4.7  
1.875  
2.5  
523  
191  
4.7  
402  
100  
4.7  
2.8  
464  
100  
4.7  
3.3  
562  
100  
33  
4.7  
INDUCTOR SELECTION  
to guarantee good performance is 1.76µH at ILIM (typ) dc  
current over the ambient temperature range. Shielded  
inductors radiate less noise and should be preferred.  
There are two main considerations when choosing an induc-  
tor; the inductor should not saturate, and the inductor current  
ripple should be small enough to achieve the desired output  
voltage ripple. Different saturation current rating specifica-  
tions are followed by different manufacturers so attention  
must be given to details. Saturation current ratings are typi-  
cally specified at 25˚C. However, ratings at the maximum  
ambient temperature of application should be requested  
from the manufacturer. The minimum value of inductance  
There are two methods to choose the inductor saturation  
current rating.  
Method 1:  
The saturation current is greater than the sum of the maxi-  
mum load current and the worst case average to peak  
inductor current. This can be written as:  
11  
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for design flexibility. This allows substitution of a low-noise  
toroidal inductor, in the event that noise from low-cost bobbin  
models is unacceptable.  
Application Information (Continued)  
INPUT CAPACITOR SELECTION  
A ceramic input capacitor of 4.7 µF, 6.3V is sufficient for most  
applications. Place the input capacitor as close as possible  
to the VIN pin of the device. A larger value may be used for  
improved input voltage filtering. Use X7R or X5R types; do  
not use Y5V. DC bias characteristics of ceramic capacitors  
must be considered when selecting case sizes like 0805 and  
0603. The minimum input capacitance to guarantee  
good performance is 2.2µF at 3V dc bias; 1.5µF at 5V dc  
bias including tolerances and over ambient temperature  
range. The input filter capacitor supplies current to the PFET  
switch of the LM3674 in the first half of each cycle and  
reduces voltage ripple imposed on the input power source. A  
ceramic capacitor’s low ESR provides the best noise filtering  
of the input voltage spikes due to this rapidly changing  
current. Select a capacitor with sufficient ripple current rat-  
ing. The input current ripple can be calculated as:  
IRipple : average to peak inductor current  
Ioutmax: maximum load current (600mA)  
VIN: maximum input voltage in application  
L: min inductor value including worst case tolerances  
(30% drop can be considered for method 1)  
f: minimum switching frequency (1.6 MHz)  
VOUT: output voltage  
Method 2:  
A more conservative and recommended approach is to  
choose an inductor that has saturation current rating greater  
than the max current limit of 1200 mA.  
A 2.2 µH inductor with a saturation current rating of at least  
1200 mA is recommended for most applications. The induc-  
tor’s resistance should be less than around 0.3for good  
efficiency. Table 2 lists suggested inductors and suppliers.  
For low-cost applications, an unshielded bobbin inductor is  
suggested. For noise critical applications, a toroidal or  
shielded-bobbin inductor should be used. A good practice is  
to lay out the board with overlapping footprints of both types  
TABLE 2. Suggested Inductors and Their Suppliers  
Vendor Dimensions LxWxH(mm)  
Coilcraft 3.3 x 3.3 x 1.4  
Model  
D.C.R (max)  
200 mΩ  
150 mΩ  
53 mΩ  
DO3314-222MX  
LPO3310-222MX  
ELL5GM2R2N  
CDRH2D14-2R2  
Coilcraft  
Panasonic  
Sumida  
3.3 x 3.3 x 1.0  
5.2 x 5.2 x 1.5  
3.2 x 3.2 x 1.55  
94 mΩ  
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12  
Application Information (Continued)  
OUTPUT CAPACITOR SELECTION  
A ceramic output capacitor of 10 µF, 6.3V is sufficient for  
most applications. Use X7R or X5R types; do not use Y5V.  
DC bias characteristics of ceramic capacitors must be con-  
sidered when selecting case sizes like 0805 and 0603. DC  
bias characteristics vary from manufacturer to manufacturer  
and dc bias curves should be requested from them as part of  
the capacitor selection process.  
Because these two components are out of phase the rms  
value can be used to get an approximate value of peak-to-  
peak ripple.  
Voltage peak-to-peak ripple, root mean squared =  
The minimum output capacitance to guarantee good  
performance is 5.75µF at 1.8V dc bias including toler-  
ances and over ambient temperature range. The output  
filter capacitor smoothes out current flow from the inductor to  
the load, helps maintain a steady output voltage during  
transient load changes and reduces output voltage ripple.  
These capacitors must be selected with sufficient capaci-  
tance and sufficiently low ESR to perform these functions.  
Note that the output ripple is dependent on the current ripple  
and the equivalent series resistance of the output capacitor  
(RESR).  
The RESR is frequency dependent (as well as temperature  
dependent); make sure the value used for calculations is at  
the switching frequency of the part.  
The output voltage ripple is caused by the charging and  
discharging of the output capacitor and by the RESR and can  
be calculated as:  
Voltage peak-to-peak ripple due to capacitance can be ex-  
pressed as follow:  
Voltage peak-to-peak ripple due to ESR =  
TABLE 3. Suggested Capacitors and Their Suppliers  
Model  
Type  
Vendor  
Voltage Rating  
Case size inch (mm)  
10 µF for COUT  
GRM21BR60J106K  
C2012X5R0J106K  
JMK212BJ106K  
4.7 µF for CIN  
Ceramic, X5R  
Ceramic, X5R  
Ceramic, X5R  
Murata  
TDK  
6.3V  
6.3V  
6.3V  
0805 (2012)  
0805 (2012)  
0805 (2012)  
Taiyo-Yuden  
GRM21BR60J475K  
JMK212BJ475K  
C2012X5R0J475K  
Ceramic, X5R  
Ceramic, X5R  
Ceramic, X5R  
Murata  
Taiyo-Yuden  
TDK  
6.3V  
6.3V  
6.3V  
0805 (2012)  
0805 (2012)  
0805 (2012)  
BOARD LAYOUT CONSIDERATIONS  
EMI, ground bounce, and resistive voltage loss in the traces.  
These can send erroneous signals to the DC-DC converter  
IC, resulting in poor regulation or instability.  
PC board layout is an important part of DC-DC converter  
design. Poor board layout can disrupt the performance of a  
DC-DC converter and surrounding circuitry by contributing to  
13  
www.national.com  
Application Information (Continued)  
20167231  
FIGURE 5. Board Layout Design Rules for the LM3674  
Good layout for the LM3674 can be implemented by follow-  
ing a few simple design rules, as illustrated in .  
reduces voltage errors caused by resistive losses across  
the traces.  
1. Place the LM3674, inductor and filter capacitors close  
together and make the traces short. The traces between  
these components carry relatively high switching cur-  
rents and act as antennas. Following this rule reduces  
radiated noise. Special care must by given to place the  
input filter capacitor very close to the VIN and GND pin.  
5. Route noise sensitive traces, such as the voltage feed-  
back path, away from noisy traces between the power  
components. The voltage feedback trace must remain  
close to the LM3674 circuit and should be direct but  
should be routed opposite to noisy components. This  
reduces EMI radiated onto the DC-DC converter’s own  
voltage feedback trace. A good approach is to route the  
feedback trace on another layer and to have a ground  
plane between the top layer and layer on which the  
feedback trace is routed. In the same manner for the  
adjustable part it is desired to have the feedback divid-  
ers on the bottom layer.  
2. Arrange the components so that the switching current  
loops curl in the same direction. During the first half of  
each cycle, current flows from the input filter capacitor,  
through the LM3674 and inductor to the output filter  
capacitor and back through ground, forming a current  
loop. In the second half of each cycle, current is pulled  
up from ground, through the LM3674 by the inductor, to  
the output filter capacitor and then back through ground,  
forming a second current loop. Routing these loops so  
the current curls in the same direction prevents mag-  
netic field reversal between the two half-cycles and re-  
duces radiated noise.  
6. Place noise sensitive circuitry, such as radio IF blocks,  
away from the DC-DC converter, CMOS digital blocks  
and other noisy circuitry. Interference with noise-  
sensitive circuitry in the system can be reduced through  
distance.  
In mobile phones, for example, a common practice is to  
place the DC-DC converter on one corner of the board,  
arrange the CMOS digital circuitry around it (since this also  
generates noise), and then place sensitive preamplifiers and  
IF stages on the diagonally opposing corner. Often, the  
sensitive circuitry is shielded with a metal pan and power to  
it is post-regulated to reduce conducted noise, using low-  
dropout linear regulators.  
3. Connect the ground pins of the LM3674, and filter ca-  
pacitors together using generous component-side cop-  
per fill as a pseudo-ground plane. Then, connect this to  
the ground-plane (if one is used) with several vias. This  
reduces ground-plane noise by preventing the switching  
currents from circulating through the ground plane. It  
also reduces ground bounce at the LM3674 by giving it  
a low-impedance ground connection.  
4. Use wide traces between the power components and for  
power connections to the DC-DC converter circuit. This  
www.national.com  
14  
Physical Dimensions inches (millimeters) unless otherwise noted  
5-Lead SOT23-5 Package  
NS Package Number MF05A  
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves  
the right at any time without notice to change said circuitry and specifications.  
For the most current product information visit us at www.national.com.  
LIFE SUPPORT POLICY  
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS  
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR  
CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body, or  
(b) support or sustain life, and whose failure to perform when  
properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to result  
in a significant injury to the user.  
2. A critical component is any component of a life support  
device or system whose failure to perform can be reasonably  
expected to cause the failure of the life support device or  
system, or to affect its safety or effectiveness.  
BANNED SUBSTANCE COMPLIANCE  
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products  
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain  
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.  
Leadfree products are RoHS compliant.  
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Support Center  
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Fax: +49 (0) 180-530 85 86  
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