LM4836MTEX/NOPB [NSC]
IC 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDSO28, TSSOP-28, Audio Control IC;
| 型号： | LM4836MTEX/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | IC 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDSO28, TSSOP-28, Audio Control IC 复用器 放大器 功率放大器 |
| 文件： | 总16页 (文件大小：661K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
June 1999
LM4836
Stereo 2W Audio Power Amplifiers
with DC Volume Control, Bass Boost, and Input Mux
General Description
Key Specifications
The LM4836 is a monolithic integrated circuit that provides
DC volume control, and stereo bridged audio power amplifi-
ers capable of producing 2W into 4Ω (Note 1) with less than
1.0% THD+N, or 2.2W into 3Ω (Note 2) with less than 1.0%
THD+N.
Boomer® audio integrated circuits were designed specifically
to provide high quality audio while requiring a minimum
amount of external components. The LM4836 incorporates a
DC volume control, stereo bridged audio power amplifiers,
selectable gain or bass boost, and an input mux making it
n PO at 1% THD+N
into 3Ω (LM4836MTE)
into 4Ω (LM4836MTE)
into 8Ω (LM4836)
2.2W(typ)
2.0W(typ)
1.1W(typ)
1.0%(typ)
n Single-ended mode - THD+N
at 85mW into 32Ω
n Shutdown current
0.2µA(typ)
optimally suited for multimedia monitors, portable radios, Features
desktop, and portable computer applications.
n PC98 and PC99 Compliant
n DC Volume Control Interface
n Input mux
The LM4836 features an externally controlled, low-power
consumption shutdown mode, and both a power amplifier
and headphone mute for maximum system flexibility and
performance.
Note 1: When properly mounted to the circuit board, the LM4836MTE will
deliver 2W into 4Ω. The LM4836MT will deliver 1.1W into 8Ω. See the Appli-
cation Information section for LM4836MTE usage information.
n System Beep Detect
n Stereo switchable bridged/single-ended power amplifiers
n Selectable internal/external gain and bass boost
configurable
n “Click and pop” suppression circuitry
n Thermal shutdown protection circuitry
Note 2: An LM4836MTE which has been properly mounted to the circuit
board and forced-air cooled will deliver 2.2W into 3Ω.
Applications
n Portable and Desktop Computers
n Multimedia Monitors
n Portable Radios, PDAs, and Portable TVs
Connection Diagram
TSSOP Package
DS101088-2
Top View
Order Number LM4836MT
See NS Package Number MTC28 for TSSOP
Order Number LM4836MTE
See NS Package Number MXA28A for Exposed DAP TSSOP
Boomer® is a registered trademark of NationalSemiconductor Corporation.
© 1999 National Semiconductor Corporation
DS101088
www.national.com
Absolute Maximum Ratings (Note 10)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
θJC (typ) — MTC28
20˚C/W
80˚C/W
2˚C/W
θJA (typ) — MTC28
θJC (typ) — MXA28A
θJA (typ) — MXA28A (Note 4)
θJA (typ) — MXA28A (Note 3)
θJA (typ) — MXA28A (Note 5)
θJA (typ) — MXA28A (Note 6)
41˚C/W
54˚C/W
59˚C/W
93˚C/W
Supply Voltage
6.0V
-65˚C to +150˚C
−0.3V to VDD +0.3V
Internally limited
2500V
Storage Temperature
Input Voltage
Power Dissipation
Operating Ratings
ESD Susceptibility (Note 12)
ESD Susceptibility (Note 13)
Junction Temperature
250V
Temperature Range
TMIN ≤ TA ≤TMAX
150˚C
−40˚C ≤TA ≤ 85˚C
2.7V≤ VDD ≤ 5.5V
Soldering Information
Vapor Phase (60 sec.)
Supply Voltage
215˚C
220˚C
Infrared (15 sec.)
See AN-450 “Surface Mounting and their Effects on
Product Reliability” for other methods of soldering
surface mount devices.
Electrical Characteristics for Entire IC
(Notes 7, 10)
The following specifications apply for VDD = 5V and TA = 25˚C unless otherwise noted.
LM4836
Units
(Limits)
Symbol
Parameter
Supply Voltage
Conditions
Typical
Limit
(Note 15)
(Note 14)
VDD
2.7
5.5
30
2.0
4
V (min)
V (max)
mA (max)
µA (max)
V (min)
IDD
ISD
VIH
VIL
Quiescent Power Supply Current
Shutdown Current
VIN = 0V, IO = 0A
Vpin 24 = VDD
15
0.2
Headphone Sense High Input Voltage
Headphone Sense Low Input Voltage
0.8
V (max)
Electrical Characteristics for Volume Attenuators
(Notes 7, 10)
The following specifications apply for VDD = 5V and TA = 25˚C unless otherwise noted.
LM4836
Units
(Limits)
Symbol
Parameter
Attenuator Range
Conditions
Typical
Limit
(Note 15)
(Note 14)
±
CRANGE
Gain with Vpin 5 ≥ 4.5V
0
0.5
dB (max)
dB (min)
dB (min)
dB (min)
dB (min)
0
−1.0
-70
-80
-70
CRANGE
AM
Attenuator Range
Mute Attenuation
Attenuation with Vpin 5 = 0V
Vpin 3 = 5V, Bridged Mode
Vpin 3 = 5V, Single-Ended Mode
-73
-88
-80
Electrical Characteristics for Single-Ended Mode Operation
(Notes 7, 10)
The following specifications apply for VDD = 5V and TA = 25˚C unless otherwise noted.
LM4836
Units
(Limits)
Symbol
PO
Parameter
Output Power
Conditions
Typical
Limit
(Note 14)
(Note 15)
THD+N = 1.0%; f = 1kHz;
85
95
mW
mW
RL = 32Ω
THD+N = 10%; f = 1 kHz; RL
=
32Ω
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2
Electrical Characteristics for Single-Ended Mode Operation (Continued)
(Notes 7, 10)
The following specifications apply for VDD = 5V and TA = 25˚C unless otherwise noted.
LM4836
Units
(Limits)
Symbol
THD+N
PSRR
SNR
Parameter
Total Harmonic Distortion+Noise
Power Supply Rejection Ratio
Signal to Noise Ratio
Conditions
Typical
Limit
(Note 14)
(Note 15)
VOUT = 1VRMS, f=1kHz, RL = 10kΩ,
0.065
58
%
AVD = 1
CB = 1.0 µF, f =120 Hz,
VRIPPLE = 200 mVrms
dB
dB
dB
POUT =75 mW, R = 32Ω, A-Wtd
102
65
L
Filter
Xtalk
Channel Separation
f=1kHz, CB = 1.0 µF
Electrical Characteristics for Bridged Mode Operation
(Notes 7, 10)
The following specifications apply for VDD = 5V and TA = 25˚C unless otherwise noted.
LM4836
Units
(Limits)
Symbol
VOS
Parameter
Conditions
Typical
Limit
(Note 14)
(Note 15)
Output Offset Voltage
Output Power
VIN = 0V
10
50
mV (max)
W
PO
THD + N = 1.0%; f=1kHz; RL = 3Ω
2.2
(Note 8)
THD + N = 1.0%; f=1kHz; RL = 4Ω
2
W
(Note 9)(Note 15)
THD = 1.5% (max);f = 1 kHz;
1.1
1.0
W (min)
RL = 8Ω
THD+N = 10%;f = 1 kHz; RL = 8Ω
1.5
0.3
W
%
<
<
20 kHz,
THD+N
Total Harmonic Distortion+Noise
PO = 1W, 20 Hz
f
RL = 8Ω, AVD = 2
PO = 340 mW, RL = 32Ω
1.0
74
%
PSRR
SNR
Xtalk
Power Supply Rejection Ratio
Signal to Noise Ratio
CB = 1.0 µF, f = 120 Hz,
dB
VRIPPLE = 200 mVrms; RL = 8Ω
VDD = 5V, POUT = 1.1W, RL = 8Ω,
A-Wtd Filter
93
70
dB
dB
Channel Separation
f=1kHz, CB = 1.0 µF
2
Note 3: The θ given is for an MXA28A package whose exposed-DAP is soldered to an exposed 2in piece of 1 ounce printed circuit board copper.
JA
2
Note 4: The θ given is for an MXA28A package whose exposed-DAP is soldered to a 2in piece of 1 ounce printed circuit board copper on a bottom side layer
JA
through 21 8mil vias.
2
Note 5: The θ given is for an MXA28A package whose exposed-DAP is soldered to an exposed 1in piece of 1 ounce printed circuit board copper.
JA
Note 6: The θ given is for an MXA28A package whose exposed-DAP is not soldered to any copper.
JA
Note 7: All voltages are measured with respect to the ground pins, unless otherwise specified. All specifications are tested using the typical application as shown
in Figure 2.
Note 8: When driving 3Ω loads from a 5V supply the LM4836MTE exposed DAP must be soldered to the circuit board and forced-air cooled.
Note 9: When driving 4Ω loads from a 5V supply the LM4836MTE exposed DAP must be soldered to the circuit board.
Note 10: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 11: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
, θ , and the ambient temperature T . The maximum
JA
A
allowable power dissipation is P
DMAX
= (T
JMAX
− T )/θ . For the LM4836MT, T = 150˚C, and the typical junction-to-ambient thermal resistance, when board
JA JMAX
A
mounted, is 80˚C/W assuming the MTC28 package.
Note 12: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 13: Machine Model, 220 pF–240 pF discharged through all pins.
Note 14: Typicals are measured at 25˚C and represent the parametric norm.
Note 15: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
3
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Typical Application
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4
Truth Table for Logic Inputs (Note 16)
Mute
Mux Control
HP Sense
Inputs Selected
Left In 1, Right In 1
Left In 1, Right In 1
Left In 2, Right In 2
Left In 2, Right In 2
-
Bridged Output
Vol. Adjustable
Muted
Single-Ended Output
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
-
Vol. Adjustable
-
Vol. Adjustable
Muted
Vol. Adjustable
Muted
Muted
Note 16: If system beep is detected on the Beep in pin (pin 11) and beep is fed to inputs, the system beep will be passed through the bridged amplifier regardless
of the logic of the Mute, HP sense, or DC Volume Control pins.
Typical Performance Characteristics
MTE Specific Characteristics
LM4836MTE
THD+N vs Output Power
LM4836MTE
THD+N vs Frequency
LM4836MTE
THD+N vs Output Power
DS101088-70
DS101088-71
DS101088-72
LM4836MTE
THD+N vs Frequency
LM4836MTE
Power Dissipation vs Output Power
LM4836MTE (Note 17)
Power Derating Curve
DS101088-73
DS101088-65
DS101088-64
Note 17: These curves show the thermal dissipation ability of the LM4836MTE at different ambient temperatures given these conditions:
2
2
500LFPM + 2in : The part is soldered to a 2in , 1 oz. copper plane with 500 linear feet per minute of forced-air flow across it.
2
2
2in on bottom: The part is soldered to a 2in , 1oz. copper plane that is on the bottom side of the PC board through 21 8 mil vias.
2
2
2in : The part is soldered to a 2in , 1oz. copper plane.
2
2
1in : The part is soldered to a 1in , 1oz. copper plane.
Not Attached: The part is not soldered down and is not forced-air cooled.
5
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Non-MTE Specific Characteristics
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Output Power
DS101088-57
DS101088-15
DS101088-18
DS101088-21
DS101088-58
DS101088-16
DS101088-19
DS101088-22
DS101088-14
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Frequency
DS101088-17
DS101088-20
DS101088-24
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Non-MTE Specific Characteristics (Continued)
THD+N vs Output Power
THD+N vs Output Power
THD+N vs Output Power
DS101088-25
DS101088-27
DS101088-26
THD+N vs Output Power
THD+N vs Output Power
THD+N vs Output Power
THD+N vs Output Power
THD+N vs Output Power
DS101088-30
DS101088-29
DS101088-28
THD+N vs Output Power
THD+N vs Output Power
DS101088-31
DS101088-32
DS101088-33
THD+N vs Output Voltage
Docking Station Pins
THD+N vs Output Voltage
Docking Station Pins
DS101088-34
DS101088-59
DS101088-60
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Non-MTE Specific Characteristics (Continued)
Output Power vs
Load Resistance
Output Power vs
Load Resistance
Output Power vs
Load Resistance
DS101088-62
DS101088-6
DS101088-7
Power Supply
Rejection Ratio
Output Power vs
Load Resistance
Dropout Voltage
DS101088-53
DS101088-38
DS101088-8
Noise Floor
Noise Floor
Volume Control
Characteristics
DS101088-41
DS101088-42
DS101088-10
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Non-MTE Specific Characteristics (Continued)
Power Dissipation vs
Output Power
Power Dissipation vs
Output Power
External Gain/
Bass Boost
Characteristics
DS101088-51
DS101088-52
DS101088-61
Power Derating Curve
Crosstalk
Crosstalk
DS101088-49
DS101088-50
DS101088-63
Output Power
Output Power
Supply Current
vs Supply voltage
vs Supply Voltage
vs Supply Voltage
DS101088-54
DS101088-56
DS101088-9
9
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typical operation is not around the maximum power dissipa-
tion point, the ambient temperature can be increased. Refer
to the Typical Performance Characteristics curves for
power dissipation information for different output powers.
Application Information
EXPOSED-DAP MOUNTING CONSIDERATIONS
The exposed-DAP (die attach pad) must be tied to ground.
The exposed-DAP of the LM4836MTE requires special at-
tention to thermal design. If thermal design issues are not
properly addressed, an LM4836MTE driving 4Ω will go into
thermal shutdown.
LAYOUT
As stated in the Grounding section, placement of ground re-
turn lines is imperative in maintaining the highest level of
system performance. It is not only important to route the cor-
rect ground return lines together, but also to be aware of
where the ground return lines are routed with respect to each
other. The output load ground returns should be physically
located as far as possible from low signal level lines and their
ground return lines.
The exposed-DAP on the bottom of the LM4836MTE should
be soldered down to a copper plane on the circuit board. The
copper plane will conduct heat away from the exposed-DAP.
If the copper plane is not on the top surface of the circuit
board, 20 to 30 vias of 0.010 inches or smaller in diameter
should be used to thermally couple the exposed-DAP to the
plane. For good thermal conduction, the vias must be
plated-through and solder-filled.
3Ω and 4Ω Layout Considerations
With low impedance loads, the output power at the loads is
heavily dependent on trace resistance from the output pins
of the LM4836. Traces from the output of the LM4836MTE to
the load or load connectors should be as wide as practical.
Any resistance in the output traces will reduce the power de-
livered to the load. For example, with a 4Ω load and 0.1Ω of
trace resistance in each output, output power at the load
drops from 2W to 1.8W.
The copper plane used to conduct heat away from the
exposed-DAP should be as large as practical. If the plane is
on the same side of the circuit board as the exposed-DAP, 2
in2 is the minimum for 5V operation into 4Ω. If the heat sink
plane is buried or not on the same side as the exposed-DAP,
5in2 is the minimum for 5V operation into 4Ω. If the ambient
temperature is higher than 25˚C, a larger copper plane or
forced-air cooling may be required to keep the LM4836MTE
junction temperature below the thermal shutdown tempera-
ture (150˚C). See the power derating curve for the
LM4836MTE for derating information.
Output power is also dependent on supply regulation. To
keep the supply voltage from sagging under full output con-
ditions, the supply traces should be as wide as practical.
The LM4836MTE requires forced-air cooling when operating
into 3Ω.
Grounding
In order to achieve the best possible performance, there are
certain grounding techniques to be followed. All input refer-
ence grounds should be tied with their respective source
grounds and brought back to the power supply ground sepa-
rately from the output load ground returns. Bringing the
ground returns for the output loads back to the supply sepa-
rately will keep large signal currents from interfering with the
stable AC input ground references. The exposed-DAP of the
LM4836MTE package must be tied to ground.
POWER DISSIPATION
Power dissipation is a major concern when using any power
amplifier and must be thoroughly understood to ensure a
successful design. Equation 1 states the maximum power
dissipation point for a single-ended amplifier operating at a
given supply voltage and driving a specified load.
PDMAX = (VDD)2/(2π 2RL) (1)
However, a direct consequence of the increased power de-
livered to the load by a bridged amplifier is an increase in in-
ternal power dissipation. Equation 2 states the maximum
power dissipation point for a bridged amplifier operating at a
given supply voltage and driving a specified load.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is criti-
cal for low noise performance and high power supply rejec-
tion. The capacitor location on both the bypass and power
supply pins should be as close to the device as possible. The
effect of a larger half supply bypass capacitor is improved
PSRR due to increased half-supply stability. Typical applica-
tions employ a 5 volt regulator with 10 µF and a 0.1 µF by-
pass capacitors which aid in supply stability, but do not elimi-
nate the need for bypassing the supply nodes of the
PDMAX = 4(VDD)2/(2π 2RL) (2)
Since the LM4836 is a stereo power amplifier, the maximum
internal power dissipation is two times that of Equation 1 or
Equation 2 depending on the mode of operation. Even with
the power dissipation of the stereo amplifiers, the LM4836
does not require heatsinking. The power dissipation from the
amplifiers, must not be greater than the package power dis-
sipation that results from Equation 3:
LM4836. The selection of bypass capacitors, especially C B
,
is thus dependent upon desired PSRR requirements, de-
sired turn on time, click and pop performance as explained in
the section, Proper Selection of External Components,
system cost, and size constraints. It is also recommended to
decouple each of the VDD pins with a 0.1µF capacitor to
ground.
PDMAX = (TJMAX − TA)/ θ
(3)
JA
For the LM4836 TSSOP package, θJA = 80˚C/W and TJMAX
= 150˚C. Depending on the ambient temperature, T A, of the
system surroundings, Equation 3 can be used to find the
maximum internal power dissipation supported by the IC
packaging. If the result of Equation 1 and 2 is greater than
that of Equation 3, then either the supply voltage must be de-
creased, the load impedance increased, or the ambient tem-
perature reduced. For the typical application of a 5V power
supply, with an 8Ω bridged loads, the maximum ambient
temperature possible without violating the maximum junction
temperature is approximately 48˚C provided that device op-
eration is around the maximum power dissipation points.
Power dissipation is a function of output power and thus, if
PROPER SELECTION OF EXTERNAL COMPONENTS
Proper selection of external components in applications us-
ing integrated power amplifiers is critical to optimize device
and system performance. While the LM4836 is tolerant of
external component combinations, consideration to compo-
nent values must be used to maximize overall system qual-
ity.
The LM4836’s bridged amplifier should be used in low gain
configurations to minimize THD+N values, and maximize the
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There is a linear relationship between the size of CB and the
turn-on time. Here are some typical turn-on times for differ-
ent values of CB:
Application Information (Continued)
signal to noise ratio. Low gain configurations require large in-
put signals to obtain a given output power. Input signals
equal to or greater than 1Vrms are available from sources
such as audio codecs.
CB
TON
0.01 µF
0.1 µF
0.22 µF
0.47 µF
1.0 µF
4.7 µF
2 ms
Besides gain, one of the major considerations is the closed-
loop bandwidth of the amplifier. To a large extent, the band-
width is dictated by the choice of external components
shown in Figure 1. Both the input coupling capacitor, CI, and
the output coupling capacitor form first order high pass filters
which limit low frequency response given in Equations 4 and
5.
20 ms
42 ms
84 ms
200 ms
1sec
In order to eliminate “click and pop”, all capacitors must be
discharged before turn-on. Rapid on/off switching of the de-
vice or shutdown function may cause the “click and pop” cir-
cuitry to not operate fully, resulting in increased “click and
pop” noise.
fIC = 1/(2πRiCi) (4)
fOC = 1/(2πRLCO) (5)
These values should be chosen based on required fre-
quency response.
In systems where the line out and headphone jack are the
same, the output coupling cap, CO, is of particular concern.
CO is chosen for a desired cutoff frequency with a head-
phone load. This desired cutoff frequency will change when
the headphone load is replaced by a high impedance line out
load(powered speakers). The input impedance of head-
phones are typically between 32Ω and 64Ω. Whereas, the
input impedance of powered speakers can vary from 1kΩ to
100kΩ. As the RC time constant of the load and the output
coupling capacitor increases, the turn off transients are in-
creased.
Selection of Input and Output Capacitor Size
Large input and output capacitors are both expensive and
space hungry for portable designs. Clearly, a certain sized
capacitor is needed to couple in low frequencies without se-
vere attenuation. In many cases the speakers used in por-
table systems, whether internal or external, have little ability
to reproduce signals below 100 Hz–150 Hz. In this case, us-
ing a large input or output capacitor may not increase system
performance.
In addition to system cost and size, click and pop perfor-
mance is effected by the size of the input coupling capacitor,
Ci. A larger input coupling capacitor requires more charge to
reach its quiescent DC voltage (nominally 1/2 VDD.) This
charge comes from the output through the feedback and is
apt to create pops once the device is enabled. By minimizing
the capacitor size based on necessary low frequency re-
sponse, turn-on pops can be minimized.
To improve click and pop performance in this situation, exter-
nal resistor R7 should be added as shown in Figure 3. The
recommended value for R7 is between 150Ω to 1kΩ. To
achieve virtually clickless and popless performance R7 =
150Ω, CO = 220µF, and CB = 1.0µF should be used. Lower
values of R7 will result in better click and pop performance.
However, it should be understood that lower resistance val-
ues of R7 will increase current consumption.
CLICK AND POP CIRCUITRY
The LM4836 contains circuitry to minimize turn-on transients
or “click and pops”. In this case, turn-on refers to either
power supply turn-on or the device coming out of shutdown
mode. When the device is turning on, the amplifiers are inter-
nally muted. An internal current source ramps up the voltage
of the bypass pin. Both the inputs and outputs ideally track
the voltage at the bypass pin. The device will remain in mute
mode until the bypass pin has reached its half supply volt-
age, 1/2 VDD. As soon as the bypass node is stable, the de-
vice will become fully operational.
Although the bypass pin current source cannot be modified,
the size of the bypass capacitor, CB, can be changed to alter
the device turn-on time and the amount of “click and pop”. By
increasing CB, the amount of turn-on pop can be reduced.
However, the trade-off for using a larger bypass capacitor is
an increase in the turn-on time for the device. Reducing CB
will decrease turn-on time and increase “click and pop”.
DS101088-5
FIGURE 2. Resistor for Varying Output Loads
DOCKING STATION
In an application such as a notebook computer, docking sta-
tion or line level outputs may be required. Pin 9 and Pin 13
can drive loads greater than 1kΩ rail to rail. These pins are
tied to the output of the input op-amp to drive powered
speakers and other high impedance loads. Output coupling
capacitors need to be placed in series with the load. The rec-
ommended values of the capacitors are between 0.33µF to
1.0µF with the positive side of the capacitors toward the IC.
The outputs of the docking station pins cannot be attenuated
11
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MUTE FUNCTION
Application Information (Continued)
By placing a logic level high on the mute pin (pin5), the out-
puts of the amplifiers and pins 9 and 13 will be muted. The
beep in signal will be output even if the LM4836 is muted.
The mute pin must not be floated.
with the DC volume control. However the gain of the outputs
can be configured by adjusting the feedback and input resis-
tors for the input op-amp. The input op-amp is in an inverting
configuration where the gain is:
HP SENSE FUNCTION
RF / Ri = - Av
The LM4836 possesses a headphone sense pin (pin 21) that
mutes the bridged amplifier, when given a logic high, so that
headphone or line out operation can occur while the bridged
connected load will be muted.
Note that by adjusting the gain of the input op-amp the over-
all gain of the output amplifiers are also affected. Although
the single ended outputs of the output amplifiers can be used
to drive line level outputs, it is recommended to use Pins 9
and 13 to achieve better performance.
Figure 3 shows the implementation of the LM4836’s head-
phone control function using a single-supply. The voltage di-
vider of R1 and R2 set the voltage at the HP sense pin (pin
21) to be approximately 50 mV when there are no head-
phones plugged into the system. This logic-low voltage at
the HP sense pin enables the bridged power amplifiers. Re-
sistor R4 limits the amount of current flowing out of the HP
sense pin when the voltage at that pin goes below ground re-
sulting from the music coming from the headphone amplifier.
Since the threshold of the HP sense pin is set at 4V ( or 80%
MUX CONTROL
The LM4836 contains two pairs of inputs. The Mux Contol
pin controls wihch set of inputs are selected. Left In 1 and
Right In 1 are selected when Pin 2 is given a logic level low.
Left In 2 and Right In 2 are selected whenever a logic level
high is placed on Pin 2.
BEEP DETECT FUNCTION
V
DD), the output swing cannot cause false triggering.
The Beep Detect pin (pin 11) is a mono input that detects the
presence of a beep signal. When a signal greater than
2.5VP-P (or 1/2 VDD) is present at pin 11, the Beep Detect cir-
cuitry will enable the bridged amplifiers. Beep in signals less
than 2.5VP-P (or 1/2 VDD) will not trigger the Beep Detect cir-
cuitry. When triggered, the Beep Detect circuitry will enable
the bridged amplifiers regardless of the state of the Mute,
Volume Control, or HP sense pins. The Beep Detect pin will
not pass the beep signal to the output. As shown in the Fig.
2, a 200kΩ resistor is placed in series with the input capaci-
tor. This 200kΩ resistor can be changed to vary the ampli-
tude of the beep in signal. Higher values of the resistor will
reduce the amplifier gain and attenuate the beep in signal.
These resistors are required in order for the beep signal to
pass to the output. In cases where system beeps are re-
When a set of headphones are plugged into the system, the
contact pin of the headphone jack is disconnected from the
signal pin, interrupting the voltage divider set up by resistors
R1 and R2. Resistor R1 then pulls up the HP sense pin, en-
abling the headphone function and disabling the bridged am-
plifier. The headphone amplifier then drives the headphones,
whose impedance is in parallel with resistor R2 and R3. Also
shown in Figure 3 are the electrical connections for the
headphone jack and plug. A 3-wire plug consists of a Tip,
Ring and Sleeve, where the Tip and Ring are signal carrying
conductors and the Sleeve is the common ground return.
One control pin contact for each headphone jack is sufficient
to indicate that the user has inserted a plug into a jack and
that another mode of operation is desired.
quired when the system is in
LM4836 must be brought out of shutdown before the beep in
signal is input.
a suspended mode, the
The LM4836 can be used to drive both a bridged 8Ω internal
speaker and a pair of 32Ω speakers without using the HP
sense circuit. In this case the HP sense is controlled by a mi-
croprocessor or a switch.
SHUTDOWN FUNCTION
In order to reduce power consumption while not in use, the
LM4836 contains a shutdown pin to externally turn off the
bias circuitry. The LM4836 will shutdown when a logic high is
placed on the shutdown pin. The trigger point between a
logic low and logic high level is typically half supply. It is best
to switch between ground and the supply VDD to provide
maximum device performance. By switching the shutdown
pin to VDD, the LM4836 supply current draw will be mini-
mized. While the device will be disabled with shutdown pin
voltages less than VDD, the idle current may be greater than
the typical value of 0.2 µA.The shutdown pin should not be
floated, since this may result in an undetermined state.
In many applications, a microcontroller or microprocessor
output is used to control the shutdown circuitry which pro-
vides a quick, smooth transition into shutdown. Another solu-
tion is to use a single-pole, single-throw switch in conjuction
with an external pull-up resistor. When the switch is
closed,the shutdown pin is connected to ground and enables
the amplifier. If the switch is open, then the external pull-up
resistor will shutdown the LM4836. This scheme prevents
the shutdown pin from floating.
DS101088-4
FIGURE 3. Headphone Sensing Circuit
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12
The resulting low frequency differential gain of this bridged
amplifier becomes:
Application Information (Continued)
BASS BOOST FUNCTION
2(10kΩ +10kΩ) /10kΩ = 4
The Bass Boost Function can be toggled by changing the
logic at pin 19. A logic low will switch the power amplifiers to
bass boost mode. In bass boost mode the low frequency
gain of the amplifier is set by the external capacitor.
Whereas a logic high sets the amplifiers to unity gain.
With CBASS = 0.1 µF, a first order pole is formed with a corner
frequency of 160 Hz. The low frequency boost formulas as-
sume that CO, Ci, fIC, fOC allow the appropriate low fre-
quency response as explained in the Proper Selection of
External Components section. See the Typical Perfor-
mance Characteristics section for a graph that includes
In some cases a designer may want to improve the low fre-
quency response of the bridged amplifier or incorporate a
bass boost feature. This bass boost can be useful in systems
where speakers are housed in small enclosures. If the de-
signer wishes to disable the bass boost feature, pin 19 can
bass boost performance with various values of CBASS
.
DC VOLUME CONTROL
The DC voltage at the DC Volume Control pin (pin 5) deter-
mines the attenuation of output of the amplifiers. If the DC
potential of pin 5 is above 4V (typical 80% VDD) the internal
amplifiers are set at unity gain. The attenuator range is from
0 dB (pin 5 = 80% VDD) to -81 dB (pin 5 = 0V). Any DC volt-
age greater than 4V (or 80% VDD) will result in a gain of
unity. Refer to the Typical Performance Characteristics for
detailed information of the attenuation characteristics of the
DC Volume Control pin.
be tied to VDD
.
When bass boost is enabled, the output amplifiers will be in-
ternally set at a gain of 2 at low frequencies (gain of 4 in
bridged mode). As shown in Figure 2, CBASS sets the cutoff
frequency for the bass boost. At low frequencies the capaci-
tor will be virtually an open circuit. At high frequencies the ca-
pacitor will be virtually a short circuit. As a result of this, the
gain of the bridge amplifier is increased at low frequencies. A
first order pole is formed with a corner frequency at:
fc = 1/(2π10kΩCBASS
)
13
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Physical Dimensions inches (millimeters) unless otherwise noted
TSSOP Package
Order Number LM4836MT
NS Package Number MTC28 for TSSOP
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14
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Exposed-DAP TSSOP Package
Order Number LM4836MTE
NS Package Number MXA28A for Exposed-DAP TSSOP
15
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Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Tel: 1-800-272-9959
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Email: support@nsc.com
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