LM4857SP [NSC]
Stereo 1.2W Audio Sub-system with 3D Enhancement; 1.2W立体声音频子系统与3D增强
| 型号： | LM4857SP |
| 厂家： | 
National Semiconductor |
| 描述： | Stereo 1.2W Audio Sub-system with 3D Enhancement |
| 文件： | 总38页 (文件大小：1511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2004
LM4857
Stereo 1.2W Audio Sub-system with 3D Enhancement
General Description
Key Specifications
The LM4857 is an integrated audio sub-system designed for
stereo cell phone applications. Operating on a 3.3V supply, it
combines a stereo speaker amplifier delivering 495mW per
channel into an 8Ω load, a stereo headphone amplifier de-
livering 33mW per channel into a 32Ω load, a mono earpiece
amplifier delivering 43mW into a 32Ω load, and a line output
for an external powered handsfree speaker. It integrates the
audio amplifiers, volume control, mixer, power management
control, and National 3D enhancement all into a single pack-
age. In addition, the LM4857 routes and mixes the stereo
and mono inputs into 16 distinct output modes. The LM4857
is controlled through an I2C compatible interface. Other fea-
tures include an ultra-low current shutdown mode and ther-
mal shutdown protection.
j
POUT, Stereo Loudspeakers, 4Ω, 5V,
1% THD+N (LM4857SP)
1.6W (typ)
1.2W (typ)
j
POUT, Stereo Loudspeakers, 8Ω, 5V,
1% THD+N
j
POUT, Stereo Headphones, 32Ω, 5V,
1% THD+N
75mW (typ)
100mW (typ)
495mW (typ)
33mW (typ)
j
POUT, Mono Earpiece, 32Ω, 5V,
1% THD+N
j
POUT, Stereo Loudspeakers, 8Ω, 3.3V,
1% THD+N
j
POUT, Stereo Headphones, 32Ω, 3.3V,
1% THD+N
Boomer audio power amplifiers are designed specifically to
provide high quality output power with a minimal amount of
external components.
j
POUT, Mono Earpiece, 32Ω, 3.3V,
1% THD+N
43mW (typ)
0.06µA (typ)
The LM4857 is available in a 30-bump ITL package and a
28–lead LLP package.
j
Shutdown Current
Features
n Stereo speaker amplifier
n Stereo headphone amplifier
n Mono earpiece amplifier
n Mono Line Output for external handsfree carkit
n Independent Left, Right, and Mono volume controls
n National 3D enhancement
n I2C compatible interface
n Ultra low shutdown current
n Click and Pop Suppression circuit
n 16 distinct output modes
n Thermal Shutdown Protection
n Available in micro SMD and LLP packages
Applications
n Cell Phones
n PDAs
n Portable Gaming Devices
n Internet Appliances
n Portable DVD/CD/AAC/MP3 players
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation
DS200797
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Typical Application
20079708
FIGURE 1. Typical Audio Amplifier Application Circuit
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2
Connection Diagrams
30 Bump ITL Package
micro SMD Marking
200797I3
Top View
X — Date Code
T — Die Traceability
G — Boomer Family
C2 — LM4857ITL
200797A9
Top View
(Bump-side down)
Order Number LM4857ITL
See NS Package Number TLA30CZA
Pin Connection (ITL)
Pin
Name
Pin Description
Right Loudspeaker Positive Output
Power Supply
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
F1
F2
F3
F4
F5
RLS+
VDD
SDA
Data
RHP3D
RHP
GND
I2CVDD
ADR
LHP3D
VDD
Right Headphone 3D
Right Headphone Output
Ground
I2C Interface Power Supply
I2C Address Select
Left Headphone 3D
Power Supply
RLS-
NC
Right Loudspeaker Negative Output
No Connect
SCL
Clock
LINEOUT
GND
LLS-
VDD
Mono Line Output
Ground
Left Loudspeaker Negative Output
Power Supply
MIN
Mono Input
NC
No Connect
EP+
Mono Earpiece Positive Output
Ground
GND
BYPASS
LLS3D
RIN
Half-supply bypass
Left Loudspeaker 3D
Right Stereo Input
Mono Earpiece Negative Output
Left Loudspeaker Positive Output
Power Supply
EP-
LLS+
VDD
RLS3D
LIN
Right Loudspeaker 3D
Left Stereo Input
LHP
Left Headphone Output
3
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Connection Diagrams
49 Bump GR Package
micro Array Marking
200797I3
Top View
X — Date Code
T — Die Traceability
G — Boomer Family
B6 — LM4857GR
200797I4
Top View
(Bump-side down)
Order Number LM4857GR
See NS Package Number GRA49A
(available soon)
Pin Connection (GR)
Pin
Name
Pin Description
A1
NC
No Connect
A2
LHP3D
SCL
Left Headphone 3D
A3
Clock
A4
ADR
I2CVDD
RLS-
RLS-
RHP
NC
I2C Address Select
I2C Interface Power Supply
Right Loudspeaker Negative Output
Right Loudspeaker Negative Output
Right Headphone Output
No Connect
A5
A6
A7
B1
B2
B3
RHP3D
SDA
Right Headphone 3D
Data
B4
B5
VDD
GND
GND
LINEOUT
VDD
NC
Power Supply
B6
Ground
B7
Ground
C1
Mono Line Output
C2
Power Supply
C3, C4, C5
C6
No Connect
RLS+
RLS+
GND
NC
Right Loudspeaker Positive Output
Right Loudspeaker Positive Output
Ground
C7
D1
D2, D3, D4, D5
No Connect
D6
D7
E1
E2
LLS+
VDD
EP-
Left Loudspeaker Positive Output
Power Supply
Mono Earpiece Negative Output
Mono Earpiece Positive Output
EP+
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4
Pin Connection (GR) (Continued)
E3, E4, E5
NC
No Connect
E6
GND
LLS+
LHP
NC
Ground
E7
Left Loudspeaker Positive Output
Left Headphone Output
No Connect
F1
F2
F3
LIN
Left Stereo Input
Left Loudspeaker 3D
Power Supply
F4
LLS3D
VDD
LLS-
GND
NC
F5
F6
Left Loudspeaker Negative Output
Ground
F7
G1
G2
G3
G4
G5
G6
G7
No Connect
RIN
Right Stereo Input
Mono Input
MIN
RLS3D
BYPASS
NC
Right Loudspeaker 3D
Half-supply bypass
No Connect
LLS-
Left Loudspeaker Negative Output
Connection Diagram
28 – Lead SP Package
20079799
Top View
Order Number LM4857SP
See NS Package Number SPA28A
5
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Pin Connection (SP)
Pin
Name
RHP
Pin Description
Right Headphone Output
Power Supply
1
2
VDD
3
LINEOUT
GND
EP-
Mono Line Output
4
Ground
5
Mono Earpiece Negative Output
Mono Earpiece Positive Output
Left Headphone Output
Right Stereo Input
Left Stereo Input
6
EP+
7
LHP
8
RIN
9
LIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MIN
Mono Input
LLS3D
RLS3D
BYPASS
VDD
Left Loudspeaker 3D
Right Loudspeaker 3D
Half-supply bypass
Power Supply
LLS+
GND
LLS-
Left Loudspeaker Positive Output
Ground
Leftt Loudspeaker Negative Output
Power Supply
VDD
RLS-
GND
RLS+
VDD
Right Loudspeaker Negative Output
Ground
Right Loudspeaker Positive Output
Power Supply
I2CVDD
I2C Interface Power Supply
Data
I2C Address Select
SDA
ADR
SCL
Clock
RHP3D
LHP3D
Right Headphone 3D
Left Headphone 3D
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6
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
θJA (TLA30CZA) (Note 10)
θJA (SPA28A) (Note 12)
θJC (SPA28A)
62˚C/W
42˚C/W
3˚C/W
Supply Voltage
Storage Temperature
Input Voltage
6.0V
−65˚C to +150˚C
−0.3V to VDD
+0.3V
Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX
Supply Voltage
−40˚C ≤ TA ≤ +85˚C
Power Dissipation (Note 3)
ESD Susceptibility (Note 4)
ESD Susceptibility (Note 5)
Junction Temperature (TJ)
Thermal Resistance
Internally Limited
2000V
2.7V ≤ VDD ≤ 5.5V
2.5V ≤ I2CVDD ≤ 5.5V
200V
150˚C
Audio Amplifier Electrical Characteristics VDD = 5.0V (Notes 1, 2)
The following specifications apply for VDD = 5.0V, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4857
Units
(Limits)
Typical Limits (Notes
(Note 6)
7, 8)
VIN = 0V, No load;
LD5 = RD5 = 0 (Note 9)
Mode 1, 6, 11
6
5
9.5
8
mA (max)
mA (max)
mA (max)
µA (max)
IDD
Supply Current
Mode 4, 5, 9, 10, 14, 15
Mode 2, 3, 7, 8, 12, 13
Output mode 0 (Note 9)
LM4857SP
13
0.2
21
3
ISD
Shutdown Current
Speaker; THD+N = 1%;
f = 1kHz; 4Ω BTL
1.6
W
Speaker; THD+N = 1%;
f = 1kHz; 8Ω BTL
1.2
75
0.9
60
80
W (min)
mW (min)
mW (min)
mW
Headphone; THD+N = 1%;
f = 1kHz; 32Ω SE
PO
Output Power
Earpiece; THD+N = 1%;
f = 1kHz; 32Ω BTL, CD4 = 0
Earpiece; THD+N = 1%;
f = 1kHz; 32Ω BTL, CD4 = 1
LD5 = RD5 = 0
100
135
Speaker; PO= 400mW;
f = 1kHz; 8Ω BTL
0.05
0.04
%
%
%
%
Headphone; PO= 15mW;
f = 1kHz; 32Ω SE
Total Harmonic Distortion Plus
Noise
THD+N
Earpiece; PO= 15mW;
f = 1kHz; 32Ω BTL, CD4 = 0
0.05
Line Out, VO= 1VRMS
;
0.009
f = 1kHz; 5kΩ SE
Speaker; LD5 = RD5 = 0
Earpiece; LD5 = RD5 = 0
5
5
40
30
mV (max)
mV (max)
VOS
Offset Voltage
7
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Audio Amplifier Electrical Characteristics VDD = 5.0V (Notes 1, 2) (Continued)
The following specifications apply for VDD = 5.0V, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4857
Units
(Limits)
Typical Limits (Notes
(Note 6)
7, 8)
A-weighted, 0dB gain; (Note 11)
LD5 = RD5 = 0; Audio Inputs Terminated
Speaker; Mode 2, 3, 7, 8
Speaker; Mode 12, 13
Headphone; Mode 3, 4, 8, 9
Headphone; Mode 13, 14
Earpiece; Mode 1; CD4 = 0
Earpiece; Mode 6
27
38
10
14
13
18
21
11
14
17
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
NOUT
Output Noise
Earpiece; Mode 11
Line Out; Mode 5
Line Out; Mode 10
Line Out; Mode 15
f = 217Hz; Vrip = 200mVpp; CB = 2.2µF;
0dB gain; (Note 11)
LD5 = RD5 = 0; Audio Inputs Terminated
Speaker; Mode 2, 3, 7, 8
Speaker; Mode 12, 13,
Headphone; Mode 3, 4, 8, 9
Headphone; Mode 13, 14
Earpiece; Mode1
70
64
86
73
75
70
66
86
74
68
dB
dB (min)
dB
54
60
dB (min)
dB
PSRR
Power Supply Rejection Ratio
Earpiece; Mode 6
dB
Earpiece; Mode 11
57
57
dB (min)
dB
Line Out; Mode 5
Line Out; Mode 10
dB
Line Out; Mode 15
dB (min)
LD5 = RD5 = 0
Loudspeaker; PO= 400mW;
f = 1kHz
85
85
dB
dB
Xtalk
TWU
Crosstalk
Headphone; PO= 15mW;
f = 1kHz
CD5 = 0; CB = 2.2µF
CD5 = 1; CB = 2.2µF
120
230
ms
ms
Wake-up Time
Audio Amplifier Electrical Characteristics VDD = 3.0V (Notes 1, 2)
The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4857
Units
(Limits)
Typical Limits (Notes
(Note 6)
7, 8)
VIN = 0V, No load;
LD5 = RD5 = 0 (Note 9)
Mode 1, 6, 11
5.5
4.5
9
mA (max)
mA (max)
mA (max)
µA (max)
IDD
Supply Current
Mode 4, 5, 9, 10, 14, 15
Mode 2, 3, 7, 8, 12, 13
Mode 0 (Note 9)
7.5
19
2.5
11.2
0.06
ISD
PO
Shutdown Current
Output Power
LM4857SP
Speaker; THD+N = 1%;
f = 1kHz; 4Ω BTL
530
mW
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8
Audio Amplifier Electrical Characteristics VDD = 3.0V (Notes 1, 2) (Continued)
The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4857
Units
(Limits)
Typical Limits (Notes
(Note 6)
7, 8)
Speaker; THD+N = 1%;
400
320
mW (min)
mW (min)
mW (min)
mW
f = 1kHz; 8Ω BTL
Headphone; THD+N = 1%;
f = 1kHz; 32Ω SE
25
30
30
20
22
PO
Output Power
Earpiece; THD+N = 1%;
f = 1kHz; 32Ω BTL; CD4 = 0
Earpiece; THD+N = 1%;
f = 1kHz; 32Ω BTL; CD4 = 1
LD5 = RD5 = 0
Speaker; PO= 200mW;
f = 1kHz; 8Ω BTL
0.05
0.04
%
%
%
%
Headphone; PO= 10mW;
f = 1kHz; 32Ω SE
Total Harmonic Distortion Plus
Noise
THD+N
Earpiece; PO=10mW;
f = 1kHz; 32Ω BTL; CD4 = 0
0.06
Line Out; VO= 1VRMS
;
0.015
f = 1kHz; 5kΩ SE
Speaker; LD5 = RD5 = 0
Earpiece; LD5 = RD5 = 0
A-weighted; 0dB gain; (Note 11)
LD5 = RD5 = 0; All Inputs Terminated
Speaker; Mode 2, 3, 7, 8
Speaker; Mode 12, 13
Headphone; Mode 3, 4, 8, 9
Headphone; Mode 13, 14
Earpiece; Mode 1
5
5
40
30
mV (max)
mV (max)
VOS
Offset Voltage
27
38
10
14
13
18
21
11
14
17
µV
µV
µV
µV
µV
µV
µV
µV
µV
µV
NOUT
Output Noise
Earpiece; Mode 6
Earpiece; Mode 11
Line Out; Mode 5
Line Out; Mode 10
Line Out; Mode 15
f = 217Hz, Vrip = 200mVpp; CB = 2.2µF;
0dB gain; (Note 11)
LD5 = RD5 = 0; All Audio Inputs
Terminated
Speaker; Mode 2, 3, 7, 8
Speaker; Mode 12, 13,
Headphone; Mode 3, 4, 8, 9
Headphone; Mode 13, 14
Earpiece; Mode1
70
65
87
75
76
70
67
88
74
71
dB
dB (min)
dB
55
62
PSRR
Power Supply Rejection Ratio
dB (min)
dB
Earpiece; Mode 6
dB
Earpiece; Mode 11
57
58
dB (min)
dB
Line Out; Mode 5
Line Out; Mode 10
dB
Line Out; Mode 15
dB (min)
9
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Audio Amplifier Electrical Characteristics VDD = 3.0V (Notes 1, 2) (Continued)
The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4857
Units
(Limits)
Typical Limits (Notes
(Note 6)
7, 8)
LD5 = RD5 = 0
Loudspeaker; PO= 200mW;
f = 1kHz
82
82
dB
dB
Xtalk
TWU
Crosstalk
Headphone; PO= 10mW;
f = 1kHz
CD5 = 0; CB = 2.2µF
CD5 = 1; CB = 2.2µF
80
ms
ms
Wake-up Time
140
Volume Control Electrical Characteristics (Notes 1, 2)
The following specifications apply for VDD = 5.0V and VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4857
Units
(Limits)
Typical Limits (Notes
(Note 6)
6
7, 8)
5.5
maximum gain setting
dB (min)
dB (max)
dB (min)
dB (max)
dB (min)
dB (max)
dB (min)
dB (max)
dB
6.5
Stereo Volume Control Range
Mono Volume Control Range
minimum gain setting
maximum gain setting
minimum gain setting
-40.5
12
-41
-40
11.5
12.5
-35
-34.5
-34
Volume Control Step Size
Volume Control Step Size
Error
1.5
+/-0.2
+/-0.5
dB (max)
Stereo Channel to Channel
Gain Mismatch
0.3
dB
Mode 12, Vin = 1VRMS
Headphone
Mute Attenuation
85
85
dB
Line Out
dB
maximum gain setting
33.5
25
42
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
LIN and RIN Input Impedance
minimum gain setting
maximum gain setting
minimum gain setting
100
20
75
125
15
M
IN Input Impedance
25
98
73
123
Control Interface Electrical Characteristics (Notes 1, 2)
The following specifications apply for VDD = 5V and VDD = 3V and 2.5V ≤ I2CVDD ≤ 5.5V, unless otherwise specified. Limits
apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4857
Units
(Limits)
Typical Limits (Notes
(Note 6)
7, 8)
2.5
100
0
t1
SCL period
µs (min)
ns (min)
ns (min)
ns (min)
t2
t3
t4
SDA Set-up Time
SDA Stable Time
Start Condition Time
100
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10
Control Interface Electrical Characteristics (Notes 1, 2) (Continued)
The following specifications apply for VDD = 5V and VDD = 3V and 2.5V ≤ I2CVDD ≤ 5.5V, unless otherwise specified. Limits
apply for TA = 25˚C.
Symbol
Parameter
Conditions
LM4857
Units
(Limits)
Typical Limits (Notes
(Note 6)
7, 8)
t5
Stop Condition time
100
ns (min)
V (min)
V (max)
VIH
VIL
Digital Input High Voltage
Digital Input Low Voltage
0.7 x I2CVDD
0.3 x I2CVDD
Note 1: All voltages are measured with respect to the GND pin unless otherwise specified.
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
, θ , and the ambient temperature, T . The maximum
A
JMAX JA
allowable power dissipation is P
= (T
- T ) / θ or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4857 operating in Mode
DMAX
JMAX A JA
3, 8, or 13 with V
= 5V, 8Ω stereo loudspeakers and 32Ω stereo headphones, the total power dissipation is 1.348W. θ = 62˚C/W.
DD
JA
Note 4: Human body model, 100pF discharged through a 1.5kΩ resistor.
Note 5: Machine Model, 220pF-240pF discharged through all pins.
Note 6: Typicals are measured at +25˚C and represent the parametric norm.
Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
2
Note 9: Shutdown current and supply current are measured in a normal room environment. All digital input pins are connected to I CV
.
DD
2
Note 10: The given θ is for an LM4857ITL mounted on a PCB with a 2in area of 1oz printed circuit board copper ground plane.
JA
Note 11: “0dB gain” refers to the volume control gain setting of M , L , and R set at 0dB.
IN IN
IN
2
Note 12: The given θ is for an LM4857SP mounted on a PCB with a 2in area of 10z printed circuit board ground plane.
A
11
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External Components Description
Components
Functional Description
1.
CIN
This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the
amplifier’s input terminals. CIN also creates a highpass filter with the internal resistor Ri (Input
Impedance) at fc = 1/(2πRiCIN).
2.
3.
4.
5.
6.
CS
CB
This is the supply bypass capacitor. It filters the supply voltage applied to the VDD pin and helps
reduce the noise at the VDD pin.
This is the BYPASS pin capacitor. It filters the VDD / 2 voltage and helps maintain the LM4857’s
PSRR.
COUT
R3D
C3D
This is the output coupling capacitor. It blocks the DC voltage and couples the output signal to the
speaker load RL. COUT also creates a high pass filter with RL at fO = 1/(2πRLCOUT).
This resistor sets the gain of the National 3D effect. Please refer to the National 3D Enhancement
section for information on selecting the value of R3D
.
This capacitor sets the frequency at which the National 3D effect starts to occur. Please refer to the
National 3D Enhancement section for information on selecting the value of C3D
.
Typical Performance Characteristics (Note 11)
LM4857SP THD+N vs Frequency
LM4857SP THD+N vs Frequency
20079755
VDD = 5V; LLS, RLS; PO = 400mW;
RL = 4Ω; Mode 7; 0dB Gain
20079756
VDD = 3V; LLS, RLS; PO = 200mW;
RL = 4Ω; Mode 7; 0dB Gain
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Typical Performance Characteristics (Note 11) (Continued)
LM4857SP THD+N vs Output Power
LM4857SP THD+N vs Output Power
20079757
20079758
VDD = 5V; LLS, RLS; f = 1kHz;
VDD = 3V; LLS, RLS; f = 1kHz;
RL = 4Ω; Mode 7; 0dB Gain
RL = 4Ω; Mode 7; 0dB Gain
THD+N vs Frequency
THD+N vs Frequency
20079710
20079711
VDD = 5V; LLS, RLS; PO = 400mW;
VDD = 3V; LLS, RLS; PO = 200mW;
RL = 8Ω; Mode 7; 0dB Gain
RL = 8Ω; Mode 7; 0dB Gain
13
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Typical Performance Characteristics (Note 11) (Continued)
THD+N vs Frequency
THD+N vs Frequency
20079712
20079713
VDD = 5V; LHP, RHP; PO = 15mW;
VDD = 3V; LHP, RHP; PO = 10mW;
RL = 32Ω; Mode 9; 0dB Gain
RL = 32Ω; Mode 9; 0dB Gain
THD+N vs Frequency
THD+N vs Frequency
20079714
20079715
VDD = 5V; EP; PO = 15mW;
VDD = 3V; EP; PO = 10mW;
RL = 32Ω; Mode 1; 0dB Gain, CD4 = 0
RL = 32Ω; Mode 1; 0dB Gain, CD4 = 0
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Typical Performance Characteristics (Note 11) (Continued)
THD+N vs Frequency
THD+N vs Frequency
20079716
20079717
VDD = 5V; LINEOUT; VO = 1VRMS
;
VDD = 3V; LINEOUT; VO = 1VRMS;
RL = 5kΩ; Mode 5; 0dB Gain
RL = 5kΩ; Mode 5; 0dB Gain
THD+N vs Frequency
THD+N vs Frequency
20079718
20079719
VDD = 5V; LINEOUT; VO = 1VRMS
;
VDD = 3V; LINEOUT; VO = 1VRMS;
RL = 5kΩ; Mode 10; 0dB Gain
RL = 5kΩ; Mode 10; 0dB Gain
15
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Typical Performance Characteristics (Note 11) (Continued)
THD+N vs Output Power
THD+N vs Output Power
20079720
20079721
VDD = 5V; LLS, RLS; f = 1kHz;
VDD = 3V; LLS, RLS; f = 1kHz;
RL = 8Ω; Mode 7; 0dB Gain
RL = 8Ω; Mode 7; 0dB Gain
THD+N vs Output Power
THD+N vs Output Power
20079722
20079723
VDD = 5V; LHP, RHP; f = 1kHz;
VDD = 3V; LHP, RHP; f = 1kHz;
RL = 32Ω; Mode 9; 0dB Gain
RL = 32Ω; Mode 9; 0dB Gain
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16
Typical Performance Characteristics (Note 11) (Continued)
THD+N vs Output Power
THD+N vs Output Power
20079724
20079725
VDD = 5V; EP; f = 1kHz; RL = 32Ω;
Mode 1; 0dB Gain; Top-CD4 = 1; Bot-CD4 = 0
VDD = 3V; EP; f = 1kHz;
RL = 32Ω; Mode 1; 0dB Gain
PSRR vs Frequency
PSRR vs Frequency
20079726
20079727
VDD = 5V; LLS, RLS; RL = 8Ω; 0db Gain;
All audio inputs terminated
VDD = 3V; LLS, RLS; RL = 8Ω; 0db Gain;
All audio inputs terminated
Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8
Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8
17
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Typical Performance Characteristics (Note 11) (Continued)
PSRR vs Frequency
PSRR vs Frequency
20079728
20079729
VDD = 5V; LHP, RHP; RL = 32Ω; 0db Gain;
All audio inputs terminated
VDD = 3V; LHP, RHP; RL = 32Ω; 0db Gain;
All audio inputs terminated
Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9
Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9
PSRR vs Frequency
PSRR vs Frequency
20079730
VDD = 5V; EP; RL = 32Ω; 0db Gain;
All audio inputs terminated
20079731
VDD = 3V; EP; RL = 32Ω; 0db Gain;
All audio inputs terminated
Top-Mode 11; Mid-Mode 6; Bot-Mode 1
Top-Mode 11; Mid-Mode 6; Bot-Mode 1
www.national.com
18
Typical Performance Characteristics (Note 11) (Continued)
PSRR vs Frequency
PSRR vs Frequency
20079732
20079733
VDD = 5V; LINEOUT; RL = 5kΩ; 0db Gain;
All audio inputs terminated
VDD = 3V; LINEOUT; RL = 5kΩ; 0db Gain;
All audio inputs terminated
Top-Mode 15; Mid-Mode 10; Bot-Mode 5
Top-Mode 15; Mid-Mode 10; Bot-Mode 5
Crosstalk vs Frequency
Crosstalk vs Frequency
20079734
20079735
VDD = 5V; LLS, RLS; PO = 400mW; RL = 8Ω;
Mode 7; 0db Gain; 3D off
VDD = 3V; LLS, RLS; PO = 200mW; RL = 8Ω;
Mode 7; 0db Gain; 3D off
Top-Left to Right; Bot- Right to Left
Top-Left to Right; Bot- Right to Left
19
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Typical Performance Characteristics (Note 11) (Continued)
Crosstalk vs Frequency
Crosstalk vs Frequency
20079736
20079737
VDD = 5V; LHP, RHP; PO = 15mW; RL = 32Ω;
Mode 9; 0db Gain; 3D off
VDD = 3V; LHP, RHP; PO = 10mW; RL = 32Ω;
Mode 9; 0db Gain; 3D off
Top-Left to Right; Bot- Right to Left
Top-Left to Right; Bot- Right to Left
Frequency vs Response
Frequency vs Response
20079739
LLS, RLS; RL = 8Ω;
Mode 7; Full Gain
20079738
LLS, RLS; RL = 8Ω;
Mode 2; Full Gain
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20
Typical Performance Characteristics (Note 11) (Continued)
Frequency vs Response
Frequency vs Response
20079740
20079741
LHP, RHP; RL = 32Ω; CO = 100µF
LHP, RHP; RL = 32Ω; CO = 100µF
Mode 4; Full Gain
Mode 9; Full Gain
Frequency vs Response
Frequency vs Response
20079742
20079743
EP; RL = 32Ω; Mode 1; Full Gain
LINEOUT; RL = 5kΩ; CO = 2.2µF
Top-CD4 = 1; Bot-CD4 = 0
Mode 5; Full Gain
21
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Typical Performance Characteristics (Note 11) (Continued)
Frequency vs Response
Power Dissipation vs Output Power
20079745
20079744
LLS, RLS; RL = 8Ω; THD+N ≤ 1%
Top-VDD = 5V; Bot-VDD = 3V
per channel
LINEOUT; RL = 5kΩ; CO = 2.2µF
Mode 10; Full Gain
Power Dissipation vs Output Power
Power Dissipation vs Output Power
20079746
20079747
LHP, RHP; RL = 32Ω; THD+N ≤ 1%
Top-VDD = 5V; Bot-VDD = 3V
per channel
EP; RL = 32Ω; THD+N ≤ 1%
Top-VDD = 5V; Bot-VDD = 3V
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22
Typical Performance Characteristics (Note 11) (Continued)
Output Power vs Load Resistance
Output Power vs Load Resistance
20079748
20079749
LLS, RLS; RL = 8Ω;
LHP, RHP; RL = 32Ω;
Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N; Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N;
Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N
Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N
Output Power vs Load Resistance
Output Power vs Load Resistance
20079750
20079751
EP; RL = 32Ω; CD4 = 0
EP; RL = 32Ω; CD4 = 1
Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N; Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N;
Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N
Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N
23
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Typical Performance Characteristics (Note 11) (Continued)
Output Power vs Supply Voltage
Output Power vs Supply Voltage
20079752
20079753
LLS, RLS; RL = 8Ω;
Top–10% THD+N; Bot–1% THD+N
LHP, RHP; RL = 32Ω;
Top–10% THD+N; Bot–1% THD+N
Output Power vs Supply Voltage
20079754
EP; RL = 32Ω;
Top–10% THD+N; CD4 = 1; Topmid–1% THD+N, CD4 = 1
Botmid–10% THD+N; CD4 = 0; Bot–1% THD+N, CD4 = 0
www.national.com
24
Application Information
200797F5
FIGURE 2. I2C Bus Format
200797F4
FIGURE 3. I2C Timing Diagram
TABLE 1. Chip Address
A7
1
A6
1
A5
1
A4
1
A3
1
A2
0
A1
EC
0
A0
0
Chip Address
ADR = 0
1
1
1
1
1
0
0
ADR = 1
1
1
1
1
1
0
1
0
EC - externally configured by ADR pin
TABLE 2. Control Registers
D7
0
D6
0
D5
0
D4
D3
D2
D1
D0
Mono Volume control
Left Volume control
Right Volume control
Mode control
MD4
LD4
RD4
CD4
MD3
LD3
RD3
CD3
MD2
LD2
RD2
CD2
MD1
LD1
RD1
CD1
MD0
LD0
RD0
CD0
0
1
LD5
RD5
CD5
1
0
1
1
25
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Application Information (Continued)
TABLE 3. Mono Volume Control
MD4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MD3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Gain (dB)
-34.5
-33.0
-31.5
-30.0
-28.5
-27.0
-25.5
-24.0
-22.5
-21.0
-19.5
-18.0
-16.5
-15.0
-13.5
-12.0
-10.5
-9.0
-7.5
-6.0
-4.5
-3.0
-1.5
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
www.national.com
26
Application Information (Continued)
TABLE 4. Stereo Volume Control
LD4//RD4
LD3//RD3
LD2//RD2
LD1//RD1
LD0//RD0
Gain (dB)
-40.5
-39.0
-37.5
-36.0
-34.5
-33.0
-31.5
-30.0
-28.5
-27.0
-25.5
-24.0
-22.5
-21.0
-19.5
-18.0
-16.5
-15.0
-13.5
-12.0
-10.5
-9.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-7.5
-6.0
-4.5
-3.0
-1.5
0.0
1.5
3.0
4.5
6.0
27
www.national.com
Application Information (Continued)
TABLE 5. Mixer and Output Mode Control
Mode CD3 CD2 CD1 CD0
Mono
Line Out
Mono Earpiece
(CD4 = 0) (CD4 =
1)
Loudspeaker Loudspeaker Headphone Headphone
L
R
L
R
0
1
0
0
0
0
0
0
0
1
SD
SD
SD
SD
SD
SD
SD
SD
SD
MUTE
(GM x M) 2(GM
M)
x
MUTE
MUTE
2
3
4
5
6
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
MUTE
MUTE
SD
SD
SD
SD
SD
SD
SD
SD
2(GM x M)
2(GM x M)
SD
2(GM x M)
2(GM x M)
SD
MUTE
(GM x M)
(GM x M)
MUTE
MUTE
(GM x M)
(GM x M)
MUTE
MUTE
(GM x M)
MUTE
SD
SD
(GL x L) + 2(GL
x
x
SD
SD
MUTE
MUTE
(GR x R)
L) +
2(GR
R)
7
8
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
MUTE
MUTE
SD
SD
SD
SD
SD
2(GL x L)
2(GL x L)
SD
2(GR x R)
2(GR x R)
SD
MUTE
(GL x L)
(GL x L)
MUTE
MUTE
(GR x R)
(GR x R)
MUTE
SD
9
MUTE
SD
10
(GL x L) +
(GR x R)
SD
SD
SD
11
1
0
1
1
MUTE (GM x M) + 2(GM
x
SD
SD
MUTE
MUTE
(GL x L) +
(GR x R)
M) +
2(GL
L)
x
+2(GR
R)
x
12
13
14
15
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
MUTE
MUTE
MUTE
SD
SD
SD
SD
SD
2(GL x L) + 2(GR x R) +
2(GM x M) 2(GM x M)
2(GL x L) + 2(GR x R) +
MUTE
MUTE
SD
SD
SD
(GL x L) +
(GM x M)
(GL x L) +
(GM x M)
MUTE
(GR x R) +
(GM x M)
(GR x R) +
(GM x M)
MUTE
2(GM x M)
SD
2(GM x M)
SD
(GM x M)
+(GL x L)
+(GR x R)
SD
SD
M - M Input Level
IN
L - L Input Level
IN
R - R Input Level
IN
G
G
G
- Mono Volume Control Gain
- Left Stereo Volume Control Gain
- Right Stereo Volume Control Gain
M
L
R
SD - Shutdown
MUTE - Mute
TABLE 6. National 3D Enhancement
0
1
0
1
Loudspeaker National 3D Off
Loudspeaker National 3D On
Headphone National 3D Off
Headphone National 3D On
LD5
RD5
TABLE 7. Wake-up Time Select
0
1
Fast Wake-up Setting
Slow Wake-up Setting
CD5
www.national.com
28
Application Information (Continued)
TABLE 8. Earpiece Amplifier Gain Select
0
1
0dB Earpiece Output Stage Gain Setting
6dB Earpiece Output Stage Gain Setting
CD4
I2C COMPATIBLE INTERFACE
channel separation whenever the left and right speakers are
too close to one another, due to system size constraints or
equipment limitations.
The LM4857 uses a serial bus, which conforms to the I2C
protocol, to control the chip’s functions with two wires: clock
(SCL) and data (SDA). The clock line is uni-directional. The
data line is bi-directional (open-collector). The maximum
clock frequency specified by the I2C standard is 400kHz. In
this discussion, the master is the controlling microcontroller
and the slave is the LM4857.
An external RC network, shown in Figure 1, is required to
enable the 3D effect. There are separate RC networks for
both the stereo loudspeaker outputs as well as the stereo
headphone outputs, so the 3D effect can be set indepen-
dently for each set of stereo outputs.
The I2C address for the LM4857 is determined using the
ADR pin. The LM4857’s two possible I2C chip addresses are
of the form 111110X10 (binary), where X1 = 0, if ADR is logic
low; and X1 = 1, if ADR is logic high. If the I2C interface is
used to address a number of chips in a system, the
LM4857’s chip address can be changed to avoid any pos-
sible address conflicts.
The amount of the 3D effect is set by the R3D resistor.
Decreasing the value of R3D will increase the 3D effect. The
C3D capacitor sets the low cutoff frequency of the 3D effect.
Increasing the value of C3D will decrease the low cutoff
frequency at which the 3D effect starts to occur, as shown by
Equation 1.
The bus format for the I2C interface is shown in Figure 2. The
bus format diagram is broken up into six major sections:
f3D(-3dB) = 1 / 2π(R3D)(C3D
)
(1)
The "start" signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all
devices attached to the I2C bus to check the incoming ad-
dress against their own address.
Activating the 3D effect will cause an increase in gain by a
multiplication factor of (1 + 20kΩ/R3D). Setting R3D to 20kΩ
will result in a gain increase by a multiplication factor of
(1+20kΩ/20kΩ) = 2 or 6dB whenever the 3D effect is acti-
vated. The volume control can be programmed through the
I2C compatible interface to compensate for the extra 6dB
increase in gain. For example, if the stereo volume control is
set at 0dB (11011 from Table 4) before the 3D effect is
activated, the volume control should be programmed to
–6dB (10111 from Table 4) immediately after the 3D effect
has been activated. Setting R3D = 20kΩ and C3D = 0.22µF
allows the LM4857 to produce a pronounced 3D effect with a
minimal increase in output noise.
The 8-bit chip address is sent next, most significant bit first.
The data is latched in on the rising edge of the clock. Each
address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master
releases the data line high (through a pull-up resistor). Then
the master sends an acknowledge clock pulse. If the
LM4857 has received the address correctly, then it holds the
data line low during the clock pulse. If the data line is not
held low during the acknowledge clock pulse, then the mas-
ter should abort the rest of the data transfer to the LM4857.
EXPOSED-DAP MOUNTING CONSIDERATIONS
The 8 bits of data are sent next, most significant bit first.
Each data bit should be valid while the clock level is stable
high.
The LM4857’s exposed-DAP (die attach paddle) package
(SP) provides a low thermal resistance between the die and
the PCB to which the part is mounted and soldered. This
allows rapid heat transfer from the die to the surrounding
PCB copper area heatsink, copper traces, ground plane, and
finally, surrounding air. The result is a low voltage audio
power amplifier that produces 1.6W dissipation in a 4Ω load
at ≤ 1% THD+N and over 1.8W in a 3Ω load at 10% THD+N.
This high power is achieved through careful consideration of
necessary thermal design. Failing to optimize thermal design
may compromise the LM4857’s high power performance and
activate unwanted, though necessary, thermal shutdown
protection.
After the data byte is sent, the master must check for another
acknowledge to see if the LM4857 received the data.
If the master has more data bytes to send to the LM4857,
then the master can repeat the previous two steps until all
data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data
signal goes high while the clock signal is high. The data line
should be held high when not in use.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD
)
The LM4857’s I2C interface is powered up through the
I2CVDD pin. The LM4857’s I2C interface operates at a volt-
age level set by the I2CVDD pin which can be set indepen-
dent to that of the main power supply pin VDD. This is ideal
whenever logic levels for the I2C interface are dictated by a
microcontroller or microprocessor that is operating at a lower
supply voltage than the main battery of a portable system.
The SP package must have its DAP soldered to a copper
pad on the PCB. The DAP’s PCB copper pad is then, ideally,
connected to a large plane of continuous unbroken copper.
This plane forms a thermal mass, heat sink, and radiation
area. Place the heat sink area on either outside plane in the
case of a two-sided or multi-layer PCB. (The heat sink area
can also be placed on an inner layer of a multi-layer board.
The thermal resistance, however, will be higher.) Connect
the DAP copper pad to the inner layer or backside copper
heat sink area with 9 (3 X 3) (SP) vias. The via diameter
should be 0.012in - 0.013in with a 1.27mm pitch. Ensure
efficient thermal conductivity by plugging and tenting the vias
with plating and solder mask, respectively.
NATIONAL 3D ENHANCEMENT
The LM4857 features a 3D audio enhancement effect that
widens the perceived soundstage from a stereo audio signal.
The 3D audio enhancement improves the apparent stereo
29
www.national.com
Bridge mode amplifiers are different from single-ended am-
plifiers that drive loads connected between a single amplifi-
er’s output and ground. For a given supply voltage, bridge
mode has a distinct advantage over the single-ended con-
figuration: its differential output doubles the voltage swing
across the load. Theoretically, this produces four times the
output power when compared to a single-ended amplifier
under the same conditions. This increase in attainable output
power assumes that the amplifier is not current limited and
that the output signal is not clipped.
Application Information (Continued)
Best thermal performance is achieved with the largest prac-
tical copper heat sink area. If the heatsink and amplifier
share the same PCB layer, a nominal 2in2 area is necessary
for 5V operation with a 4Ω load. Heatsink areas not placed
on the same PCB layer as the LM4857 should be 4in2 for the
same supply voltage and load resistance. The last two area
recommendations apply for 25˚C ambient temperature. In-
crease the area to compensate for ambient temperatures
above 25˚C. In all circumstances and under all conditions,
the junction temperature must be held below 150˚C to pre-
vent activating the LM4857’s thermal shutdown protection.
An example PCB layout for the exposed-DAP SP package is
shown in the Demonstration Board Layout section. Further
detailed and specific information concerning PCB layout and
fabrication and mounting an SP (LLP) is found in National
Semiconductor’s AN1187.
Another advantage of the differential bridge output is no net
DC voltage across the load. This is accomplished by biasing
LLS- and LLS+ outputs at half-supply. This eliminates the
coupling capacitor that single supply, single-ended amplifiers
require. Eliminating an output coupling capacitor in a typical
single-ended configuration forces a single-supply amplifier’s
half-supply bias voltage across the load. This increases
internal IC power dissipation and may permanently damage
loads such as speakers.
PCB LAYOUT AND SUPPLY REGULATION
CONSIDERATIONS FOR DRIVING 3Ω AND 4Ω LOADS
POWER DISSIPATION
Power dissipated by a load is a function of the voltage swing
across the load and the load’s impedance. As load imped-
ance decreases, load dissipation becomes increasingly de-
pendent on the interconnect (PCB trace and wire) resistance
between the amplifier output pins and the load’s connec-
tions. Residual trace resistance causes a voltage drop,
which results in power dissipated in the trace and not in the
load as desired. For example, 0.1Ω trace resistance reduces
the output power dissipated by a 4Ω load from 1.6W to 1.5W.
The problem of decreased load dissipation is exacerbated
as load impedance decreases. Therefore, to maintain the
highest load dissipation and widest output voltage swing,
PCB traces that connect the output pins to a load must be as
wide as possible.
Power dissipation is a major concern when designing a
successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to
the load by a bridge amplifier is higher internal power dissi-
pation. The LM4857 has 3 sets of bridged-tied amplifier pairs
driving LLS, RLS, and EP. The maximum internal power
dissipation operating in the bridge mode is twice that of a
single-ended amplifier. From Equation (3) and (4), assuming
a 5V power supply and an 8Ω load, the maximum power
dissipation for LLS and RLS is 634mW per channel. From
equation (5), assuming a 5V power supply and a 32Ω load,
the maximum power dissipation for EP is 158mW.
2
PDMAX-LLS = 4(VDD
)
/ (2π2 RL): Bridged
/ (2π2 RL): Bridged
/ (2π2 RL): Bridged
(3)
(4)
(5)
Poor power supply regulation adversely affects maximum
output power. A poorly regulated supply’s output voltage
decreases with increasing load current. Reduced supply
voltage causes decreased headroom, output signal clipping,
and reduced output power. Even with tightly regulated sup-
plies, trace resistance creates the same effects as poor
supply regulation. Therefore, making the power supply
traces as wide as possible helps maintain full output voltage
swing.
2
PDMAX-RLS = 4(VDD
)
2
PDMAX-EP = 4(VDD
)
The LM4857 also has 3 sets of single-ended amplifiers
driving LHP, RHP, and LINEOUT. The maximum internal
power dissipation for ROUT and LOUT is given by equation
(6) and (7). From Equations (6) and (7), assuming a 5V
power supply and a 32Ω load, the maximum power dissipa-
tion for LOUT and ROUT is 40mW per channel. From equa-
tion (8), assuming a 5V power supply and a 5kΩ load, the
maximum power dissipation for LINEOUT is negligible.
BRIDGE CONFIGURATION EXPLANATION
The LM4857 consists of three sets of a bridged-tied amplifier
pairs that drive the left loudspeaker (LLS), the right loud-
speaker (RLS), and the mono earpiece (EP). For this discus-
sion, only the LLS bridge-tied amplifier pair will be referred
to. The LM4857 drives a load, such as a speaker, connected
between outputs, LLS+ and LLS-. In the LLS amplifier block,
the output of the amplifier that drives LLS- serves as the
input to the unity gain inverting amplifier that drives LLS+.
2
PDMAX-LHP = (VDD
)
/ (2π2 RL): Single-ended
/ (2π2 RL): Single-ended
/ (2π2 RL): Single-ended
(6)
(7)
(8)
2
2
PDMAX-RHP = (VDD
)
This results in both amplifiers producing signals identical in
magnitude, but 180˚ out of phase. Taking advantage of this
phase difference, a load is placed between LLS- and LLS+
and driven differentially (commonly referred to as ’bridge
mode’). This results in a differential or BTL gain of:
PDMAX-LINE = (VDD
)
The maximum internal power dissipation of the LM4857
occurs during output modes 3, 8, and 13 when both loud-
speaker and headphone amplifiers are simultaneously on;
and is given by Equation (9).
AVD = 2(Rf / Ri) = 2
(2)
Both the feedback resistor, Rf, and the input resistor, Ri, are
internally set.
PDMAX-TOTAL
=
PDMAX-LLS + PDMAX-RLS + PDMAX-LHP + PDMAX-RHP (9)
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30
LM4857’s supply pins and ground. Keep the length of leads
and traces that connect capacitors between the LM4857’s
power supply pin and ground as short as possible.
Application Information (Continued)
The maximum power dissipation point given by Equation (9)
must not exceed the power dissipation given by Equation
(10):
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires a high
value input coupling capacitor (Ci in Figure 1). In many
cases, however, the speakers used in portable systems,
whether internal or external, have little ability to reproduce
signals below 50Hz. Applications using speakers with this
limited frequency response reap little improvement; by using
a large input capacitor.
PDMAX’ = (TJMAX - TA) / θJA
(10)
The LM4857’s TJMAX = 150˚C. In the ITL package, the
LM4857’s θJA is 62˚C/W. At any given ambient temperature
TA, use Equation (10) to find the maximum internal power
dissipation supported by the IC packaging. Rearranging
Equation (10) and substituting PDMAX-TOTAL for PDMAX’ re-
sults in Equation (11). This equation gives the maximum
ambient temperature that still allows maximum stereo power
dissipation without violating the LM4857’s maximum junction
temperature.
The internal input resistor (Ri) and the input capacitor (Ci)
produce a high pass filter cutoff frequency that is found using
Equation (13).
fc = 1 / (2πRiCi)
(13)
TA = TJMAX - PDMAX-TOTAL θJA
(11)
As an example when using a speaker with a low frequency
limit of 50Hz and Ri = 20kΩ, Ci, using Equation (13) is
0.19µF. The 0.22µF Ci shown in Figure 4 allows the LM4857
to drive high efficiency, full range speaker whose response
extends below 40Hz.
For a typical application with a 5V power supply, stereo 8Ω
loudspeaker load, and the stereo 32Ω headphone load, the
maximum ambient temperature that allows maximum stereo
power dissipation without exceeding the maximum junction
temperature is approximately 66.4˚C for the ITL package.
Output Capacitor Value Selection
Amplifying the lowest audio frequencies also requires the
use of a high value output coupling capacitor (CO in Figure
1). A high value output capacitor can be expensive and may
compromise space efficiency in portable design.
TJMAX = PDMAX-TOTAL θJA + TA
(12)
Equation (12) gives the maximum junction temperature TJ
-
The speaker load (RL) and the output capacitor (CO) form a
high pass filter with a low cutoff frequency determined using
Equation (14).
MAX. If the result violates the LM4857’s 150˚C, reduce the
maximum junction temperature by reducing the power sup-
ply voltage or increasing the load resistance. Further allow-
ance should be made for increased ambient temperatures.
fc = 1 / (2πRLCO)
(14)
The above examples assume that a device is a surface
mount part operating around the maximum power dissipation
point. Since internal power dissipation is a function of output
power, higher ambient temperatures are allowed as output
power or duty cycle decreases. If the result of Equation (9) is
greater than that of Equation (10), then decrease the supply
voltage, increase the load impedance, or reduce the ambient
temperature. If these measures are insufficient, a heat sink
can be added to reduce θJA. The heat sink can be created
using additional copper area around the package, with con-
nections to the ground pin(s), supply pin and amplifier output
pins. External, solder attached SMT heatsinks such as the
Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC, θCS, and
When using a typical headphone load of RL = 32Ω with a low
frequency limit of 50Hz, CO is 99µF.
The 100µF CO shown in Figure 4 allows the LM4857 to drive
a headphone whose frequency response extends below
50Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consid-
eration should be paid to value of CB, the capacitor con-
nected to the BYPASS pin. Since CB determines how fast
the LM4857 settles to quiescent operation, its value is critical
when minimizing turn-on pops. The slower the LM4857’s
θ
SA. (θJC is the junction-to-case thermal impedance, θCS is
outputs ramp to their quiescent DC voltage (nominally VDD
/
the case-to-sink thermal impedance, and θSA is the sink-to-
ambient thermal impedance.) Refer to the Typical Perfor-
mance Characteristics curves for power dissipation informa-
tion at lower output power levels.
2), the smaller the turn-on pop. Choosing CB equal to 2.2µF
along with a small value of Ci (in the range of 0.1µF to
0.39µF), produces a click-less and pop-less shutdown func-
tion. As discussed above, choosing Ci no larger than neces-
sary for the desired bandwidth helps minimize clicks and
pops. CB’s value should be in the range of 5 times to 10
times the value of Ci. This ensures that output transients are
eliminated when the LM4857 transitions in and out of shut-
down mode. Connecting a 2.2µF capacitor, CB, between the
BYPASS pin and ground improves the internal bias voltage’s
stability and improves the amplifier’s PSRR. The PSRR im-
provements increase as the bypass pin capacitor value in-
creases. However, increasing the value of CB will increase
wake-up time. The selection of bypass capacitor value, CB,
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically
use a 10µF in parallel with a 0.1µF filter capacitors to stabi-
lize the regulator’s output, reduce noise on the supply line,
and improve the supply’s transient response. However, their
presence does not eliminate the need for a local 1.0µF
tantalum bypass capacitance connected between the
31
www.national.com
Application Information (Continued)
depends on desired PSRR requirements, click and pop per-
formance, wake-up time, system cost, and size constraints.
20079709
FIGURE 4. Reference Design Board Schematic
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32
Demonstration Board ITL PCB Layout
20079707
Recommended ITL PCB Layout:
Top Silkscreen
20079706
Recommended ITL PCB Layout:
Top Layer
20079704
Recommended ITL PCB Layout:
Inner Layer 1
20079705
Recommended ITL PCB Layout:
Inner Layer 2
33
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Demonstration Board ITL PCB Layout (Continued)
20079703
Recommended ITL PCB Layout:
Bottom Layer
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34
Demonstration Board SP PCB Layout
200797I9
Recommended SP PCB Layout:
Top Over Layer
200797I8
Recommended SP PCB Layout:
Top Layer
200797I7
Recommended SP PCB Layout:
Mid Layer
200797I6
Recommended SP PCB Layout:
Bottom Layer
35
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Physical Dimensions inches (millimeters) unless otherwise noted
30-Bump micro SMD
Order Number LM4857ITL
NS Package Number TLA30CZA
X1 = 2.543 0.03 X2 = 2.949 0.03 X3 = 0.6 0.075
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36
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28 — Lead SP Package
Order Number LM4857SP
NS Package Number SPA28A
37
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
49 Bump GR Package
Order Number LM4857GR
NS Package Number GRA49A
(available soon)
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
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Support Center
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Fax: +49 (0) 180-530 85 86
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Support Center
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Fax: 81-3-5639-7507
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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