LM4937_技术文档

February 2007

LM4937

Audio Sub-System with OCL Stereo Headphone Output

and RF Suppression

General Description

Key Specifications

The LM4937 is an integrated audio sub-system designed for

mono voice, stereo music cell phones connecting to base

band processors with mono differential analog voice paths.

Operating on a 3.3V supply, it combines a mono speaker am-

plifier delivering 520mW into an 8Ω load, a stereo headphone

amplifier delivering 36mW per channel into a 32Ω load, and

a mono earpiece amplifier delivering 55mW into a 32Ω load.

It integrates the audio amplifiers, volume control, mixer, and

power management control all into a single package. In ad-

dition, the LM4937 routes and mixes the single-ended stereo

and differential mono inputs into multiple distinct output

modes. The LM4937 features an I²S serial interface for full

range audio and an I²C or SPI compatible interface for control.

The full range music path features an SNR of 85dB with an

18-bit 48kHz input.

■ꢀP_OUT, BTL, 8Ω, 3.3V, 1%

■ꢀP_OUTH/P, 32Ω, 3.3V, 1%

■ꢀP_OUTMono Earpiece, 32Ω, 1%

■ꢀShutdown current

520mW (typ)

36mW (typ)

55mW (typ)

0.6µA (typ)

85dB (typ)

■ꢀSNR (DAC + Amplifier)

Features

18-bit stereo DAC

■

Multiple distinct output modes

Mono speaker amplifier

Stereo headphone amplifier

Boomer audio power amplifiers are designed specifically to

provide high quality output power with a minimal amount of

external components.

Mono earpiece amplifier

Differential mono analog input

Independent loudspeaker, headphone and mono earpiece

volume controls

■

I²C/SPI (selectable) compatible interface

■

Ultra low shutdown current

Click and Pop Suppression circuit

Applications

Cell Phones

■

PDAs

Boomer® is a registered trademark of National Semiconductor Corporation.

202020

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Block Diagram

20202001

FIGURE 1. Audio Sub-System Block Diagram with OCL HP Outputs

(HP outputs may also be configured as cap-coupled)

Connection Diagrams

36 – Bump Micro SMD

20202058

Top View (Bump Side Down)

Order Number LM4937TL

See NS Package Number TLA36LVA

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2

36 – Bump Micro SMD

Top Marking Drawing

20202002

Top View

XY — 2 Digit Date Code

TT — Die Traceability

G — Boomer Family

I1 — LM4937TL

3

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Pin Descriptions

Pin Name

Digital/

Analog

I/O, Power

Description

A1

A2

A3

A4

A5

A6

B1

B2

B3

B4

B5

B6

C1

C2

C3

C4

C5

C6

D1

D2

D3

D4

D5

D6

E1

E2

E3

E4

E5

E6

F1

F2

F3

F4

F5

F6

DGND

MCLK

I2S_WS

SDA/SDI

DVDD

VDD_IO

PLL_VDD

I2S_SDATA

I2S_CLK

GPIO

D

A

P

I

DIGITAL GND

MASTER CLOCK

I/O

P

I

I2S WORD SELECT

I2C SDA OR SPI SDI

DIGITAL SUPPLY VOLTAGE

I/O SUPPLY VOLTAGE

PLL SUPPLY VOLTAGE

I2S SERIAL DATA INPUT

I2S CLOCK SIGNAL

I/O

O

P

I

TEST PIN (MUST BE LEFT FLOATING)

I2C SUPPLY VOLTAGE

I2C_VDD

SDL/SCK

PLL_GND

PLL_OUT

PLL_IN

ADDR/ENB

BYPASS

AVDD

AGND

NC

I2C_SCL OR SPI_SCK

P

O

I

PLL GND

PLL FILTER OUTPUT

PLL FILTER INPUT

I

I2C ADDRESS OR SPI ENB DEPENDING ON MODE

HALF-SUPPLY BYPASS

ANALOG SUPPLY VOLTAGE

ANALOG GND

I

P

ANALOG GND

NO CONNECT

MODE

RHP

D

A

I

O

I

SELECTS BETWEEN I2C OR SPI CONTROL

RIGHT HEADPHONE OUTPUT

HEADPHONE CENTER PIN OUTPUT (1/2 VDD or GND)

ANALOG NEGATIVE DIFFERENTIAL INPUT

ANALOG LEFT CHANNEL INPUT

ANALOG RIGHT CHANNEL INPUT

NO CONNECT

CHP

DIFF_

LIN

I

RIN

I

NC

LHP

A

O

P

I

LEFT HEADPHONE OUTPUT

ANALOG GND

AGND

DIFF+

EP_

ANALOG POSITIVE DIFFERENTIAL INPUT

MONO EARPIECE-

O

P

O

EP+

MONO EARPIECE+

LS-

LOUDSPEAKER OUT-

AVDD

LS+

ANALOG SUPPLY VOLTAGE

LOUD SPEAKER OUT+

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4

Thermal Resistance

ꢁθ_JA(TLA36)

See AN-1279

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

100°C/W

Operating Ratings

Temperature Range

T_MIN≤ T_A≤ T_MAX

Supply Voltage

Analog Supply Voltage

Digital Supply Voltage

Storage Temperature

Input Voltage

6.0V

-65°C to +150°C

-0.3V to V_DD+0.3V

Internally Limited

2000V

−40°C ≤T_A≤+85°C

Power Dissipation (Note 3)

ESD Susceptibility (Note 4)

ESD Susceptibility (Note 5)

Junction Temperature

2.7V ≤ AV_DD≤ 5.5V

2.7V ≤ DV_DD≤ 4.0V

2.4V ≤I²CV_DD≤4.0V

200V

150°C

Audio Amplifier Electrical Characteristics AV_DD= 3.0V, DV_DD= 3.0V (Notes 1, 2)

The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified.

Limits apply for T_A= 25°C.

Symbol

Parameter

Conditions

LM4937

Typical Limits

(Note 6) (Notes 7, 8)

Units

(Limits)

V_IN= 0, No Load

14

19

mA (max)

All Amps On + DAC, OCL (Note 11)

Headphone Mode Only, OCL

4.6

7

6.25

11.5

mA (max)

Mono Loudspeaker Mode Only (Note 11)

I_DD

Supply Current

Mono Earpiece Speaker Mode Only

D_6 = 0 (register 01h)

D_6 = 1

3.7

3.3

5

mA (max)

mA

DAC Off, All Amps On (OCL) (Note 11)

10

15.5

2

mA (max)

I_SD

Shutdown Current

0.6

μA (max)

Speaker; THD = 1%;

f = 1kHz, 8Ω BTL

Headphone; THD = 1%;

f = 1kHz, 32Ω SE

420

27

370

24

mW (min)

P_O

Output Power

Earpiece; THD = 1%;

f = 1kHz, 32Ω BTL

mW (min)

45

2.4

40

V_{FS DAC}

THD+N

Full Scale DAC Output

Total Harmonic Distortion

Vpp

%

Speaker; P_O= 200mW;

f = 1kHz, 8Ω BTL

Headphone; P_O= 10mW;

f = 1kHz, 32Ω SE

Earpiece; P_O= 20mW;

f = 1kHz, 32Ω BTL

Speaker

0.04

0.01

0.04

%

10

55

50

40

mV (max)

V_OS

Offset Voltage

Earpiece

8

Headphone (OCL)

Output Noise

A = weighted; 0dB gain;

See Table 1

Table 1

∈

O

PSRR

Power Supply Rejection Ratio

f = 217Hz; V_ripple= 200mV_P-P

Table 2

–60

C_B= 2.2μF; See Table 2

Headphone; P_O= 10mW

f = 1kHz; OCL

Xtalk

T_WU

Crosstalk

dB

35

85

56

ms (max)

dB

Wake-Up Time

C_B= 2.2μF, CD6 = 0

C_B= 2.2μF, CD6 = 1

CMRR

Common-Mode Rejection Ratio

f = 217Hz, V_RMS= 200mVpp

5

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Audio Amplifier Electrical Characteristics AV_DD= 5.0V, DV_DD= 3.3V (Notes 1, 2)

The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified.

Limits apply for T_A= 25°C.

Symbol

Parameter

Conditions

LM4937

Typical Limits

Units

(Limits)

(Note 6) (Notes 7,

8)

V_IN= 0, No Load

17.5

mA (max)

All Amps On + DAC, OCL (Note 11)

Headphone Mode Only (OCL)

5.8

11.6

5

mA (max)

μA (max)

I_DD

Supply Current

Mono Loudspeaker Mode Only (Note 11)

Mono Earpiece Mode Only (Note 11)

DAC Off, All Amps On (OCL) (Note 11)

12.9

1.6

I_SD

Shutdown Current

Speaker; THD = 1%;

f = 1kHz, 8Ω BTL

Headphone; THD = 1%;

f = 1kHz, 32Ω SE

1.25

80

mW (min)

P_O

Output Power

Earpiece; THD = 1%;

f = 1kHz, 32Ω BTL

175

2.4

mW (min)

Vpp

V_{FS DAC}

Full Scale DAC Output

Total Harmonic Distortion

Speaker; P_O= 500mW;

f = 1kHz, 8Ω BTL

Headphone; P_O= 30mW;

f = 1kHz, 32Ω SE

Earpiece; P_O= 40mW;

f = 1kHz, 32Ω BTL; CD4 = 0

Speaker

0.03

%

THD+N

0.01

0.04

%

10

8

mV

V_OS

Offset Voltage

Earpiece

HP (OCL)

8

Output Noise

A = weighted; 0dB gain;

See Table 1

∈

O

Table 1

Table 3

–56

PSRR

Power Supply Rejection Ratio

f = 217Hz; V_ripple= 200mV_P-P

C_B= 2.2μF; See Table 3

Headphone; P_O= 15mW

f = 1kHz; OCL

Xtalk

T_WU

Crosstalk

dB

45

ms

C_B= 2.2μF, CD6 = 0

C_B= 2.2μF, CD6 = 1

Wake-Up Time

130

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6

Volume Control Electrical Characteristics (Notes 1, 2)

The following specifications apply for 3V ≤ AV_DD≤ 5V and 2.7V ≤ DV_DD≤ 4.0V, unless otherwise specified. Limits apply for T_A=

25°C.

Symbol

Parameter

Conditions

LM4937

Typical

Units

(Limits)

Limits

(Note 6) (Notes 7,

8)

–7

dB (min)

dB (max)

dB (min)

dB (max)

dB (min)

dB (max)

dB (min)

dB (max)

minimum gain setting

–6

–5

Stereo Analog Inputs PreAmp Gain

Setting Range

15.5

maximum gain setting

minimum gain setting

maximum gain setting

minimum gain setting

maximum gain setting

15

14.5

PGR

–13

–12

–11

Differential Mono Analog Input

PreAmp Gain Setting Range

9.5

9

8.5

–59

–56

–53

Output Volume Control for

Loudspeaker, Headphone Output,

or Earpiece Output

VCR

4.5

+5

5.5

Stereo Channel to Channel Gain

Mismatch

ΔA_CH-CH

0.3

dB

V_in= 1V_rms, Gain = 0dB

with load

Mute Attenuation

A_MUTE

R_INPUT

Headphone

<-90

dB (min)

kΩ (min)

kΩ (max)

DIFF+, DIFF-, L_INand R_INInput

Impedance

18

23

28

Digital Section Electrical Characteristics (Notes 1, 2)

The following specifications apply for 3V ≤ AV_DD≤ 5V and 2.7V ≤ DV_DD≤ 4.0V, unless otherwise specified. Limits apply for T_A=

25°C.

Symbol

Parameter

Conditions

LM4937

Typical

Units

(Limits)

Limits

(Note 6) (Notes 7,

8)

Mode 0, DV_DD= 3.0V

DI_SD

Digital Shutdown Current

No MCLK

0.01

μA

f_MCLK= 12MHz, DV_DD= 3.0V

ALL MODES EXCEPT 0

DI_DD

Digital Power Supply Current

PLL Quiescent Current

5.3

4.8

6.5

6

mA (max)

PLLI_DD

f_MCLK= 12MHz, DV_DD= 3.0V

Audio DAC (Typical numbers are with 6.144MHz audio clock and 48kHz sampling frequency

R_DAC

Audio DAC Ripple

dB

kHz

dB

20Hz - 20kHz through headphone output

-3dB point

+/-0.1

22.6

76

PB_DAC

SBA_DAC

Audio DAC Passband width

Audio DAC Stop band Attenuation Above 24kHz

Audio DAC Dynamic Range

DC - 20kHz, –60dBFS; AES17 Standard

See Table 4

DR_DAC

Table 4

dB

Audio DAC-AMP Signal to Noise

Ratio

A-Weighted, Signal = V_Oat 0dBFS, f = 1kHz

SNR

Table 4

95

dB

Noise = digital zero, A-weighted, See Table

4

SNR_DAC

Internal DAC SNR

A-weighted (Note 10)

PLL

10

26

f_IN

Input Frequency on MCLK pin

12

MHz

7

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Symbol

Parameter

Conditions

LM4937

Typical

Units

(Limits)

Limits

(Note 6) (Notes 7,

8)

SPI/I²C

f_SPI

Maximum SPI Frequency

SPI Data Setup Time

SPI ENB Setup Time

SPI Data Hold Time

SPI ENB Hold Time

SPI Clock Low Time

SPI Clock High Time

I²C_CLK Frequency

I²C_DATA Hold Time

I²C_DATA Setup Time

I²C/SPI Input High Voltage

4000

100

125

400

100

kHz (max)

ns (max)

kHz (max)

ns (max)

t_SPISETD

t_SPISETENB

t_SPIHOLDD

t_SPIHOLDENB

t_SPICL

t_SPICH

f_CLKI2C

t_I2CHOLD

t_I2CSET

I²CV_DD0.7 x

I²CV_DD

V_IH

V (min)

V (max)

I²C/SPI Input Low Voltage

0

0.3 x

I²CV_DD

V_IL

I²S

I²S_RES = 0

I²S_RES = 1

1536

3072

6144

12288

40

I²S_CLK Frequency

kHz (max)

f_CLKI₂_S

I²S_WS Duty Cycle

50

%

60

Digital Input High Voltage

0.7 x

DV_DD

V_IH

V_IL

V (min)

V (max)

Digital Input Low Voltage

0.3 x

DV_DD

Note 1: All voltages are measured with respect to the GND pin unless otherwise specified.

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions

which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters

where no limit is given, however, the typical value is a good indication of device performance.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T_JMAX,θ_JA, and the ambient temperature, T_A. The maximum

allowable power dissipation is P_DMAX= (T_JMAX– T_A) / θ _JAor the number given in Absolute Maximum Ratings, whichever is lower. For the LM4937 typical application

with V_DD= 3.3V, R_L= 8Ω stereo operation, the total power dissipation is TBDW. θ_JA= TBD°C/W.

Note 4: Human body model: 100pF discharged through a 1.5kΩ resistor.

Note 5: Machine model: 220pF - 240pF discharged through all pins.

Note 6: Typicals are measured at 25°C and represent the parametric norm.

Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 8: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Note 9: Shutdown current is measured in a normal room environment.

Note 10: Internal DAC only with DAC modes 00 and 01.

Note 11: Enabling mono bit (D_6 in Output Control Register 01h) will save 400μA (typ) from specified current.

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8

TABLE 1. Output Noise

Output Noise AV_DD= 5V and AV_DD= 3V. All gains set to 0dB. Units in μV. A - weighted

MODE

EP

22

68

38

29

38

LS

22

88

48

34

48

HP OCL

Units

μV

1

2

3

4

5

6

7

8

μV

8

μV

46

24

18

24

μV

TABLE 2. PSRR AV_DD= 3V

PSRR AV_DD= 3V. f = 217Hz; V_ripple= 200mVp-p; C_B= 2.2μF.

MODE

EP(Typ)

69

LS (Typ)

76

LS (Limit)

HP (Typ)

HP (Limit)

Units

1

2

3

4

5

6

7

72

55

61

64

61

dB

69

76

67

68

69

76

63

62

69

68

69

70

69

68

TABLE 3. PSRR AV_DD= 5V

PSRR AV_DD= 5V. All gains set to 0dB. f = 217Hz; V_ripple= 200mVp-p; C_B= 2.2μF

MODE

EP (Typ)

LS (Typ)

72

HP (Typ)

Units

1

2

3

4

5

6

7

68

69

68

71

69

70

71

70

dB

72

66

69

72

69

TABLE 4. Dynamic Range and SNR

Dynamic Range and SNR. 3V ≤ AV_DD≤ 5V. All programmable gain set to 0dB. Units in dB.

DR (Typ)

SNR (Typ)

Units

LS

HP

EP

95

97

85

dB

9

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System Control

The LM4937 is controlled via either a two wire I²C compatible interface or three wire SPI interface, selectable with the MODE pin.

This interface is used to configure the operating mode, interfaces, data converters, mixers and amplifiers. The LM4937 is controlled

by writing 8 bit data into a series of write-only registers, the device is always a slave for both type of interfaces.

THREE WIRE, SPI INTERFACE (MODE = 1)

Three Wire Mode Write Bus Transaction

20202059

Three Wire Mode Write Bus Timing

20202060

FIGURE 2. Three Wire Mode Write Bus

When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is clocked in on the rising

edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are used to select an address within the device,

the lower 8 bits (7:0) contain the updated data for this register.

TWO WIRE I²C COMPATIBLE INTERFACE (MODE = 0)

Two Wire Mode Write Bus Transaction

202020j6

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10

Two Wire Mode Write Bus Timing

20202062

FIGURE 3. Two Wire Mode Write Bus

When the part is configured as an I²C device then the LM4937 will respond to one of two addresses, according to the ADDR input.

If ADDR is low then the address portion of the I²C transaction should be set to write to 0010000. When ADDR is high then the

address input should be set to write to 1110000.

TABLE 5. Chip Address

A7

0

A6

EC

0

A5

EC

0

A4

1

A3

0

A2

0

A1

0

A0

0

Chip Address

ADR = 0

0

1

0

ADR = 1

0

1

0

EC — Externally configured by ADR pin

11

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12

13

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System Controls

TABLE 7. Loudspeaker, Earpiece, HP Left or Right Volume Control

EP_VOL_4,

LS_VOL_4,

HP_L_VOL_4,

HP_R_VOL_4

EP_VOL_3,

EP_VOL_2,

LS_VOL_2,

HP_L_VOL_2,

HP_R_VOL_2

EP_VOL_1,

LS_VOL_1,

HP_L_VOL_1,

HP_R_VOL_1

EP_VOL_0,

LS_VOL_0,

HP_L_VOL_0,

HP_R_VOL_0

LS_VOL_3,

HP_L_VOL_3,

HP_R_VOL_3

Gain (dB)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

<–90 (MUTE)

–56

–52

–48

–45

–42

–39

–36

–33

–30

–28

–26

–24

–22

–20

–18

–16

–14

–12

–10

–8

–6

–4

–3

–2

–1

0

+1

+2

+3

+4

+5

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14

TABLE 8. Mixer Code Control

Mode

CD3

CD2

CD1

CD0

Mono

Earpiece

Loudspeaker Headphone

L

Headphone

R

0

1

2

3

4

5

0

1

0

1

0

1

0

1

0

1

0

1

SD

M

SD

M

SD

M

SD

M

AL+AR

M+AL+AR

DL+DR

AL+AR

M+AL+AR

DL+DR

AL

AR

M+AL

DL

M+AR

DR

DL+DR+

AL+AR

DL+AL

AL+AR

DL+AL

DR+AR

6

1

0

1

M+DL+AL+

DR+AR

M+DL+AL+

DR+AR

M+DL+AL

M+DL

M+DR+AR

M+DR

7

M+DL+DR

SD — Shutdown

M — Mono Differential Input

AL — Analog Left Channel

AR — Analog Right Channel

DL — I2S DAC Left Channel

DR — I2S DAC Right Channel

MUTE — Mute

Note: Power-On Default Mode is Mode 0

15

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TABLE 9. Output Control (01h)

LS_OUTPUT = 1

Output On

LS_OUTPUT = 0

Output Off

Loudspeaker

HP_L_OUTPUT = 1

Output On

HP_L_OUTPUT = 0

Headphone Left Channel

Output Off

Output Mute

(OCL = 1)

(OCL = 0)

HP_R_OUTPUT = 1

Output On

HP_R_OUTPUT = 0

Headphone Right Channel

Output Off

(OCL = 0)

Output Mute

(OCL = 1)

EP_OUTPUT = 1

Output On

EP_OUTPUT = 0

Earpiece

Output Off

CD3 = 0

CD3 = 1

All Outputs

Outputs Toggled Via Register Control

All Outputs Off

TABLE 10. Mono Differential Amplifier Input Gain Select (08h)

MONO_IN_GAIN_2

MONO_IN_GAIN_1

MONO_IN_GAIN_0

Input Gain Setting

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–12dB

–9dB

–6dB

–3dB

0dB

3dB

6dB

9dB

TABLE 11. Analog Single-Ended Input Amplifier Gain Select (07h)

ANA_L_GAIN_2

ANA_R_GAIN_2

ANA_L_GAIN_1

ANA_R_GAIN_1

ANA_L_GAIN_0

ANA_R_GAIN_0

Input Gain Setting

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–6dB

–3dB

0dB

3dB

6dB

9dB

12dB

15dB

TABLE 12. DAC Gain Select (08h)

DIG_L_GAIN_1

DIG_R_GAIN_1

DIG_L_GAIN_0

DIG_R_GAIN_0

Input Gain Setting

0

1

0

1

0

1

–3dB

0dB

3dB

6dB

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16

PLL Configuration Registers

PLL M DIVIDER CONFIGURATION REGISTER

This register is used to control the input divider of the PLL.

PLL_M (0Ah) (Set = logic 1, Clear = logic 0)

Bits

Register

Description

6:0

PLL_M

Programs the PLL input divider to select:

PLL_M

Divide Ratio

0

1

Divider Off

1

2

1.5

2

3

4

2.5

...

3→

126

63.5

NOTES:

The M divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details.

The division of the M divider is derived from PLL_M as such:

M = (PLL_M+1) / 2

PLL N DIVIDER CONFIGURATION REGISTER

This register is used to control PLL N divider.

PLL_N (0Bh) (Set = logic 1, Clear = logic 0)

Bits

Register

Description

7:0

PLL_N

Programs the PLL feedback divider:

PLL_N

0

Divide Ratio

Divider Off

10

1 → 10

11

12

...

248

249

248

249

NOTES:

The N divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The N divider should never be

set so that (Fin/M) * N > 55MHz (or 80MHz if FAST_VCO is set in the PLL_N_MOD register).

The non-sigma-delta division of the N divider is derived from the PLL_N as such:

N = PLL_N

Fin /M is often referred to as F_comp(Frequency of Comparison) or F_ref(Reference Frequency). In this document, F_compis used.

PLL P DIVIDER CONFIGURATION REGISTER

This register is used to control the PLL's P divider.

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PLL_P (0Dh) (Set = logic 1, Clear = logic 0)

Bits

3:0

Register

PLL_P

Description

Programs the PLL input divider to select:

0

1

Divider Off

1

1.5

2

3

...

13

14

15

–> 2.5

7

7.5

8

NOTES:

The output of this divider should be either 12 or 24MHz in USB mode or 11.2896MHz, 12.288MHz or 24.576MHz in non-USB modes.

The division of the P divider is derived from PLL_P as such:

P = (PLL_P+1) / 2

PLL N MODULATOR AND DITHER SELECT CONFIGURATION REGISTER

This register is used to control the Fractional component of the PLL.

PLL_N_MOD (0Ch) (Set = logic 1, Clear = logic 0)

Bits

Register

Description

4:0

PLL_N_MOD

This programs the PLL N Modulator's fractional component:

PLL_N_MOD

Fractional Addition

0

1

0/32

1/32

2 → 30

2/32 → 30/32

6:5

DITHER_LEVEL

FAST_VCO

Allows control over the dither used by the N Modulator

DITHER_LEVEL

DAC Sub-system Input Source

Medium (32)

00

01

10

Small (16)

Large (48)

7

If set the VCO maximum and minimum frequencies are raised:

FAST_VCO

Maximum F_VCO

40–55MHz

0

NOTES:

The complete N divider is a fractional divider as such:

N = PLL_N + (PLL_N_MOD/32)

If the modulus input is zero, then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula:

Fout = (Fin * N) / (M * P)

Please see over for more details on the PLL and common settings.

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18

Further Notes on PLL Programming

The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 25MHz with frequency errors

noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz sample

rates from any common clock source when the oversampling rate of the audio system is 125fs. In systems where 128x oversampling

must be used (for example with an isochronous I2S data stream) a clock synchronous to the sample rate should be used as input

to the PLL (typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a clock that is accurate

to within typical crystal tolerances of the real sample rate.

20202063

Example Of PLL Settings For 48Khz Sample Rates

f_in (MHz)

11

fsamp (kHz)

M

11

5

N

60

P

5

6

5

PLL_M

21

9

PLL_N

60

PLL_N_MOD

PLL_P

f_out (MHz)

48

0

9

12

25

12.288

13

4

19.53125

60

7

19

17

0

9

13

9

25

17

53

27

25

53

40

32

60

9

14.4

37.5

100

37

16

0

9

16.2

27

14

13

27

20.5

16.5

100

50

9

16.8

50

0

9

19.2

40.625

100

40

20

0

9

19.44

19.68

19.8

100

62

11

9

62.5

50

16

0

50

9

Example PLL Settings For 44.1Khz Sample Rates

f_in (MHz)

11

fsamp (kHz)

44.1

M

N

55.125

P

PLL_M

21

PLL_N

55

PLL_N_MOD

PLL_P

f_out (MHz)

11.025000

11

5

4

2

9

11.2896

12

44.1

8

39.0625

22.96875

55.125

5

4

5

15

9

39

22

55

45

30

55

45

38

45

30

9

7

9

5

31

4

13

12

9

25

23

17

33

31

26

40

21

14.4

16.2

16.8

19.2

19.44

19.68

19.8

45.9375

30.625

30

20

25

30

9

17

16

55.78125

45.9375

13.5 38.28125

20.5 45.9375

30

20

11

30.625

These tables cover the most common applications, obtaining clocks for sample rates such as 22.05kHz and 192kHz should be

done by changing the P divider value or the R divider in the clock configuration diagram.

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If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining

11.2896 from 12.000MHz is shown below.

Choose a small range of P so that the VCO frequency is swept between 45 and 55MHz (or 60-80MHz if VCOFAST is used).

Remembering that the P divider can divide by half integers. So for P = 4.0 → 7.0 sweep the M inputs from 2.5 → 24. The most

accurate N and N_MOD can be calculated by:

N = FLOOR(((Fout/Fin)*(P*M)),1)

N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0)

This shows that setting M = 11.5, N = 75 N_MOD = 47 P = 7 gives a comparison frequency of just over 1MHz, a VCO frequency

of just under 80MHz (so VCO_FAST must be set) and an output frequency of 11.289596 which gives a sample rate of

44.099985443kHz, or accurate to 0.33 ppm.

Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used in the above mode.

The I2S should be master on the LM4937 so that the data source can support appropriate SRC as required. This method should

only be used with data being read on demand to eliminate sample rate mismatch problems.

Where a system clock exists at an integer multiple of the required DAC clock rate it is preferable to use this rather than the PLL.

The LM4937 is designed to work in 8,12,16,24,32, and 48kHz modes from a 12MHz clock without the use of the PLL. This saves

power and reduces clock jitter.

Clock Configuration Register

This register is used to control the multiplexers and clock R divider in the clock module.

CLOCK (09h) (Set = logic 1, Clear = logic 0)

Bits

Register

Description

0

FAST_CLOCK

If set master clock is divided by two.

FAST_CLOCK

MCLK Frequency

Normal

0

1

Divided by 2

1

2

PLL_INPUT

Programs the PLL input multiplexer to select:

PLL_INPUT

PLL Input Source

0

1

MCLK

I²S Input Clock

AUDIO_CLK_SEL

Selects which clock is passed to the audio sub-system

DAC_CLK_SEL

DAC Sub-system

Input Source

0

1

PLL Input

PLL Output

3

PLL_ENABLE

If set enables the PLL. (MODES 4–7 only)

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20

Bits

Register

Description

7:4

R_DIV

Programs the R divider

R_DIV

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Divide Value

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

7

7.5

8

20202053

By default the stereo DAC operates at 250*fs, i.e. 12.000MHz (at the clock generator input clock) for 48kHz data. It is expected

that the PLL be used to drive the audio system unless a 12.000MHz master clock is supplied. The PLL can also use the I2S clock

input as a source. In this case, the audio DAC uses the clock from the output of the PLL.

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Common Clock Settings for the DAC

The DAC can work in 4 modes, each with different oversampling rates, 125,128,64 & 32. In normal operation 125x oversampling

provides for the simplest clocking solution as it will work from 12.000MHz (common in most systems with Bluetooth or USB) at

48kHz exactly. The other modes are useful if data is being provided to the DAC from an uncontrollable isochronous source (such

as a CD player, DAB, or other external digital source) rather than being decoded from memory. In this case the PLL can be used

to derive a clock for the DAC from the I2S clock.

The DAC oversampling rate can be changed to allow simpler clocking strategies, this is controlled in the DAC SETUP register but

the oversampling rates are as follows:

DAC MODE

Over sampling Ratio Used

00

01

10

11

125

128

64

32

The following table describes the clock required at the clock generator input for various clock sample rates in the different DAC

modes:

Fs (kHz)

8

DAC Oversampling Ratio

Required CLock at DAC Clock Generator Input (MHz)

125

128

125

128

125

128

125

128

125

128

125

128

125

128

125

128

125

128

64

2

8

2.048

2.75625

2.8224

3

11.025

12

3.072

4

16

4.096

5.5125

5.6448

6

22.05

24

6.144

8

32

8.192

11.025

11.2896

12

44.1

48

12.288

11.2896

12.288

22.5792

24.576

88.2

96

64

176.4

192

32

Methods for producing these clock frequencies are described in the PLL section.

The R divider can be used when the master clock is exactly 12.00 MHz in order to generate different sample rates. The Table

below shows different sample rates supported from 12.00MHz by using only the R divider and disabling the PLL. In this way we

can save power and the clock jitter will be low.

R_DIV

Divide Value

DAC Clock Generator Input Frequency <MHz>

Sample Rate Supported <KHz>

11

9

6

5

2

2.4

3

8

9.6

12

7

4

5

3

4

16

4

2.5

4.8

19.2

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22

R_DIV

Divide Value

DAC Clock Generator Input Frequency <MHz>

Sample Rate Supported <KHz>

3

2

0

2

1.5

1

6

8

24

32

48

12

The R divider can also be used along with the P divider in order to create the clock needed to support low sample rates.

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DAC Setup Register

This register is used to configure the basic operation of the stereo DAC.

DAC_SETUP (0Eh) ꢀ (Set = logic 1, Clear = logic 0)

Bits

Register

Description

1:0

DAC_MODE

The DAC used in the LM4937 can operate in one of 4 oversampling modes.

The modes are described as follows:

DAC_MODE

Oversampling

Rate

Typical FS

Clock Required

00

01

125

48KHz

12.000MHz (USB

Mode)

128

44.1KHz

48KHz

11.2896MHz

12.288MHz

10

11

64

32

96KHz

12.288MHz

24.576MHz

192KHz

2

3

4

5

MUTE_L

MUTE_R

Mutes the left DAC channel on the next zero crossing.

Mutes the right DAC channel on the next zero crossing.

If set the dither in DAC is disabled.

DITHER_OFF

DITHER

If set the dither in DAC is enabled all the time.

ALWAYS_ON

6

CUST_COMP

If set the DAC frequency response can be programmed manually via a 5 tap FIR

“compensation” filter. This can be used to enhance the frequency response of small

loudspeakers or provide a crude tone control. The compensation Coefficients can be

set by using registers 10h to 15h.

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24

Interface Control Register

This register is used to control the I2S and I²C compatible interface on the chip.

INTERFACE (0Fh) (Set = logic 1, Clear = logic 0)

Bits

Register

Description

0

I2S_MASTER_SLAVE

If set the LM4937 acts as a master for

I2S, so both I2S clock and I2S word

select are configured as outputs. If

cleared the LM4937 acts as a slave

where both I2S clock and word select

are configured as inputs.

1

I2S_RESOLUTION

If set the I2S resolution is set to 32 bits.

If clear, resolution is set to 16 bits. This

bit only affects the I2S Interface in

master mode. In slave mode the I2S

Interface can support any I2S

compatible resolution. In master mode

the I2S resolution also depends on the

DAC mode as the note below explains.

2

3

I2S_MODE

I2C_FAST

If set the I2S is configured in left

justified mode timing. If clear, the I2S

interface is configured in normal I2S

mode timing.

If set enables the I2C to run in fast

mode with an I2C clock up to 3.4MHz.

If clear the I2C speed gets its default

value of a maximum of 400kHz

NOTES:

The master I2S format depends on the DAC mode. In USB mode the number of bits per word is 25 (i.e. 2.4MHz for a 48kHz sample rate). The duty cycle is 40/60.

In non-USB modes the format is 32 or 16 bits per word, depending on I2S_RESOLTION and the duty cycle is always 50-50. In slave mode it will decode any I2S

compatible data stream.

20202027

I2S Mode Timing

20202028

Left Justified Mode Timing

25

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must be programmed via the I2C/SPI Interface in bytes as

follows:

FIR Compensation Filter

Configuration Registers

These registers are used to configure the DAC’s FIR com-

pensation filter. Three 16 bit coefficients are required and

COMP_COEFF (10h → 15h) (Set = logic 1, Clear = logic 0)

Address

10h

Register

Description

COMP_COEFF0_LSB

COMP_COEFF0_MSB

COMP_COEFF1_LSB

COMP_COEFF1_MSB

COMP_COEFF2_LSB

COMP_COEFF2_MSB

Bits [7:0] of the 1st and 5th FIR tap (C0 and C4)

Bits [15:8] of the 1st and 5th FIR tap (C0 and C4)

Bits [7:0] of the 2nd and 4th FIR tap (C1 and C3)

Bits [15:8] of the 2nd and 4th FIR tap (C1 and C3)

Bits [7:0] of the 3rd FIR tap (C2)

11h

12h

13h

14h

15h

Bits [15:8] of the 3rd FIR tap (C2)

NOTES:

The filter must be phase linear to ensure the data keeps the correct stereo imaging so the second half of the FIR filter must be the reverse of the 1st half.

20202055

If the CUST_COMP option in register 0Eh is not set the FIR

filter will use its default values for a linear response from the

DAC into the analog mixer, these values are:

DAC_OSR

00

C0, C4

434

C1, C3

–2291

–371

C2

26984

25699

01, 10, 11

61

If using 96 or 192kHz data then the custom compensation

may be required to obtain flat frequency responses above

24kHz. The total power of any custom filter must not exceed

that of the above examples or the filters within the DAC will

clip. The coefficient must be programmed in 2’s complement.

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26

Typical Performance Characteristics

THD+N vs Frequency

3V EP Out, R_L= 32Ω, P_O= 20mW

THD+N vs Frequency

3V HP Out, R_L= 16Ω, P_O= 20mW

20202064

20202065

20202067

20202070

THD+N vs Frequency

3V LS Out, R_L= 8Ω, P_O= 200mW

THD+N vs Frequency

5V EP, R_L= 32Ω, P_O= 40mW

20202066

THD+N vs Frequency

5V HP Out, R_L= 16Ω, P_O= 60mW

THD+N vs Frequency

5V HP Out, R_L= 32Ω, P_O= 30mW

20202069

27

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THD+N vs Frequency

5V LS Out, R_L= 8Ω, P_O= 500mW

THD+N vs Output Power

3V EP Out, R_L= 16Ω, f = 1kHz

20202071

20202073

20202077

20202072

20202076

20202019

THD+N vs Output Power

3V EP Out, R_L= 32Ω, f = 1kHz

THD+N vs Output Power

3V HP Out, R_L= 16Ω, f = 1kHz

THD+N vs Output Power

3V HP Out, R_L= 32Ω, f = 1kHz

THD+N vs Output Power

3V LS Out, R_L= 8Ω, f = 1kHz

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THD+N vs Output Power

5V EP Out, R_L= 16Ω, f = 1kHz

THD+N vs Output Power

5V EP Out, R_L= 32Ω, f = 1kHz

20202078

20202079

THD+N vs Output Power

5V HP Out, R_L= 16Ω, f = 1kHz

THD+N vs Output Power

5V HP Out, R_L= 32Ω, f = 1kHz

20202080

20202081

THD+N vs Output Power

5V LS Out, R_L= 8Ω, f = 1kHz

THD+N vs I2S Level

EP Out

20202083

20202082

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THD+N vs I2S Level

HP Out

THD+N vs I2S Level

LS Out

20202085

20202084

20202086

20202088

PSRR vs Frequency

3V EP Out Mode 1

PSRR vs Frequency

3V EP Out Mode 4

20202087

PSRR vs Frequency

3V HP Out Mode 2

PSRR vs Frequency

3V HP Out Mode 4

20202089

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PSRR vs Frequency

3V LS Out Mode 2

PSRR vs Frequency

3V LS Out Mode 4

20202090

20202092

20202094

20202091

20202093

20202095

PSRR vs Frequency

5V HP Out Mode 2

PSRR vs Frequency

5V HP Out Mode 4

PSRR vs Frequency

5V LS Out Mode 4

PSRR vs Frequency

5V LS Out Mode 2

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Output Power vs Supply Voltage

EP Out , R_L= 32Ω, 1% THD+N

Output Power vs Supply Voltage

HP Out , R_L= 32Ω, 1% THD+N

20202097

20202096

Output Power vs Supply Voltage

LS Out , R_L= 8Ω, 1% THD+N

20202098

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32

Application Information

I²S

The LM4937 supports both master and slave I2S transmission at either 16 or 32 bits per word at clock rates up to 3.072MHz (48kHz

stereo, 32bit). The basic format is shown below:

20202007

FIGURE 4.

MONO ONLY SETTING

The LM4937 may be restricted to mono amplification only by setting D-6 in Output Control register 0x01h to 1. This may save an

additional 400μA from I_DD

.

LM4937 DEMOBOARD OPERATION

BOARD LAYOUT

ꢀPin 3 — I2S_SDI

ꢀPin 4 — I2S_WS

JP20 — Toslink SPDIF Input

JP21 — Coaxial SPDIF Input

DIGITAL SUPPLIES

JP14 — Digital Power DVDD

JP10 — I/O Power IOVDD

JP13 — PLL Supply PLLVDD

JP16 — USB Board Supply BBVDD

JP15 — I2C VDD

Coaxial and Toslink inputs may be toggled between by use of

S25. Only one may be used at a time. Must be used in con-

junction with on-board SPDIF receiver chip.

OUTPUTS

JP5 — BTL Loudspeaker Output

All supplies may be set independently. All digital ground is

common. Jumpers may be used to connect all the digital sup-

plies together.

JP1 — Left Headphone Output (Single-Ended or OCL)

JP3 — Right Headphone Output (Single-Ended or OCL)

P1 — Stereo Headphone Jack (Same as JP1, JP2, Single-

Ended or OCL)

S9 – connects VDD_PLL to VDD_D

S10 – connects VDD_D to VDD_IO

JP12 — Mono BTL Earpiece Output

S11 – connects VDD_IO to VDD_I2C

CONTROL INTERFACE

S12 – connects VDD_I2C to Analog VDD

S17 – connects BB_VDD to USB3.3V (from USB board)

S19 – connects VDD_D to USB3.3V (from USB board)

S20 – connects VDD_D to SPDIF receiver chip

X1, X2 – USB Control Bus for I2C/SPI

X1

Pin 9 – Mode Select (SPI or I2C)

ANALOG SUPPLY

JP11 — Analog Supply

X2

ꢀS12 — connects Analog VDD with Digital VDD (I2C_VDD)

ꢀS16 — connects Analog Ground with Digital Ground

ꢀS21 — connects Analog VDD to SPDIF receiver chip

Pin 1 – SDA

Pin 3 – SCL

Pin 15 – ADDR/END

Pin 14 – USB5V

Pin 16 – USB3.3V

Pin 16 – USB GND

INPUTS

Analog Inputs

JP2 — Mono Differential Input

JP6 — Left Input

MISCELLANEOUS

I2S BUS SELECT

JP7 — Right Input

S23, S24, S26, S27 – I2S Bus select. Toggles between on-

board and external I2S (whether on-board SPDIF receiver is

used). All jumpers must be set the same. Jumpers on top two

Digital Inputs

JP19 — Digital Interface

ꢀPin 1 — MCLK

ꢀPin 2 — I2S_CLK

33

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pins selects external bus (JP19). Jumpers on bottom two pins

selects on-board SPDIF receiver output.

using the common SPDIF output found on most CD/DVD

players today. There are some limitations in its useage, as the

receiver will not work with digital supplies of less than 3V and

analog supplies of less than 4V. This means low analog sup-

ply voltage testing of the LM4937 must be done on the exter-

nal digital bus.

HEADPHONE OUTPUT CONFIGURATION

Jumpers S1, S2, S3, and S4 are used to configure the head-

phone outputs for either cap-coupled outputs or output ca-

pacitorless (OCL) mode in addition to the register control

internal to the LM4937 for this feature. Jumpers S1 and S3

bypass the output DC blocking capacitors when OCL mode

is required. S2 connects the center amplifer HPCOUT to the

headphone ring when in OCL mode. S4 connects the center

ring to GND when cap-coupled mode is desired. S4 must be

removed for OCL mode to function properly. Jumper settings

for each mode:

The choice of using on-board or external digital bus is made

usign jumpers S23, S24, S26, and S27 as described above.

S25 selects whether the Toslink or Coaxial SPDIF input is

used. The top two pins connects the toslink, the bottom two

connect the coaxial input.

Power on the digital side is routed through S20 (connecting

to the other digital supplies), while on the analog side it is

interrupted by S21. Both jumpers must be in place for the re-

ceiver to function. The part is already configured for I2S

standard outputs. Jumper S28 allows the DATA output to be

pulled either high or low. Default is high (jumper on right two

pins).

OCL (CD_6 = 1)

S1 = ON

S2 = ON

S3 = ON

It may be necessary to quickly toggle S29 to reset the receiver

and start it working upon initial power up.. A quick short across

S29 should clear this condition.

S4 = OFF

Cap-Coupled (CD_6 = 0)

S1 = OFF

S2 = OFF

LM4937 I²C/SPI INTERFACE SOFTWARE

S3 = OFF

Convenient graphical user interface software is available for

demonstration purposes of the LM4937. It allows for either

SPI or I²C control via either USB or parallel port connections

to a Windows computer. Control options include all mode and

output settings, volume controls, PLL and DAC setup, FIR

setting and on-the-fly adjustment by an easy to use graphical

interface. An advanced option is also present to allow direct,

register-level commands. Software is available from

www.national.com and is compatible with Windows operating

systems of Windows 98 or more (with USB support) with the

latest .NET updates from Microsoft.

S4 = ON

PLL FILTER CONFIGURATION

The LM4937 demo board comes with a simple filter setup by

connecting jumpers S5 and S6. Removing these and con-

necting jumpers S7 and S8 will allow for an alternate PLL filter

configuration to be used at R2 and C23.

ON-BOARD SPDIF RECEIVER

The SPDIF receiver present on the LM4937 demo board al-

lows quick demonstration of the capabilities of the LM4937 by

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34

Demonstration Board Schematic

35

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36

37

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Revision History

Rev

1.0

1.1

1.2

Date

Description

Initial release.

Text edits.

10/04/06

10/13/06

12/15/06

Changed the datasheet title from RF

Resistant Topology to RF Suppression.

1.3

02/09/07

Replaced curve (THD+N vs Output Power,

3V LS Out) with the curve 20166975 from

LM4934. These 2 curves have identical

performance).

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38

Physical Dimensions inches (millimeters) unless otherwise noted

36-Bump micro SMD

Order Number LM4937TL

NS Package Number TLA36LVA

X₁= 3255±30μm, X₂= 3510±30μm, X₃= 600±75μm

39

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Notes

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型号：	LM4937
厂家：	National Semiconductor
描述：	Audio Sub-System with OCL Stereo Headphone Output and RF Suppression 音频子系统与OCL立体声耳机输出和射频抑制射频
文件：	总40页 (文件大小：865K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM4937 [NSC]

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