LM5100CMA [NSC]
IC 1 A HALF BRDG BASED MOSFET DRIVER, PDSO8, MS-012AA, SOIC-8, MOSFET Driver;
| 型号： | LM5100CMA |
| 厂家： | 
National Semiconductor |
| 描述： | IC 1 A HALF BRDG BASED MOSFET DRIVER, PDSO8, MS-012AA, SOIC-8, MOSFET Driver 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总16页 (文件大小：348K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 9, 2009
LM5100A/B/C
LM5101A/B/C
3A, 2A and 1A High Voltage High-Side and Low-Side Gate
Drivers
General Description
Features
The LM5100A/B/C and LM5101A/B/C High Voltage Gate
Drivers are designed to drive both the high-side and the low-
side N-Channel MOSFETs in a synchronous buck or a half-
bridge configuration. The floating high-side driver is capable
of operating with supply voltages up to 100V. The “A” versions
provide a full 3A of gate drive while the “B” and “C” versions
provide 2A and 1A respectively. The outputs are indepen-
dently controlled with CMOS input thresholds (LM5100A/B/C)
or TTL input thresholds (LM5101A/B/C). An integrated high
voltage diode is provided to charge the high-side gate drive
bootstrap capacitor. A robust level shifter operates at high
speed while consuming low power and providing clean level
transitions from the control logic to the high-side gate driver.
Under-voltage lockout is provided on both the low-side and
the high-side power rails. These devices are available in the
standard SOIC-8 pin, PSOP-8 pin and the LLP-10 pin pack-
ages. The LM5100C and LM5101C are also available in
eMSOP-8 package.
Drives both a high-side and low-side N-Channel
■
MOSFETs
Independent high and low driver logic inputs
■
■
■
■
■
■
■
■
Bootstrap supply voltage up to 118V DC
Fast propagation times (25 ns typical)
Drives 1000 pF load with 8 ns rise and fall times
Excellent propagation delay matching (3 ns typical)
Supply rail under-voltage lockout
Low power consumption
Pin compatible with HIP2100/HIP2101
Typical Applications
Current Fed push-pull converters
■
■
■
■
Half and Full Bridge power converters
Synchronous buck converters
Two switch forward power converters
Forward with Active Clamp converters
■
Package
SOIC-8
■
■
■
■
PSOP-8
LLP-10 (4 mm x 4 mm)
eMSOP-8 (LM5100/01C)
Simplified Block Diagram
20203103
FIGURE 1.
© 2009 National Semiconductor Corporation
202031
www.national.com
Input/Output Options
Part Number
LM5100A
LM5101A
LM5100B
LM5101B
LM5100C
LM5101C
Input Thresholds
CMOS
TTL
Peak Output Current
3A
3A
2A
2A
1A
1A
CMOS
TTL
CMOS
TTL
Connection Diagrams
20203101
20203102
20203136
20203135
www.national.com
2
Ordering Information
Ordering Number
LM5100A/LM5101AM
LM5100A/LM5101AMX
LM5100A/LM5101AMR
LM5100A/LM5101AMRX
LM5100A /LM5101ASD
LM5100A/LM5101ASDX
LM5100B/LM5101BMA
LM5100B/LM5101BMAX
LM5100B/LM5101BSD
LM5100B/LM5101BSDX
LM5100C/LM5101CMA
LM5100C/LM5101CMAX
LM5100C /LM5101CSD
LM5100C/LM5101CSDX
LM5100C/LM5101CMYE
LM5100C/LM5101CMY
LM5100C/LM5101CMYX
Package Type
NSC Package Drawing
M08A
Supplied As
SOIC 8
SOIC 8
PSOP 8
PSOP 8
LLP 10
95 units shipped in anti static rails
2500 shipped in Tape & Reel
95 units shipped in anti static rails
2500 shipped in Tape & Reel
1000 shipped in Tape & Reel
4500 shipped in Tape & Reel
95 units shipped in anti static rails
2500 shipped in Tape & Reel
1000 shipped in Tape & Reel
4500 shipped in Tape & Reel
95 units shipped in anti static rails
2500 shipped in Tape & Reel
1000 shipped in Tape & Reel
4500 shipped in Tape & Reel
250 shipped in Tape & Reel
1000 shipped in Tape & Reel
3500 shipped in Tape & Reel
M08A
MRA08A
MRA08A
SDC10A
SDC10A
M08A
LLP 10
SOIC 8
SOIC 8
LLP 10
M08A
SDC10A
SDC10A
M08A
LLP 10
SOIC 8
SOIC 8
LLP 10
M08A
SDC10A
SDC10A
MUY08A
MUY08A
MUY08A
LLP 10
eMSOP-8
eMSOP-8
eMSOP-8
3
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Pin Descriptions
Pin #
Name
Description
Application Information
SOIC-8 PSOP-8 LLP-10 eMSOP-8
1
1
1
1
VDD
Positive gate drive
supply
Locally decouple to VSS using low ESR/ESL capacitor
located as close to the IC as possible.
2
2
2
2
HB
High-side gate driver Connect the positive terminal of the bootstrap capacitor
bootstrap rail
to HB and the negative terminal to HS. The bootstrap
capacitor should be placed as close to the IC as
possible.
3
4
5
3
4
5
3
4
7
3
4
5
HO
HS
HI
High-side gate driver Connect to the gate of high-side MOSFET with a short,
output
low inductance path.
High-side MOSFET
source connection
Connect to the bootstrap capacitor negative terminal
and the source of the high-side MOSFET.
High-side driver control The LM5100A/B/C inputs have CMOS type thresholds.
input
The LM5101A/B/C inputs have TTL type thresholds.
Unused inputs should be tied to ground and not left
open.
6
6
8
6
LI
Low-side driver control The LM5100A/B/C inputs have CMOS type thresholds.
input
The LM5101A/B/C inputs have TTL type thresholds.
Unused inputs should be tied to ground and not left
open.
7
8
7
8
9
7
8
VSS
LO
Ground return
All signals are referenced to this ground.
10
Low-side gate driver
output
Connect to the gate of the low-side MOSFET with a
short, low inductance path.
EP
EP
EP
EP (LLP and PSOP and eMSOP
packages)
Solder to the ground plane under the IC to aid in heat
dissipation.
Note: For LLP-10 and eMSOP-8 package, it is recommended that the exposed pad on the bottom of the package is soldered to ground plane on the
PC board, and that ground plane should extend out from beneath the IC to help dissipate heat. For LLP-10 package, pins 5 and 6 have no connection.
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4
Junction Temperature
Storage Temperature Range
ESD Rating HBM (Note 2)
+150°C
−55°C to +150°C
2 kV
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
VDD to VSS
HB to HS
−0.3V to +18V
−0.3V to +18V
Conditions
VDD
HS
+9V to +14V
−1V to 100V
VHS +8V to VHS +14V
< 50 V/ns
LI or HI Input
LO Output
−0.3V to VDD +0.3V
−0.3V to VDD +0.3V
VHS −0.3V to VHB +0.3V
−5V to +100V
HB
HO Output
HS Slew Rate
Junction Temperature
HS to VSS (Note 6)
HB to VSS
−40°C to +125°C
118V
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to
+125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the
most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB
=
12V, VSS = VHS = 0V, No Load on LO or HO (Note 4).
Symbol
Parameter
Conditions
LI = HI = 0V
Min
Typ
Max
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current, LM5100A/B/C
VDD Quiescent Current, LM5101A/B/C
VDD Operating Current
0.1
0.25
2.0
0.2
0.4
3
mA
LI = HI = 0V
f = 500 kHz
LI = HI = 0V
f = 500 kHz
HS = HB = 100V
f = 500 kHz
IDDO
IHB
mA
mA
mA
µA
Total HB Quiescent Current
0.06
1.6
0.2
3
IHBO
IHBS
IHBSO
Total HB Operating Current
HB to VSS Current, Quiescent
HB to VSS Current, Operating
0.1
10
0.4
mA
INPUT PINS
VIL
Input Voltage Threshold LM5100A/B/C
Rising Edge
Rising Edge
4.5
1.3
5.4
1.8
500
50
6.3
2.3
V
VIL
Input Voltage Threshold LM5101A/B/C
Input Voltage Hysteresis LM5100A/B/C
Input Voltage Hysteresis LM5101A/B/C
Input Pulldown Resistance
V
VIHYS
VIHYS
RI
mV
mV
kΩ
100
6.0
5.7
200
400
7.4
7.1
UNDER VOLTAGE PROTECTION
VDDR
VDDH
VHBR
VHBH
VDD Rising Threshold
VDD Threshold Hysteresis
HB Rising Threshold
6.9
0.5
6.6
0.4
V
V
V
V
HB Threshold Hysteresis
BOOT STRAP DIODE
VDL
VDH
RD
Low-Current Forward Voltage
High-Current Forward Voltage
IVDD-HB = 100 µA
IVDD-HB = 100 mA
0.52
0.8
0.85
1
V
V
Dynamic Resistance LM5100A/B/C, LM5101A/B/ IVDD-HB = 100 mA
C
1.0
1.65
Ω
LO & HO GATE DRIVER
VOL
VOH
IOHL
Low-Level Output Voltage LM5100A/LM5101A IHO = ILO = 100 mA
0.12
0.16
0.28
0.24
0.28
0.60
3
0.25
0.4
Low-Level Output Voltage LM5100B/LM5101B
V
V
A
Low-Level Output Voltage LM5100C/LM5101C
0.65
0.45
0.60
1.10
High-Level Output Voltage LM5100A/LM5101A IHO = ILO = 100 mA
VOH = VDD– LO or
VOH = HB - HO
High-Level Output Voltage LM5100B/LM5101B
High-Level Output Voltage LM5100C/LM5101C
Peak Pullup Current LM5100A/LM5101A
Peak Pullup Current LM5100B/LM5101B
Peak Pullup Current LM5100C/LM5101C
HO, LO = 0V
2
1
5
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Symbol
Parameter
Conditions
HO, LO = 12V
Min
Typ
3
Max
Units
IOLL
Peak Pulldown Current LM5100A/LM5101A
Peak Pulldown Current LM5100B/LM5101B
Peak Pulldown Current LM5100C/LM5101C
2
A
1
THERMAL RESISTANCE
Junction to Ambient
SOIC-8
170
40
θJA
LLP-10 (Note 3)
PSOP-8
°C/W
40
eMSOP-8 (Note 3)
80
Switching Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to
+125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the
most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB
=
12V, VSS = VHS = 0V, No Load on LO or HO (Note 4).
Symbol
tLPHL
Parameter
Conditions
Min
Typ
Max
45
Units
LO Turn-Off Propagation Delay
LM5100A/B/C
LI Falling to LO Falling
20
ns
ns
ns
LO Turn-Off Propagation Delay
LM5101A/B/C
22
20
26
20
22
20
26
1
56
45
56
45
56
45
56
10
10
10
10
tLPLH
tHPHL
tHPLH
tMON
tMOFF
LO Turn-On Propagation Delay
LM5100A/B/C
LI Rising to LO Rising
HI Falling to HO Falling
HI Rising to HO Rising
LO Turn-On Propagation Delay
LM5101A/B/C
HO Turn-Off Propagation Delay
LM5100A/B/C
HO Turn-Off Propagation Delay
LM5101A/B/C
LO Turn-On Propagation Delay
LM5100A/B/C
ns
ns
LO Turn-On Propagation Delay
LM5101A/B/C
Delay Matching: LO on & HO off
LM5100A/B/C
Delay Matching: LO on & HO off
LM5101A/B/C
4
Delay Matching: LO off & HO on
LM5100A/B/C
1
ns
ns
ns
Delay Matching: LO on & HO off
LM5101A/B/C
4
8
tRC, tFC
tR
Either Output Rise/Fall Time
CL = 1000 pF
Output Rise Time (3V to 9V) LM5100A/ CL = 0.1 µF
LM5101A
430
Output Rise Time (3V to 9V) LM5100B/
LM5101B
570
990
260
430
715
Output Rise Time (3V to 9V) LM5100C/
LM5101C
tF
Output Fall Time (3V to 9V) LM5100A/
LM5101A
CL = 0.1 µF
Output Fall Time (3V to 9V) LM5100B/
LM5101B
ns
Output Fall Time (3V to 9V) LM5100C/
LM5101C
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6
Symbol
tPW
Parameter
Conditions
Min
Typ
Max
Units
Minimum Input Pulse Width that Changes
the Output
50
ns
tBS
Bootstrap Diode Reverse Recovery Time IF = 100 mA,
IR = 100 mA
37
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. 2 kV for all pins except Pin 2, Pin 3 and Pin 4 which are
rated at 1000V for HBM and 100V for MM.
Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power
planes embedded in PCB. See Application Note AN-1187.
Note 4: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 5: The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment.
Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not exceed -1V.
However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur,
the HS voltage must never be more negative than VDD-15V. For example if VDD = 10V, the negative transients at HS must not exceed -5V.
Typical Performance Characteristics
Peak Sourcing Current vs VDD
Peak Sinking Current vs VDD
20203128
20203127
Sink Current vs Output Voltage
Source Current vs Output Voltage
20203129
20203130
7
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LM5100A/B/C IDD vs Frequency
LM5101A/B/C IDD vs Frequency
20203110
20203109
Operating Current vs Temperature
IHB vs Frequency
20203111
20203114
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
20203119
20203118
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8
Undervoltage Rising Thresholds vs Temperature
Undervoltage Threshold Hysteresis vs Temperature
20203122
20203117
Bootstrap Diode Forward Voltage
LM5100A/B/C Input Threshold vs Temperature
20203123
20203115
LM5101A/B/C Input Threshold vs Temperature
LM5100A/B/C Input Threshold vs VDD
20203125
20203124
9
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LM5101A/B/C Input Threshold vs VDD
LM5100A/B/C Propagation Delay vs Temperature
20203126
20203112
LM5101A/B/C Propagation Delay vs Temperature
LO & HO Gate Drive - High Level Output Voltage vs
Temperature
20203113
20203120
LO & HO Gate Drive - Low Level Output Voltage vs
Temperature
LO & HO Gate Drive - Output High Voltage vs VDD
20203131
20203121
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10
LO & HO Gate Drive - Output Low Voltage vs VDD
20203132
Timing Diagram
20203104
FIGURE 2.
a) The first priority in designing grounding connections
is to confine the high peak currents that charge and
discharge the MOSFET gate into a minimal physical
area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the
MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
b) The second high current path includes the bootstrap
capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET
body diode. The bootstrap capacitor is recharged on a
cycle-by-cycle basis through the bootstrap diode from
the ground referenced VDD bypass capacitor. The
recharging occurs in a short time interval and involves
high peak current. Minimizing this loop length and area
on the circuit board is important to ensure reliable
operation.
Layout Considerations
The optimum performance of high and low-side gate drivers
cannot be achieved without taking due considerations during
circuit board layout. Following points are emphasized.
1. Low ESR / ESL capacitors must be connected close to
the IC, between VDD and VSS pins and between the HB
and HS pins to support the high peak currents being
drawn from VDD during turn-on of the external MOSFET.
2. To prevent large voltage transients at the drain of the top
MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch
node (HS pin), the parasitic inductances in the source of
top MOSFET and in the drain of the bottom MOSFET
(synchronous rectifier) must be minimized.
4. Grounding Considerations:
11
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Diode Power Dissipation VIN = 50V
Power Dissipation Considerations
The total IC power dissipation is the sum of the gate driver
losses and the bootstrap diode losses. The gate driver losses
are related to the switching frequency (f), output load capac-
itance on LO and HO (CL), and supply voltage (VDD) and can
be roughly calculated as:
2
PDGATES = 2 • f • CL • VDD
There are some additional losses in the gate drivers due to
the internal CMOS stages used to buffer the LO and HO out-
puts. The following plot shows the measured gate driver
power dissipation versus frequency and load capacitance. At
higher frequencies and load capacitance values, the power
dissipation is dominated by the power losses driving the out-
put loads and agrees well with the above equation. This plot
can be used to approximate the power losses due to the gate
drivers.
20203106
Gate Driver Power Dissipation (LO + HO)
VDD = 12V, Neglecting Diode Losses
20203105
The bootstrap diode power loss is the sum of the forward bias
power loss that occurs while charging the bootstrap capacitor
and the reverse bias power loss that occurs during reverse
recovery. Since each of these events happens once per cycle,
the diode power loss is proportional to frequency. Larger ca-
pacitive loads require more energy to recharge the bootstrap
capacitor resulting in more losses. Higher input voltages
(VIN) to the half bridge result in higher reverse recovery loss-
es. The following plot was generated based on calculations
and lab measurements of the diode recovery time and current
under several operating conditions. This can be useful for ap-
proximating the diode power dissipation.
The total IC power dissipation can be estimated from the pre-
vious plots by summing the gate drive losses with the boot-
strap diode losses for the intended application.
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12
Physical Dimensions inches (millimeters) unless otherwise noted
Controlling dimension is inch. Values in [ꢀ] are millimeters.
Notes: Unless otherwise specified.
Standard lead finish to be 200 microinches/5.08 micrometers minimum lead/tin (solder) on copper.
1.
Dimension does not include mold flash.
2.
Reference JEDEC registration MS-012, Variation AA, dated May 1990.
3.
SOIC-8 Outline Drawing
NS Package Number M08A
PSOP-8 Outline Drawing
NS Package Number MRA08A
13
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Notes: Unless otherwise specified.
For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web page (www.national.com).
1.
Maximum allowable metal burr on lead tips at the package edges is 76 microns.
2.
No JEDEC registration as of May 2003.
3.
LLP-10 Outline Drawing
NS Package Number SDC10A
eMSOP-8 Outline Drawing
NS Package Number MUY08A
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14
Notes
15
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Notes
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