LM5106 [NSC]
100V Half Bridge Gate Driver with Programmable; 100V半桥栅极驱动器，具有可编程
| 型号： | LM5106 |
| 厂家： | 
National Semiconductor |
| 描述： | 100V Half Bridge Gate Driver with Programmable |
| 文件： | 总12页 (文件大小：715K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2006
LM5106
100V Half Bridge Gate Driver with Programmable
Dead-Time
n 1.2A peak output source current
n Bootstrap supply voltage range up to 118V DC
n Single TTL compatible Input
n Programmable turn-on delays (Dead-time)
n Enable Input pin
n Fast turn-off propagation delays (32ns typical)
n Drives 1000pF with 15ns rise and 10ns fall time
n Supply rail under-voltage lockout
n Low power consumption
General Description
The LM5106 is a high voltage gate driver designed to drive
both the high side and low side N-Channel MOSFETs in a
synchronous buck or half bridge configuration. The floating
high side driver is capable of working with rail voltages up to
100V. The single control input is compatible with TTL signal
levels and a single external resistor programs the switching
transition dead-time through tightly matched turn-on delay
circuits. The robust level shift technology operates at high
speed while consuming low power and provides clean output
transitions. Under-voltage lockout disables the gate driver
when either the low side or the bootstrapped high side
supply voltage is below the operating threshold. The LM5106
is offered in the MSOP-10 or thermally enhanced 10-pin LLP
plastic package.
Typical Applications
n Solid State motor drives
n Half and Full Bridge power converters
n Two switch forward power converters
Features
Package
n Drives both a high side and low side N-channel
MOSFET
n LLP-10 (4 mm x 4 mm)
n MSOP-10
n 1.8A peak output sink current
Simplified Block Diagram
20175902
FIGURE 1.
© 2006 National Semiconductor Corporation
DS201759
www.national.com
Connection Diagram
20175901
10-Lead MSOP or LLP
See NS Number MUB10A, SDC10A
Ordering Information
Ordering Number
Package Type
NSC Package Drawing
Supplied As
LM5106MM
MSOP-10
MUB10A
MUB10A
SDC10A
SDC10A
1000 shipped as Tape & Reel
3500 shipped as Tape & Reel
1000 shipped as Tape & Reel
4500 shipped as Tape & Reel
LM5106MMX
LM5106SD
MSOP-10
LLP-10
LM5106SDX
LLP-10
Pin Descriptions
Pin
Name
Description
Application Information
1
VDD
Positive gate drive supply
Decouple VDD to VSS using a low ESR/ESL capacitor, placed as
close to the IC as possible.
2
HB
High side gate driver
bootstrap rail
Connect the positive terminal of bootstrap capacitor to the HB pin
and connect negative terminal to HS. The Bootstrap capacitor
should be placed as close to IC as possible.
3
4
HO
HS
High side gate driver
output
Connect to the gate of high side N-MOS device through a short,
low inductance path.
High side MOSFET source
connection
Connect to the negative terminal of the bootststrap capacitor and to
the source of the high side N-MOS device.
5
6
NC
Not Connected
Dead-time programming
pin
RDT
A resistor from RDT to VSS programs the turn-on delay of both the
high and low side MOSFETs. The resistor should be placed close
to the IC to minimize noise coupling from adjacent PC board traces.
TTL compatible threshold with hysteresis. LO and HO are held in
the low state when EN is low.
7
8
EN
IN
Logic input for driver
Disable/Enable
Logic input for gate driver
TTL compatible threshold with hysteresis. The high side MOSFET
is turned on and the low side MOSFET turned off when IN is high.
All signals are referenced to this ground.
9
VSS
LO
Ground return
10
Low side gate driver output
Connect to the gate of the low side N-MOS device with a short, low
inductance path.
NA
EP
Exposed Pad
The exposed pad has no electrical contact. Connect to system
ground plane for reduced thermal resistance.
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range
ESD Rating HBM
(Note 2)
–55˚C to +150˚C
1.5 kV
VDD to VSS
–0.3V to +18V
–0.3V to +18V
–0.3V to VDD + 0.3V
–0.3V to VDD + 0.3V
HS – 0.3V to HB + 0.3V
−5V to +100V
Recommended Operating
Conditions
HB to HS
IN and EN to VSS
LO to VSS
VDD
+8V to +14V
HS (Note 6)
–1V to 100V
HO to VSS
HB
HS + 8V to HS + 14V
HS to VSS (Note 6)
HB to VSS
<
HS Slew Rate
Junction Temperature
50V/ns
118V
–40˚C to +125˚C
RDT to VSS
–0.3V to 5V
Junction Temperature
+150˚C
Electrical Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface
type apply over the full operating junction temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS =
0V, EN = 5V. No load on LO or HO. RDT= 100kΩ(Note 4).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current
VDD Operating Current
IN = EN = 0V
0.34
2.1
0.6
3.5
0.2
3
mA
mA
mA
mA
µA
IDDO
IHB
f = 500 kHz
Total HB Quiescent Current
Total HB Operating Current
HB to VSS Current, Quiescent
HB to VSS Current, Operating
IN = EN = 0V
f = 500 kHz
0.06
1.5
IHBO
IHBS
IHBSO
HS = HB = 100V
f = 500 kHz
0.1
10
0.5
mA
INPUT IN and EN
VIL
Low Level Input Voltage Threshold
0.8
1.8
1.8
200
V
V
VIH
Rpd
High Level Input Voltage Threshold
2.2
Input Pulldown Resistance Pin IN and EN
100
500
kΩ
DEAD-TIME CONTROLS
VRDT
IRDT
Nominal Voltage at RDT
RDT Pin Current Limit
2.7
3
3.3
V
RDT = 0V
0.75
1.5
2.25
mA
UNDER VOLTAGE PROTECTION
VDDR
VDDH
VHBR
VHBH
VDD Rising Threshold
VDD Threshold Hysteresis
HB Rising Threshold
6.2
5.9
6.9
0.5
6.6
0.4
7.6
7.3
V
V
V
V
HB Threshold Hysteresis
LO GATE DRIVER
VOLL
VOHL
Low-Level Output Voltage
ILO = 100 mA
ILO = –100 mA,
VOHL = VDD – VLO
LO = 0V
0.21
0.5
0.4
V
V
High-Level Output Voltage
0.85
IOHL
IOLL
Peak Pullup Current
1.2
1.8
A
A
Peak Pulldown Current
LO = 12V
HO GATE DRIVER
VOLH
VOHH
Low-Level Output Voltage
IHO = 100 mA
IHO = –100 mA,
VOHH = HB – HO
HO = 0V
0.21
0.5
0.4
V
V
High-Level Output Voltage
0.85
IOHH
IOLH
Peak Pullup Current
1.2
1.8
A
A
Peak Pulldown Current
HO = 12V
THERMAL RESISTANCE
θJA Junction to Ambient
(Note 3), (Note 5)
40
˚C/W
3
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Switching Characteristics Specifications in standard typeface are for TJ = +25˚C, and those in boldface
type apply over the full operating junction temperature range. Unless otherwise specified, VDD = HB = 12V, VSS = HS =
0V, No Load on LO or HO (Note 4).
Symbol
tLPHL
Parameter
Conditions
Min
Typ
32
Max
56
Units
ns
Lower Turn-Off Propagation Delay
Upper Turn-Off Propagation Delay
Lower Turn-On Propagation Delay
Upper Turn-On Propagation Delay
Lower Turn-On Propagation Delay
Upper Turn-On Propagation Delay
Enable and Shutdown propagation delay
Dead-time LO OFF to HO ON & HO OFF
to LO ON
tHPHL
tLPLH
tHPLH
tLPLH
tHPLH
32
56
ns
RDT = 100k
400
450
85
520
570
115
115
36
640
690
160
160
ns
RDT = 100k
RDT = 10k
RDT = 10k
ns
ns
85
ns
t
en, tsd
ns
DT1, DT2
RDT = 100k
RDT = 10k
510
86
µs
ns
MDT
tR
Dead-time matching
RDT = 100k
CL = 1000pF
CL = 1000pF
50
ns
Either Output Rise Time
Either Output Fall Time
15
ns
tF
10
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Pin 2, Pin 3 and Pin 4 are rated at 500V.
Note 3: 4 layer board with Cu finished thickness 1.5/1.0/1.0/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power
planes embedded in PCB. See Application Note AN-1187.
Note 4: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 5: The θ is not a constant for the package and depends on the printed circuit board design and the operating conditions.
JA
Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V.
However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently.
If negative transients occur on HS, the HS voltage must never be more negative than V - 15V. For example, if V = 10V, the negative transients at HS must not
DD
DD
exceed -5V.
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4
Typical Performance Characteristics
VDD Operating Current vs Frequency
Operating Current vs Temperature
20175911
20175910
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
20175913
20175912
HB Operating Current vs Frequency
HO & LO Peak Output Current vs Output Voltage
20175917
20175916
5
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Typical Performance Characteristics (Continued)
Undervoltage Rising Threshold vs Temperature
Undervoltage Hysteresis vs Temperature
20175919
20175918
LO & HO - Low Level Output Voltage vs Temperature
LO & HO - High Level Output Voltage vs Temperature
20175921
20175920
Input Threshold vs Temperature
Dead-Time vs RT Resistor Value
20175914
20175922
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6
Typical Performance Characteristics (Continued)
Dead-Time vs Temperature (RT = 10k)
Dead-Time vs Temperature (RT = 100k)
20175926
20175927
7
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Timing Diagrams
20175903
FIGURE 2. LM5106 Input - Output Waveforms
20175904
FIGURE 3. LM5106 Switching Time Definitions: tLPLH, tLPHL, tHPLH, tHPHL
100ns to 600ns. The wide dead-time programming range
provides the flexibility to optimize drive signal timing for a
wide range of MOSFETS and applications.
The RDT pin is biased at 3V and current limited to 1 mA
maximum programming current. The time delay generator
will accommodate resistor values from 5k to 100k with a
dead-time time that is proportional to the RDT resistance.
Grounding the RDT pin programs the LM5106 to drive both
outputs with minimum dead-time.
20175930
FIGURE 4. LM5106 Enable: tsd
STARTUP AND UVLO
Both top and bottom drivers include under-voltage lockout
(UVLO) protection circuitry which monitors the supply volt-
age (VDD) and bootstrap capacitor voltage (HB – HS) inde-
pendently. The UVLO circuit inhibits each driver until suffi-
cient supply voltage is available to turn-on the external
MOSFETs, and the UVLO hysteresis prevents chattering
during supply voltage transitions. When the supply voltage is
applied to the VDD pin of the LM5106, the top and bottom
gates are held low until VDD exceeds the UVLO threshold,
typically about 6.9V. Any UVLO condition on the bootstrap
capacitor will disable only the high side output (HO).
20175931
FIGURE 5. LM5106 Dead-time: DT
LAYOUT CONSIDERATIONS
The optimum performance of high and low side gate drivers
cannot be achieved without taking due considerations during
circuit board layout. The following points are emphasized:
Operational Notes
The LM5106 is a single PWM input Gate Driver with Enable
that offers a programmable dead-time. The dead-time is set
with a resistor at the RDT pin and can be adjusted from
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8
POWER DISSIPATION CONSIDERATIONS
Operational Notes (Continued)
The total IC power dissipation is the sum of the gate driver
losses and the bootstrap diode losses. The gate driver
losses are related to the switching frequency (f), output load
capacitance on LO and HO (CL), and supply voltage (VDD
and can be roughly calculated as:
1. Low ESR / ESL capacitors must be connected close to
the IC between VDD and VSS pins and between HB and
HS pins to support high peak currents being drawn from
VDD and HB during the turn-on of the external MOS-
FETs.
)
2
PDGATES = 2 • f • CL • VDD
2. To prevent large voltage transients at the drain of the top
MOSFET, a low ESR electrolytic capacitor and a good
quality ceramic capacitor must be connected between
the MOSFET drain and ground (VSS).
There are some additional losses in the gate drivers due to
the internal CMOS stages used to buffer the LO and HO
outputs. The following plot shows the measured gate driver
power dissipation versus frequency and load capacitance. At
higher frequencies and load capacitance values, the power
dissipation is dominated by the power losses driving the
output loads and agrees well with the above equation. This
plot can be used to approximate the power losses due to the
gate drivers.
3. In order to avoid large negative transients on the switch
node (HS) pin, the parasitic inductances between the
source of the top MOSFET and the drain of the bottom
MOSFET (synchronous rectifier) must be minimized.
4. Grounding considerations:
a) The first priority in designing grounding connections is
to confine the high peak currents that charge and dis-
charge the MOSFET gates to a minimal physical area.
This will decrease the loop inductance and minimize
noise issues on the gate terminals of the MOSFETs. The
gate driver should be placed as close as possible to the
MOSFETs.
Gate Driver Power Dissipation (LO + HO)
VCC = 12V
b) The second consideration is the high current path that
includes the bootstrap capacitor, the bootstrap diode,
the local ground referenced bypass capacitor, and the
low side MOSFET body diode. The bootstrap capacitor
is recharged on a cycle-by-cycle basis through the boot-
strap diode from the ground referenced VDD bypass
capacitor. The recharging occurs in a short time interval
and involves high peak current. Minimizing this loop
length and area on the circuit board is important to
ensure reliable operation.
5. The resistor on the RDT pin must be placed very close to
the IC and separated from the high current paths to
avoid noise coupling to the time delay generator which
could disrupt timer operation.
20175905
HS TRANSIENT VOLTAGES BELOW GROUND
The HS node will always be clamped by the body diode of
the lower external FET. In some situations, board resis-
tances and inductances can cause the HS node to tran-
siently swing several volts below ground. The HS node can
swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling
HO more than -0.3V below HS can activate parasitic
transistors resulting in excessive current flow from the
HB supply, possibly resulting in damage to the IC. The
same relationship is true with LO and VSS. If necessary,
a Schottky diode can be placed externally between HO
and HS or LO and GND to protect the IC from this type
of transient. The diode must be placed as close to the IC
pins as possible in order to be effective.
2. HB to HS operating voltage should be 15V or less.
Hence, if the HS pin transient voltage is -5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
3. Low ESR bypass capacitors from HB to HS and from
VCC to VSS are essential for proper operation. The
capacitor should be located at the leads of the IC to
minimize series inductance. The peak currents from LO
and HO can be quite large. Any inductances in series
with the bypass capacitor will cause voltage ringing at
the leads of the IC which must be avoided for reliable
operation.
9
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Operational Notes (Continued)
20175908
FIGURE 6. LM5106 Driving MOSFETs Connected in Half-Bridge Configuration
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10
Physical Dimensions inches (millimeters) unless otherwise noted
MSOP-10 Outline Drawing
NS Package Number MUB10A
Notes: Unless otherwise specified
1. Standard lead finish to be 200 microinches/5.00 micrometers minimum tin/lead (solder) on copper.
2. Pin 1 identification to have half of full circle option.
3. No JEDEC registration as of Feb. 2000.
LLP-10 Outline Drawing
NS Package Number SDC10A
11
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Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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