LM5109BMAX [NSC]
High Voltage 1A Peak Half Bridge Gate Driver; 高电压1A峰值半桥栅极驱动器
| 型号： | LM5109BMAX |
| 厂家： | 
National Semiconductor |
| 描述： | High Voltage 1A Peak Half Bridge Gate Driver |
| 文件： | 总10页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2007
LM5109B
High Voltage 1A Peak Half Bridge Gate Driver
Fast propagation times (30 ns typical)
■
General Description
Drives 1000 pF load with 15ns rise and fall times
Excellent propagation delay matching (2 ns typical)
Supply rail under-voltage lockout
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■
■
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The LM5109B is a cost effective, high voltage gate driver de-
signed to drive both the high-side and the low-side N-Channel
MOSFETs in a synchronous buck or a half bridge configura-
tion. The floating high-side driver is capable of working with
rail voltages up to 90V. The outputs are independently con-
trolled with TTL compatible input thresholds. The robust level
shift technology operates at high speed while consuming low
power and providing clean level transitions from the control
input logic to the high-side gate driver. Under-voltage lockout
is provided on both the low-side and the high-side power rails.
The device is available in the SOIC-8 and the thermally en-
hanced LLP-8 packages.
Low power consumption
Pin compatible with ISL6700
Typical Applications
Current Fed push-pull converters
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Half and Full Bridge power converters
Solid state motor drives
Two switch forward power converters
Features
Package
Drives both a high-side and low-side N-Channel MOSFET
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■
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SOIC-8
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1A peak output current (1.0A sink / 1.0A source)
LLP-8 (4 mm x 4 mm)
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Independent TTL compatible inputs
Bootstrap supply voltage to 108V DC
■
Simplified Block Diagram
20211901
FIGURE 1.
© 2007 National Semiconductor Corporation
202119
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Connection Diagrams
20211902
20211903
FIGURE 2.
Ordering Information
Ordering Number
LM5109BMA
Package Type
NSC Package Drawing
Supplied As
95 Units in anti static rails
2500 Units on Tape & Reel
1000 Units on Tape & Reel
4500 Units on Tape & Reel
SOIC-8
SOIC-8
LLP-8
M08A
M08A
LM5109BMAX
LM5109BSD
LM5109BSDX
SDC08A
SDC08A
LLP-8
Pin Descriptions
Pin #
Name
Description
Application Information
SO-8
LLP-8
1
1
VDD
HI
Positive gate drive supply
Locally decouple to VSS using low ESR/ESL capacitor located as
close to IC as possible.
2
3
2
3
High side control input
Low side control input
The HI input is compatible with TTL input thresholds. Unused HI
input should be tied to ground and not left open.
LI
The LI input is compatible with TTL input thresholds. Unused LI input
should be tied to ground and not left open.
4
5
6
4
5
6
VSS
LO
HS
Ground reference
All signals are referenced to this ground.
Low side gate driver output
High side source connection
Connect to the gate of the low-side N-MOS device.
Connect to the negative terminal of the bootstrap capacitor and to
the source of the high-side N-MOS device.
7
8
7
8
HO
HB
High side gate driver output
Connect to the gate of the high-side N-MOS device.
High side gate driver positive
supply rail
Connect the positive terminal of the bootstrap capacitor to HB and
the negative terminal of the bootstrap capacitor to HS. The bootstrap
capacitor should be placed as close to IC as possible.
Note: For LLP-8 package it is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PCB and the
ground plane should extend out from underneath the package to improve heat dissipation.
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2
Junction Temperature
Storage Temperature Range
ESD Rating HBM (Note 2)
-40°C to +150°C
−55°C to +150°C
1.5 kV
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
VDD to VSS
-0.3V to 18V
−0.3V to 18V
Conditions
HB to HS
VDD
8V to 14V
−1V to 90V
VHS +8V to VHS +14V
< 50 V/ns
LI or HI to VSS
LO to VSS
−0.3V to VDD +0.3V
−0.3V to VDD +0.3V
VHS −0.3V to VHB +0.3V
HS (Note 6)
HB
HO to VSS
HS Slew Rate
Junction Temperature
HS to VSS (Note 6)
HB to VSS
−5V to 90V
108V
−40°C to +125°C
Electrical Characteristics
Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (Note 4).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current
LI = HI = 0V
f = 500 kHz
LI = HI = 0V
f = 500 kHz
0.3
1.8
0.6
2.9
0.2
2.8
10
mA
mA
mA
mA
µA
IDDO
IHB
VDD Operating Current
Total HB Quiescent Current
Total HB Operating Current
HB to VSS Current, Quiescent
HB to VSS Current, Operating
0.06
1.4
IHBO
IHBS
IHBSO
VHS = VHB = 90V
f = 500 kHz
0.1
0.5
mA
INPUT PINS LI and HI
VIL
VIH
RI
Low Level Input Voltage Threshold
0.8
100
6.0
5.7
1.8
1.8
V
V
High Level Input Voltage Threshold
Input Pulldown Resistance
2.2
200
500
kΩ
UNDER VOLTAGE PROTECTION
VDDR
VDDH
VHBR
VHBH
VDD Rising Threshold
VDD Threshold Hysteresis
HB Rising Threshold
VDDR = VDD - VSS
6.7
0.5
6.6
0.4
7.4
7.1
V
V
V
V
VHBR = VHB - VHS
HB Threshold Hysteresis
LO GATE DRIVER
VOLL Low-Level Output Voltage
ILO = 100 mA
0.38
0.72
0.65
1.20
V
V
VOHL = VLO – VSS
VOHL
High-Level Output Voltage
ILO = −100 mA,
VOHL = VDD– VLO
IOHL
IOLL
Peak Pullup Current
VLO = 0V
1.0
1.0
A
A
Peak Pulldown Current
VLO = 12V
HO GATE DRIVER
VOLH Low-Level Output Voltage
IHO = 100 mA
0.38
0.72
0.65
1.20
V
V
VOLH = VHO– VHS
VOHH
High-Level Output Voltage
IHO = −100 mA
VOHH = VHB– VHO
IOHH
IOLH
Peak Pullup Current
VHO = 0V
1.0
1.0
A
A
Peak Pulldown Current
VHO = 12V
THERMAL RESISTANCE
Junction to Ambient
SOIC-8 (Note 3), (Note 5)
LLP-8 (Note 3), (Note 5)
160
40
θJA
°C/W
3
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Switching Characteristics
Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO.
Symbol
tLPHL
Parameter
Conditions
Min
Typ
Max
56
Units
Lower Turn-Off Propagation Delay (LI
Falling to LO Falling)
30
ns
tHPHL
tLPLH
tHPLH
tMON
tMOFF
Upper Turn-Off Propagation Delay (HI
Falling to HO Falling)
30
32
32
2
56
56
56
15
ns
ns
ns
ns
Lower Turn-On Propagation Delay (LI
Rising to LO Rising)
Upper Turn-On Propagation Delay (HI
Rising to HO Rising)
Delay Matching: Lower Turn-On and
Upper Turn-Off
Delay Matching: Lower Turn-Off and
Upper Turn-On
2
15
ns
ns
ns
tRC, tFC
tPW
Either Output Rise/Fall Time
CL = 1000 pF
15
50
-
Minimum Input Pulse Width that Changes
the Output
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power
planes embedded in PCB. See Application Note AN-1187.
Note 4: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 5: The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.
Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V.
However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently.
If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD = 10V, the negative transients at HS must
not exceed -5V.
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4
Typical Performance Characteristics
VDD Operating Current vs Frequency
HB Operating Current vs Frequency
20211905
20211904
Operating Current vs Temperature
Quiescent Current vs Temperature
20211906
20211907
Quiescent Current vs Voltage
Propagation Delay vs Temperature
20211909
20211908
5
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LO and HO High Level Output Voltage vs Temperature
LO and HO Low Level Output Voltage vs Temperature
20211910
20211911
Undervoltage Rising Thresholds vs Temperature
Undervoltage Hysteresis vs Temperature
20211914
20211915
Input Thresholds vs Temperature
Input Thresholds vs Supply Voltage
20211917
20211916
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6
Timing Diagram
20211918
FIGURE 3.
and involves high peak current. Minimizing this loop
length and area on the circuit board is important to ensure
reliable operation.
Layout Considerations
Optimum performance of high and low-side gate drivers can-
not be achieved without taking due considerations during
circuit board layout. The following points are emphasized:
HS Transient Voltages Below
Ground
The HS node will always be clamped by the body diode of the
lower external FET. In some situations, board resistances and
inductances can cause the HS node to transiently swing sev-
eral volts below ground. The HS node can swing below
ground provided:
1. HS must always be at a lower potential than HO. Pulling
HO more than -0.3V below HS can activate parasitic
transistors resulting in excessive current flow from the
HB supply, possibly resulting in damage to the IC. The
same relationship is true with LO and VSS. If necessary,
a Schottky diode can be placed externally between HO
and HS or LO and GND to protect the IC from this type
of transient. The diode must be placed as close to the IC
pins as possible in order to be effective.
1. Low ESR / ESL capacitors must be connected close to
the IC between VDD and VSS pins and between HB and
HS pins to support high peak currents being drawn from
VDD and HB during the turn-on of the external
MOSFETs.
2. To prevent large voltage transients at the drain of the top
MOSFET, a low ESR electrolytic capacitor and a good
quality ceramic capacitor must be connected between
the MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch
node (HS) pin, the parasitic inductances between the
source of the top MOSFET and the drain of the bottom
MOSFET (synchronous rectifier) must be minimized.
4. Grounding considerations:
a) The first priority in designing grounding connections is
to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area.
This will decrease the loop inductance and minimize
noise issues on the gate terminals of the MOSFETs. The
gate driver should be placed as close as possible to the
MOSFETs.
b) The second consideration is the high current path that
includes the bootstrap capacitor, the bootstrap diode, the
local ground referenced bypass capacitor, and the low-
side MOSFET body diode. The bootstrap capacitor is
recharged on a cycle-by-cycle basis through the
bootstrap diode from the ground referenced VDD bypass
capacitor. The recharging occurs in a short time interval
2. HB to HS operating voltage should be 15V or less.
Hence, if the HS pin transient voltage is -5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
3. Low ESR bypass capacitors from HB to HS and from
VDD to VSS are essential for proper operation. The
capacitor should be located at the leads of the IC to
minimize series inductance. The peak currents from LO
and HO can be quite large. Any series inductances with
the bypass capacitor will cause voltage ringing at the
leads of the IC which must be avoided for reliable
operation.
7
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Physical Dimensions inches (millimeters) unless otherwise noted
Controlling dimension is inch. Values in [ꢀ] are millimeters.
Notes: Unless otherwise specified.
Standard lead finish to be 200 microinches/5.08 micrometers minimum lead/tin (solder) on copper.
1.
Dimension does not include mold flash.
2.
Reference JEDEC registration MS-012, Variation AA, dated May 1990.
3.
SOIC-8 Outline Drawing
NS Package Number M08A
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8
Notes: Unless otherwise specified.
For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web page (www.national.com).
1.
Maximum allowable metal burr on lead tips at the package edges is 76 microns.
2.
No JEDEC registration as of May 2003.
3.
LLP-8 Outline Drawing
NS Package Number SDC08A
9
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Notes
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