LM6118MD8 [NSC]
IC DUAL OP-AMP, 17 MHz BAND WIDTH, UUC, DIE, Operational Amplifier;
| 型号： | LM6118MD8 |
| 厂家： | 
National Semiconductor |
| 描述： | IC DUAL OP-AMP, 17 MHz BAND WIDTH, UUC, DIE, Operational Amplifier 放大器 |
| 文件： | 总13页 (文件大小：835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1999
LM6118/LM6218
Fast Settling Dual Operational Amplifiers
General Description
Features
The
LM6118/LM6218
are
monolithic
fast-settling
Typical
0.2 mV
400 ns
±
unity-gain-compensated dual operational amplifiers with 20
mA output drive capability. The PNP input stage has a typical
bias current of 200 nA, and the operating supply voltage is
j
j
j
j
j
j
j
Low offset voltage:
0.01% settling time:
±
±
5V to 20V.
=
Slew rate Av −1:
140 V/µs
75 V/µs
17 MHz
5.5 mA
These dual op amps use slew enhancement with special
mirror circuitry to achieve fast response and high gain with
low total supply current.
=
Slew rate Av +1:
Gain bandwidth:
Total supply current:
™
The amplifiers are built on a junction-isolated VIP (Verti-
cally Integrated PNP) process which produces fast PNP’s
that complement the standard NPN’s.
±
Output drives 50Ω load ( 1V)
Applications
n D/A converters
n Fast integrators
n Active filters
Connection Diagrams and Order Information
Small Outline Package (WM)
Dual-In-Line Package (J or N)
DS010254-3
DS010254-4
Top View
Order Number LM6218WM
See NS Package Number M14B
Top View
Order Number LM6118N,
LM6218AN or LM6218N
See NS Package Number N08E
™
VIP is a trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS010254
www.national.com
Typical Applications
DS010254-1
Single ended input to differential output
=
=
10, BW 3.2 MHz
A
V
=
40 V Response 1.4 MHz
PP
=
±
V
15V
S
Wide-Band, Fast-Settling
40 VPP Amplifier
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Junction Temperature
Storage Temperature Range
Lead Temperature
150˚C
−65˚C to +150˚C
(Soldering, 10 sec.)
300˚C
Total Supply Voltage
Input Voltage
42V
Operating Temp. Range
(Note 2)
±
Differential Input Current (Note 3)
Output Current (Note 4)
Power Dissipation (Note 5)
ESD Tolerance
10 mA
LM6118
LM6218A
LM6218
−55˚C to +125˚C
−40˚C to +85˚C
−40˚C to +85˚C
Internally Limited
500 mW
=
=
±
(C 100 pF, R 1.5 kΩ)
2 kV
Electrical Characteristics
=
=
=
=
±
±
20V, VCM 0V, VOUT 0V, IOUT 0A, unless otherwise specified. Limits with standard type face are for TJ
5V ≤ VS
≤
25˚C, and Bold Face Type are for Temperature Extremes.
Typ
LM6118
Limits
(Note 6)
1
LM6218A
Limits
(Note 6)
1
LM6218
Limits
(Note 6)
3
Parameter
Input Offset Voltage
Input Offset Voltage
Input Offset Current
Input Bias Current
Conditions
25˚C
Units
=
±
VS
15V
0.2
0.3
mV (max)
mV (max)
nA (max)
nA (max)
dB (min)
dB (min)
dB (min)
V/mV (min)
V/mV (min)
V (min)
2
2
4
V− + 3V ≤ VCM ≤ V+ − 3.5V
V− + 3V ≤ VCM ≤ V+ − 3.5V
V− + 3V ≤ VCM ≤ V+ − 3.5V
V− + 3V ≤ VCM ≤ V+ − 3.5V
1.5
1.5
3.5
2.5
2.5
4.5
20
50
50
100
200
500
1250
80
250
350
950
90
100
350
950
90
200
100
100
100
500
200
17.3
5.5
Input Common Mode
Rejection Ratio
=
±
VS
20V
85
85
75
=
Positive Power Supply
Rejection Ratio
V− −15V
90
90
80
5V ≤ V+ ≤ 20V
85
85
75
=
Negative Power Supply
Rejection Ratio
V+ 15V
90
90
80
−20V ≤ V− ≤ −5V
85
85
75
=
=
±
Large Signal
Vout
15V
RL 10k
150
100
50
150
100
50
100
70
=
±
Voltage Gain
VS
20V
=
=
±
Vout
10V
RL 500
40
=
±
±
VS
15V
(
20 mA)
=
30
30
25
=
±
±
±
±
VO Output Voltage
Swing
Supply
20V
RL 10k
17
17
17
=
±
Total Supply Current
VS
15V
7
7
7
mA (max)
7.5
100
100
50
7.5
100
100
50
7.5
100
100
50
=
=
±
±
Output Current Limit
VS
VS
15V, Pulsed
65
mA (max)
V/µs (min)
=
=
±
Slew Rate, Av −1
15V, Vout
10V
140
=
=
=
RS Rf 2k, Cf 10 pF
=
=
=
±
15V, Vout
±
Slew Rate, Av +1
VS
10V
75
50
50
50
V/µs (min)
=
=
=
RS Rf 2k, Cf 10 pF
30
30
30
=
=
±
Gain-Bandwidth Product
0.01% Settling Time
VS
15V, fo 200 kHz
17
14
14
13
MHz (min)
ns
=
=
±
∆Vout 10V, VS
15V,
400
=
=
=
=
AV −1
RS Rf 2k, Cf 10 pF
Input Capacitance
Inverter
5
3
pF
pF
Follower
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its rated operating conditions.
+
−
Note 2: Input voltage range is (V − 1V) to (V ).
3
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Electrical Characteristics (Continued)
Note 3: The inputs are shunted with three series-connected diodes back-to-back for input differential clamping. Therefore differential input voltages greater than
about 1.8V will cause excessive current to flow unless limited to less than 10 mA.
Note 4: Current limiting protects the output from a short to ground or any voltage less than the supplies. With a continuous overload, the package dissipation must
be taken into account and heat sinking provided when necessary.
Note 5: Devices must be derated using a thermal resistance of 90˚C/W for the N and WM packages.
Note 6: Limits are guaranteed by testing or correlation.
Typical Performance Characteristics
Input Bias Current
Input Noise Voltage
Common Mode Limits
DS010254-25
DS010254-26
DS010254-27
Common Mode Rejection
Power Supply Rejection
Frequency Response
High Frequency
DS010254-28
DS010254-29
DS010254-30
Unity Gain Bandwidth
Unity Gain Bandwidth
vs Output Load
Large Signal Response
(Sine Wave)
DS010254-31
DS010254-32
DS010254-33
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4
Typical Performance Characteristics (Continued)
Total Harmonic Distortion
Output Impedance
Output Saturation
DS010254-34
DS010254-35
DS010254-36
Output Current Limit
Supply Current
Slew Rate
(Both Amplifiers)
DS010254-37
DS010254-39
DS010254-38
Inverter Settling Time
Follower Settling Time
Typical Stability Range
DS010254-40
DS010254-41
DS010254-42
5
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Typical Performance Characteristics (Continued)
=
±
15V
Amplifier to Amplifier Coupling
Settling Time, Vs
DS010254-23
DS010254-7
=
=
= =
±
Step Response, Av −1, Vs
±
Step Response, Av +1, Vs
15V
15V
DS010254-8
DS010254-9
Application Information
General
Amplifier Shut Down
The LM6118/LM6218 are high-speed, fast-settling dual
op-amps. To insure maximum performance, circuit board lay-
out is very important. Minimizing stray capacitance at the in-
puts and reducing coupling between the amplifier’s input and
output will minimize problems.
If one of the amplifiers is not used, it can be shut down by
connecting both the inverting and non-inverting inputs to the
V− pin. This will reduce the power supply current by approxi-
mately 25
%.
Capacitive Loading
Supply Bypassing
Maximum capacitive loading is about 50 pF for a closed-loop
gain of +1, before the amplifier exhibits excessive ringing
and becomes unstable. A curve showing maximum capaci-
tive loads, with different closed-loop gains, is shown in the
Typical Performance Characteristics section.
To assure stability, it is recommended that each power sup-
ply pin be bypassed with a 0.1 µF low inductance capacitor
near the device. If high frequency spikes from digital circuits
or switching supplies are present, additional filtering is rec-
ommended. To prevent these spikes from appearing at the
output, R-C filtering of the supplies near the device may be
necessary.
To drive larger capacitive loads at low closed-loop gains, iso-
late the amplifier output from the capacitive load with 50Ω.
Connect a small capacitor directly from the amplifier output
to the inverting input. The feedback loop is closed from the
isolated output with a series resistor to the inverting input.
Power Dissipation
These amplifiers are specified to 20 mA output current. If ac-
companied with high supply voltages, relatively high power
dissipation in the device will occur, resulting in high junction
temperatures. In these cases the package thermal resis-
tance must be taken into consideration. (See Note 5 under
Electrical Characteristics.) For high dissipation, an N pack-
age with large areas of copper on the pc board is recom-
mended.
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6
Application Information (Continued)
Integrator
Voltage Follower
DS010254-10
DS010254-12
=
=
1000 pF, Small signal BW 5 MHz
For C
L
Examples of unity gain connections for a voltage follower, In-
verter, and integrator driving capacitive loads up to 1000 pF
are shown here. Different R1–C1 time constants and capaci-
tive loads will have an effect on settling times.
=
BW 500 kHz
20 V
p-p
Inverter
Input Bias Current Compensation
Input bias current of the first op amp can be reduced or bal-
anced out by the second op amp. Both amplifiers are laid out
in mirror image fashion and in close proximity to each other,
thus both input bias currents will be nearly identical and will
track with temperature. With both op amp inputs at the same
potential, a second op amp can be used to convert bias cur-
rent to voltage, and then back to current feeding the first op
amp using large value resistors to reduce the bias current to
the level of the offset current.
DS010254-11
Examples are shown here for an inverting application, (a)
where the inputs are at ground potential, and a second cir-
cuit (b) for compensating bias currents for both inputs.
Settling time to 0.01%, 10V Step
=
=
For C
For C
1000 pF, settling time ≈ 1500 ns
300 pF, settling time ≈ 500 ns
L
L
7
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Application Information (Continued)
Bias Current Compensation
DS010254-14
*
mount resistor close to input pin to minimize stray capacitance
(b) Compensation to Both Inputs
DS010254-13
*
adjust for zero integrator drift
(a) Inverting Input Bias Compensation
for Integrator Application
Amplifier/Parallel Buffer
DS010254-15
=
=
A
V
+5, I
±
≤ 80 mA
V
OUT
15V, C ≤ 0.01 µF
S
L
=
=
Large and small signal B.W. 1.3 MHz (THD 3%)
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8
Application Information (Continued)
Constant-Voltage Crossover Network With 12 dB/Octave Slope
DS010254-16
Bilateral Current Source
Coaxial Cable Driver
DS010254-17
=
±
V
S
15V, −10 ≤ V ≤ 10V
IN
DS010254-19
Small signal (200 mV ) BW ≈ 5 MHz
p-p
=
Output dynamic range 10V − R6 |I
|
OUT
=
=
500Ω, small signal BW 6 MHz
R
L
=
Large signal response 800 kHz
9
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Application Information (Continued)
Instrumentation Amplifier
150 MHz Gain-Bandwidth Amplifier
DS010254-20
=
=
±
A
100, V
15V,
Small signal BW ≈ 1.5 MHz
Large signal BW (20 V ) ≈ 800 kHz
DS010254-18
V
S
=
=
±
A
V
10, V
15V, All resistors 0.01%
S
p-p
Small signal and large signal (20 V ) B.W. ≈ 800 kHz
P-P
Schematic Diagram
1/2 LM6118 (Op Amp A)
DS010254-21
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10
Schematic Diagram (Continued)
Bias Circuit
DS010254-22
11
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead Molded Small Outline Package (M)
Order Number LM6218AWM or LM6218WM
NS Package Number M14B
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12
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Lead Molded Dual-In-Line Package (N)
Order Number LM6118N, LM6218AN or LM6218N
NS Package Number N08E
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