LM6629MFX [NSC]
Ultra-Low Noise, High-Speed Operational Amplifier with Shutdown; 超低噪声，高速，带有关断运算放大器
| 型号： | LM6629MFX |
| 厂家： | 
National Semiconductor |
| 描述： | Ultra-Low Noise, High-Speed Operational Amplifier with Shutdown |
| 文件： | 总28页 (文件大小：1081K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2, 2010
LMH6629
Ultra-Low Noise, High-Speed Operational Amplifier with
Shutdown
General Description
Features
The LMH6629 is a high-speed, ultra low-noise amplifier de-
signed for applications requiring wide bandwidth with high
gain and low noise such as in communication, test and mea-
surement, optical and ultrasound systems.
Specified for VS = 5V, RL = 100Ω, AV = 10V/V LLP-8 package,
unless specified
–3dB bandwidth
Input voltage noise
Input offset voltage max. over temperature
Slew rate
HD2 @ f = 1MHz, 2VPP
HD3 @ f = 1MHz, 2VPP
Supply voltage range
Typical supply current
Selectable min. gain
Enable Time
900 MHz
0.69 nV/√Hz
±0.8 mV
1600 V/ μs
−90 dBc
−94 dBc
2.7V to 5.5V
15.5 mA
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The LMH6629 operates on 2.7 to 5.5V supply with an input
common mode range that extends below ground and outputs
that swing to within 0.8V of the rails for ease of use in single
supply applications. Heavy loads up to ±250 mA can be driven
by high-frequency large signals with the LMH6629's –3dB
bandwidth of 900 MHz and 1600 V/µs slew rate. The
LMH6629 (LLP-8 package only) has user-selectable internal
compensation for minimum gains of 4 or 10 controlled by
pulling the COMP pin low or high, thereby avoiding the need
for external compensation capacitors required in competitive
devices. Compensation for the SOT23-5 package is internally
set for a minimum stable gain of 10 V/V. The LLP-8 package
also provides the power-down enable/ disable feature.
≥4 or ≥10 V/V
75 ns
Output Current
LLP-8 and SOT23-5 Packages
±250 mA
Applications
The low-input noise (0.69nV/√Hz and 2.6 pA/√Hz), low dis-
tortion (HD2/ HD3 = −90 dBc/−94 dBc) and ultra-low DC
errors (800 µV VOS maximum over temperature, ±0.45 µV/°C
drift) allow precision operation in both AC- and DC-coupled
applications.
Instrumentation Amplifiers
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Ultrasound Pre-amps
Wide-band Active Filters
Opto-electronics
The LMH6629 is fabricated in National Semiconductor’s pro-
prietary SiGe process and is available in a 3mm x 3mm 8-pin
LLP, as well as the SOT23-5, package.
Medical imaging systems
Base-station Amplifiers
Low-Noise Single Ended to Differential Conversion
Trans-impedance amplifier
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Typical Application Circuit
30068011
FIGURE 1. Transimpedance Amplifier
© 2010 National Semiconductor Corporation
300680
www.national.com
Ordering Information
Package
Part Number
LMH6629SD
LMH6629SDE
LMH6629SDX
LMH6629MF
LMH6629MFE
LM6629MFX
Package Marking
Transport Media
NSC Drawing
1k Units Tape and Reel
250 Units Tape and Reel
4.5k Units Tape and Reel
1k Units Tape and Reel
250 Units Tape and Reel
3k Units Tape and Reel
LLP-8
L6629
SDA08A
SOT23-5
AE7A
MF05A
Connection Diagrams
30068001
30068052
SOT23-5 (Top View)
LLP-8 (Top View)
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2
Junction Temperature
Storage Temperature Range
Soldering Information
+150°C
−65°C to +150°C
Absolute Maximum Ratings (Note 1, Note
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
See Product Folder at www.national.com and http://
www.national.com/ms/MS/MS-SOLDERING.pdf
Operating Ratings (Note 1)
Supply Voltage (V+ - V−
Operating Temperature Range
Package
ESD Tolerance (Note 4)
Human Body Model
Machine Model
Charge-Device Model
Positive Supply Voltage
Differential Input Voltage
Analog Input Voltage Range
Digital Input Voltage
2kV
200V
750V
2.7V to 5.5V
−40°C to +125°C
(θJA
)
−0.5 to 6.0V
3V
−0.5 to VS
−0.5 to VS
LLP-8
SOT23-5
71°C/W
179°C/W
5V Electrical Characteristics
The following specifications apply for single supply with VS = 5V, RL = 100Ω terminated to 2.5V, gain = 10V/V, VO = 2VPP, VCM
VS/2, COMP Pin = HI (LLP-8 package), unless otherwise noted. Boldface limits apply at the temperature extremes. (Note 2).
=
Min
(Note 6)
Typ
(Note 6)
Max
(Note 6)
Symbol
Parameter
Conditions
Units
DYNAMIC PERFORMANCE
VO = 200 mVPP, LLP-8 package
VO = 200 mVPP, SOT23-5 package
900
Small signal −3dB
bandwidth
1000
SSBW
LSBW
MHz
MHz
AV= 4, VO = 200 mVPP
COMP Pin = LO
VO = 2VPP
,
800
380
190
Large signal −3dB
bandwidth
COMP Pin = LO, AV= 4, VO = 2VPP
AV= 10, VO = 200 mVPP
,
330
190
95
LLP-8 package
AV= 10, VO = 200 mVPP
SOT23-5 package
,
0.1 dB bandwidth
MHz
AV= 4, VO = 200 mVPP
,
COMP Pin = LO
VO = 200 mVPP
LLP-8 package
VO = 200 mVPP
,
0
Peaking
dB
,
2
SOT23-5 package
AV= 10, 2V step
1600
530
SR
Slew rate
V/μs
AV= 4, 2V step,
COMP Pin = LO
AV= 10, 2V step, 10% to 90%,
LLP-8 package
0.90
0.95
2.8
AV= 10, 2V step, 10% to 90%, SOT23-5
package
tr/ tf
Rise/fall time
ns
AV= 4, 2V step, 10% to 90%,
COMP Pin = LO, (Slew Rate Limited)
AV= 10, 1V step, ±0.1%
Ts
Settling time
42
2
VIN = 1VPP
Overload Recovery
3
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Min
(Note 6)
Typ
(Note 6)
Max
(Note 6)
Symbol
Parameter
Conditions
Units
NOISE AND DISTORTION
fc = 1MHz, VO = 2VPP
−90
−88
−70
−65
−94
−87
−82
−75
COMP Pin = LO, AV= 4, fc = 1 MHz, VO
= 2VPP
2nd order distortion
HD2
dBc
fc = 10 MHz, VO = 2VPP
COMP Pin = LO, fc = 10 MHz,
AV= 4V, VO = 2VPP
fc = 1MHz, VO = 2VPP
COMP Pin = LO, AV= 4, fc = 1MHz, VO
= 2VPP
3rd order distortion
HD3
dBc
fc = 10 MHz, VO = 2VPP
COMP Pin = LO, fc = 10 MHz,
VO = 2VPP
Two-tone 3rd order
intercept point
fc = 25 MHz, VO = 2 VPP composite
fc = 75 MHz, VO = 2VPP composite
31
27
OIP3
dBm
en
Noise Voltage
Noise current
Noise Figure
0.69
2.6
8.0
nV/√Hz
pA/√Hz
dB
Input referred f > 1MHz
in
NF
RS = RT = 50Ω
ANALOG I/O
CMRR > 70 dB, LLP-8 package
CMRR > 70 dB, SOT23-5 package
−0.30
3.8
CMVR
VO
Input voltage range
Output voltage range
V
V
−0.30 to
3.8
0.89
0.95
0.82 to
4.19
4.0
3.9
RL = 100Ω to VS/2
0.76
0.85
0.72 to
4.28
4.1
4.0
No Load
IOUT
VOS
VO = 2.5V (Note 3)
Linear output current
Input offset voltage
250
mA
µV
±780
±800
±150
Input offset voltage
temperature drift
TcVOS
IBI
(Note 7)
(Note 6)
±0.45
−15
μV/°C
μA
−23
−37
Input bias current
Input offset current
±1.8
±3.0
IOS
±0.1
±2.8
μA
Input offset voltage
temperature drift
TCIOS
(Note 7)
nA/°C
CCM
RCM
Input capacitance
Input resistance
Common Mode
Common Mode
1.7
pF
450
kΩ
MISCELLANEOUS PARAMETERS
82
70
VCM from 0V to 3.7V, LLP-8 package
VCM from 0V to 3.7V, SOT23-5 package
87
87
83
Common mode rejection
CMRR
ratio
Power supply rejection
81
78
dB
PSRR
ratio
74
72
LLP-8 package
78
78
AVOL
Open loop gain
SOT23-5 package
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4
Min
(Note 6)
Typ
(Note 6)
Max
(Note 6)
Symbol
Parameter
Conditions
Units
DIGITAL INPUTS/TIMING
Logic low-voltage
threshold
VIL
VIH
IIL
PD and COMP pins, , LLP-8 package
PD and COMP pins, LLP-8 package
0.8
V
Logic high-voltage
threshold
2.5
PD and COMP pins = 0.8V, , LLP-8
package(Note 6)
−23
−19
−34
−38
Logic low-bias current
Logic high-bias current
−28
−22
µA
ns
PD and COMP pins = 2.5V, LLP-8
package(Note 6)
−16
−14
−27
−29
IIH
Ten
Tdis
Enable time
Disable time
LLP-8 package
LLP-8 package
75
80
POWER REQUIREMENTS
No Load, Normal Operation (PD Pin = HI
or open for LLP-8 package)
16.7
18.2
15.5
1.1
IS
Supply Current
mA
No Load, Shutdown (PD Pin =LO for
LLP-8 package)
1.85
2.0
5
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3.3V Electrical Characteristics
The following specifications apply for single supply with VS = 3.3V, RL = 100Ω terminated to 1.65V, gain = 10V/V, VO = 1VPP
,
VCM = VS/2, COMP Pin = HI (LLP-8 package), unless otherwise noted. Boldface limits apply at the temperature extremes. (Note
2)
Min
(Note 5)
Typ
(Note 5)
Max
(Note 5)
Symbol
Parameter
Conditions
Units
DYNAMIC PERFORMANCE
VO = 200 mVPP, LLP-8 package
VO = 200 mVPP, SOT23-5 package
820
950
MHz
SSBW
LSBW
Small signal −3dB bandwidth
COMP Pin = LO, AV= 4,
VO = 200 mVPP
730
VO = 1VPP
540
320
Large signal −3dB bandwidth
0.1 dB bandwidth
MHz
MHz
COMP Pin = LO, AV= 4, VO = 1VPP
AV= 10, VO = 200 mVPP
,
330
190
85
LLP-8 package
AV= 10, VO = 200 mVPP
SOT23-5 package
,
COMP Pin = LO, AV= 4,
VO = 200 mVPP
VO = 200 mVPP, LLP-8 package
VO = 200 mVPP, SOT23-5 package
AV= 10, 1.3V step
0
Peaking
dB
1.8
1100
500
SR
Slew rate
V/µs
COMP Pin = LO, AV= 4, 1.3V step
AV= 10, 1V step, 10% to 90%,
LLP-8 package
0.7
0.55
1.3
AV= 10, 1V step, 10% to 90%,
SOT23-5 package
tr/ tf
Rise/fall time
ns
AV= 4, COMP Pin = LO, 1V step,
10% to 90% (Slew Rate Limited)
AV= 10, 1V step, ±0.1%
Ts
Settling time
70
2
VIN = 1VPP
Overload Recovery
NOISE AND DISTORTION
fc = 1MHz, VO = 1VPP
–82
-88
COMP Pin = LO, AV= 4, fc = 1MHz,
VO = 1VPP
2nd order distortion
HD2
dBc
fc = 10 MHz, VO = 1VPP
-67
COMP Pin = LO, fc = 10 MHz, AV= 4V,
VO = 1VPP
-74
fc = 1MHz, VO = 1VPP
-94
COMP Pin = LO, AV= 4, fc = 1MHz,
VO = 1VPP
-112
-79
3rd order distortion
HD3
dBc
fc = 10 MHz, VO = 1VPP
COMP pin = LO, fc = 10 MHz,
VO = 1VPP
–96
Two-tone 3rd Order Intercept
Point
fc = 25 MHz, VO = 1VPP composite
fc = 75 MHz, VO = 1VPP composite
30
26
OIP3
dBm
en
in
Noise voltage
Noise current
Noise figure
0.69
2.6
8.0
nV/√HZ
pA/√HZ
dB
Input referred, f > 1MHz
NF
RS = RT = 50Ω
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6
Min
(Note 5)
Typ
(Note 5)
Max
(Note 5)
Symbol
Parameter
Input voltage range
Output voltage range
Conditions
Units
ANALOG I/O
CMRR > 70 dB, LLP-8 package
CMRR > 70 dB, SOT23-5 package
−0.30
2.1
CMVR
V
V
−0.30 to
2.1
0.90
0.95
0.79 to
2.50
2.4
2.3
RL = 100Ω to VS/2
VO
0.76
0.80
0.70 to
2.60
2.5
2.4
No load
IOUT
VOS
VO = 1.65V (Note 3)
Linear output current
Input Offset Voltage
230
mA
µV
±680
±700
±150
Input offset voltage
temperature drift
TcVOS
IBI
(Note 7)
(Note 6)
±1
−15
μV/°C
μA
−23
−35
Input Bias Current
Input Offset Current
±1.8
±3.0
IOS
±0.13
±3.2
μA
Input offset voltage
temperature drift
TCIOS
(Note 7)
nA/°C
CCM
RCM
Input Capacitance
Input Resistance
Common Mode
Common Mode
1.7
1
pF
MΩ
MISCELLANEOUS PARAMETERS
84
81
VCM from 0V to 2.0V, LLP-8 package
87
87
84
Common Mode Rejection
CMRR
Ratio
VCM from 0V to 2.0V, SOT23-5
package
dB
82
79
PSRR
AVOL
Power supply rejection ratio
Open Loop Gain
78
73
LLP-8 package
79
79
SOT23-5 package
DIGITAL INPUTS/TIMING
VIL
VIH
Logic low-voltage threshold
Logic high-voltage threshold
0.8
PD and COMP pins, LLP-8 package
V
2.0
PD and COMP pins = 0.8V, LLP-8
package (Note 6)
-17
−14
−28
−32
IIL
Logic low-bias current
Logic high-bias current
−23
−22
µA
ns
PD and COMP pins = 2.0V, LLP-8
package (Note 6)
−16
−13
−27
−31
IIH
Ten
Tdis
Enable time
Disable time
LLP-8 package
LLP-8 package
75
80
POWER REQUIREMENTS
No Load, Normal Operation (PD Pin =
HI or open for LLP-8 package)
14.9
16.0
13.7
0.89
IS
Supply Current
mA
No Load, Shutdown (PD Pin = LO for
LLP-8 package)
1.4
1.5
7
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Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ >
TA.
Note 3: The maximum continuous output current (IOUT) is determined by device power dissipation limitations. Continuous short circuit operation at elevated
ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C
Note 4: Human Body Model, applicable std. JESD22-A114C. Machine Model, applicable std. JESD22-A115-A. Field Induced Charge Device Model, applicable
std. JESD22-C101-C.
Note 5: Typical numbers are the most likely parametric norm. Bold numbers refer to over-temperature limits.
Note 6: Negative input current implies current flowing out of the device.
Note 7: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
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8
Typical Performance Characteristics
Unless otherwise specified, VS = ±2.5V, Rf = 240Ω, RL = 100Ω, VO = 2VPP, COMP pin = HI, AV = +10 V/V, LLP-8 and SOT23-5
packages (unless specifically noted).
Inverting Frequency Response
Inverting Frequency Response
30068003
30068004
Non-Inverting Frequency Response
Non-Inverting Frequency Response
30068005
30068006
Non-Inverting Frequency Response, LLP-8 Package
Non-Inverting Frequency Response, SOT23-5 Package
30068069
30068068
9
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Non-Inverting Frequency Response
with Varying VO, LLP-8 Package
Non-Inverting Frequency Response
with Varying VO, SOT23-5 Package
30068010
30068007
Non-Inverting Frequency Response
with Varying VO, LLP-8 Package
Non-Inverting Frequency Response
with Varying VO, SOT23-5 Package
30068027
30068008
Non-Inverting Frequency Response
with Varying VO, LLP-8 Package
Non-Inverting Frequency Response
with Varying VO, LLP-8 Package
30068013
30068014
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10
Frequency Response with Cap. Loading
Frequency Response Cap. Loading, LLP-8 Package
30068015
30068016
Frequency Response vs. Rf,
LLP-8 Package
Frequency Response vs. Rf,
SOT23-5 Package
30068030
30068017
Frequency Response vs. Rf,
LLP-8 Package
Frequency Response vs. Rf,
SOT23-5 Package
30068041
30068038
11
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Distortion vs. Swing,
LLP-8 Package
Distortion vs. Swing,
SOT23-5 Package
30068043
30068042
Distortion vs. Swing,
LLP-8 Package
Distortion vs. Swing,
SOT23-5 Package
30068077
30068045
Distortion vs. Gain,
LLP-8 Package
Distortion vs. Gain,
SOT23-5 Package
30068078
30068048
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12
Distortion vs. Frequency,
LLP-8 Package
Distortion vs. Frequency,
SOT23-5 Package
30068044
30068047
3rd Order Intermodulation Distortion vs. Output Voltage
Input Noise Voltage vs. Frequency
30068062
30068096
Input Noise Current vs. Frequency
PSRR vs. Frequency
30068063
30068009
13
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Open Loop Gain/Phase Response
Output Source Current,
LLP-8 Package
30068060
30068057
Output Sink Current
LLP-8 Package
Output Source Current,
SOT23-5 Package
30068058
30068065
Output Sink Current, SOT23-5 Package
Large Signal Step Response
30068073
30068066
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14
Large Signal Step Response
Large Signal Step Response
30068074
30068064
Large Signal Step Response
Small Signal Step Response, LLP-8 Package
30068075
30068046
Small Signal Step Response, LLP-8 Package
Turn-On Waveform, LLP-8 Package
30068076
30068025
15
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Turn-Off Waveform, LLP-8 Package
Supply Current vs. Supply Voltage
30068024
30068090
Offset Voltage vs. Supply Voltage (Typical Unit)
Input Bias Current vs. Supply Voltage (Typical Unit)
30068067
30068091
Input Offset Current vs. Supply Voltage (Typical Unit)
30068053
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16
Application Section
INTRODUCTION
LLP-8 CONTROL PINS & SOT23-5 COMPARISON
The LMH6629 is a high gain bandwidth, ultra low-noise volt-
age feedback operational amplifier. The excellent noise and
bandwidth enables applications such as medical diagnostic
ultrasound, magnetic tape & disk storage and fiberoptics to
achieve maximum high frequency signal-to-noise ratios. The
following discussion will enable the proper selection of exter-
nal components to achieve optimum system performance.
The LMH6629 LLP-8 package has two digital control pins;
PD and COMP pins. The PD pin, used for powerdown, floats
high (device on) when not driven. When the PD pin is pulled
low, the amplifier is disabled and the amplifier output stage
goes into a high impedance state so the feedback and gain
set resistors determine the output impedance of the circuit.
The other control pin, the COMP pin, allows control of the
internal compensation and defaults to the lower gain mode or
logic 0.
The LMH6629 (LLP-8 package only) has some additional
features to allow maximum flexibility. As shown in Figure 2
there are provisions for low-power shutdown and two internal
compensation settings, which are further discussed below
under the COMPENSATION heading. Also provided is a
feedback (FB) pin which allows the placement of the feedback
resistor directly adjacent to the inverting input (IN-) pin. This
pin simplifies printed circuit board layout and minimizes the
possibility of unwanted interaction between the feedback path
and other circuit elements.
The SOT23-5 package has the following differences relative
to the LLP-8 package:
1. No power down (shutdown) capability.
2. No COMP pin to set the minimum stable gain. SOT23–5
package minimum stable gain is internally fixed to be
10V/V.
3. No feedback (FB) pin.
From a performance point of view, the LLP-8 and the
SOT23-5 packages perform very similarly except in the fol-
lowing areas:
1. SSBW, Peaking, and 0.1 dB Bandwidth: These
differences are highlighted in the Typical Performance
Characteristics section and the Electrical Characteristics
tables. Most notable differences are with small signal (0.2
Vpp) and close to the minimum stable gain of 10V/V.
2. Distortion: It is possible to get slightly different distortion
performance. The board layout, decoupling capacitor
return current routing strongly influences this
3. Output Current: In heavy current applications, there will
be differences between these package types because of
the difference in their respective Thermal Resistances
(θJA).
30068061
FIGURE 2. 8-Pin LLP Pinout Diagram
COMPENSATION
The LMH6629 has two compensation settings that can be
controlled by the COMP pin (LLP-8 package only). The de-
fault setting is set through an internal pull down resistor and
places the COMP pin at the logic 0 state. In this configuration
the on-chip compensation is set to the maximum and band-
width is reduced to enable stability at gains as low as 4V/V.
The LLP-8 package requires the bottom-side Die Attach Pad-
dle (DAP) to be soldered to the circuit board for proper thermal
dissipation and to get the thermal resistance number speci-
fied. The DAP is tied to the V- potential within the LMH6629
package. Thus, the circuit board copper area devoted to DAP
heatsinking connection should be at the V- potential as well.
Please refer to the package drawing for the recommended
land pattern and recommended DAP connection dimensions.
When this pin is driven to the logic 1 state, the internal com-
pensation is decreased to allow higher bandwidth at higher
gains. In this state, the minimum stable gain is 10V/V. Due to
the reduced compensation, slew rate and large signal band-
width are significantly enhanced for the higher gains.
As mentioned earlier, the SOT23-5 package does not offer
the two compensation settings that the LLP-8 offers. The
SOT23-5 is internally set for a minimum gain of 10 V/V.
It is possible to externally compensate the LMH6629 for any
of the following reasons, as shown in Figure 4:
•
To operate the SOT23-5 package (which does not offer
the COMP pin) at closed loop gains < 10V/V.
•
To operate the LLP-8 package at gains below the
minimum stable gain of 4V /V when the COMP pin is LO.
Note: In this case, Figure 4 “Constraint 1” may be changed
to ≥ 4 V/V instead of ≥ 10 V/V.
To operate either package at low gain and need maximum
slew rate (COMP pin HI).
•
30068052
FIGURE 3. LLP–8 DAP(Top View)
17
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30068050
FIGURE 4. External Compensation
This circuit operates by increasing the Noise Gain (NG) be-
yond the minimum stable gain of the LMH6629 while main-
taining a positive loop gain phase angle at 0dB. There are two
constraints shown in Figure 4; “Constraint 1” ensures that NG
has increased to at least 10 V/V when the loop gain ap-
proaches 0dB, and “Constraint 2” places an upper limit on the
feedback phase lead network frequency to make sure it is fully
effective in the frequency range when loop gain approaches
0dB. These two constraints allow one to estimate the “starting
value” for Rc and Cc which may need to be fine tuned for
proper response.
Here is an example worked out for more clarification:
Assume that the objective is to use the SOT23-5 version of
the LMH6629 for a closed loop gain of +3.7 V/V using the
technique shown in Figure 4.
Selecting Rf = 249Ω → Rg = 91Ω → REQ= 66.6Ω.
For 50Ω source termination (Rs= 50Ω), select RT= 50Ω →
30068049
Rp = 25Ω.
FIGURE 5. SOT23-5 Package Low Closed Loop Gain
Operation with External Compensation
Using “Constraint 1” (= 10V/V) allows one to compute Rc ≊
56Ω. Using “Constraint 2” (= 90 MHz) defines the appropriate
value of Cc≊ 33 pF.
The frequency response plot shown in Figure 5 is the mea-
sured response with Rc and Cc values computed above and
shows a -3dB response of about 1GHz.
For the Figure 5 measured results, a compensation capacitor
(Cf') was used across Rf to compensate for the summing node
net capacitance due to the board and the SOT23–5
LMH6629. The RA and RB combination reduces the effective
capacitance of Cf‘ by the ratio of 1+RB / RA, with the constraint
that RB << Rf, thereby allowing a practical capacitance value
(> 1pF) to be used. The LLP-8 package does not need this
compensation across Rf due to its lower parasitics.
With the COMP pin HI (LLP-8 package only) or with the
SOT23–5 package, this circuit achieves high slew rate and
takes advantage of the LMH6629’s superior low-noise char-
acteristics without sacrificing stability, while enabling lower
gain applications. It should be noted that the Rc, Cc combina-
tion does lower the input impedance and increases noise gain
at higher frequencies. With these values, the input impedance
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18
reduces by 3dB at 490 MHz. The Noise Gain transfer function
“zero” is given by the equation below and it has a 3dB in-
crease at 32.8 MHz with these values:
Equation 1: External Compensation Noise Gain
(1)
Increase
CANCELLATION OF OFFSET ERRORS DUE TO INPUT
BIAS CURRENTS
The LMH6629 offers exceptional offset voltage accuracy. In
order to preserve the low offset voltage errors, care must be
taken to avoid voltage errors due to input bias currents. This
is important in both inverting and non inverting applications.
The non-inverting circuit is used here as an example. To can-
cel the bias current errors of the non-inverting configuration,
the parallel combination of the gain setting (Rg) and feedback
(Rf) resistors should equal the equivalent source resistance
(Rseq) as defined in Figure 6. Combining this constraint with
the non-inverting gain equation also seen in Figure 6 allows
both Rf and Rg to be determined explicitly from the following
equations:
30068019
FIGURE 7. Inverting Amplifier Configuration
TOTAL INPUT NOISE vs. SOURCE RESISTANCE
Rf = AVRseq and Rg = Rf/(AV-1)
To determine maximum signal-to-noise ratios from the
LMH6629, an understanding of the interaction between the
amplifier’s intrinsic noise sources and the noise arising from
its external resistors is necessary. Figure 8 describes the
noise model for the non-inverting amplifier configuration
showing all noise sources. In addition to the intrinsic input
voltage noise (en) and current noise (in = in = in−) source,
+
there is also thermal voltage noise (et = √(4KTR)) associated
with each of the external resistors.
30068018
FIGURE 6. Non-Inverting Amplifier Configuration
30068020
When driven from a 0Ω source, such as the output of an op
amp, the non-inverting input of the LMH6629 should be iso-
lated with at least a 25Ω series resistor.
FIGURE 8. Non-Inverting Amplifier Noise Model
Equation 2 provides the general form for total equivalent input
As seen in Figure 7, bias current cancellation is accomplished
for the inverting configuration by placing a resistor (Rb) on the
non-inverting input equal in value to the resistance seen by
the inverting input (Rf || (Rg+Rs)). Rb should to be no less than
25Ω for optimum LMH6629 performance. A shunt capacitor
(not shown) can minimize the additional noise of Rb.
voltage noise density (eni).
(2)
Equation 2: General Noise Equation
Equation 3 is a simplification of Equation 2 that assumes Rf ||
Rg = Rseq for bias current cancellation:
Equation 3: Noise Equation with
Rf || Rg = Rseq
(3)
Figure 9 schematically shows eni alongside VIN (the portion of
VS source which reaches the non-inverting input of Figure 6)
19
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and external components affecting gain (Av= 1 + Rf / Rg), all
connected to an ideal noiseless amplifier.
30068022
30068054
FIGURE 11. Voltage Noise Density vs. Source Resistance
FIGURE 9. Non-Inverting Amplifier Equivalent Noise
Source Schematic
If bias current cancellation is not a requirement, then Rf || Rg
need not equal Rseq. In this case, according to Equation 2,
Rf || Rg should be as low as possible to minimize noise. Re-
sults similar to Equation 2 are obtained for the inverting
configuration of Figure 7 if Rseq is replaced by Rb and Rg is
replaced by Rg + Rs. With these substitutions, Equation 2 will
yield an eni referred to the non-inverting input. Referring eni to
the inverting input is easily accomplished by multiplying eni by
the ratio of non-inverting to inverting gains (1+Rg/ Rf).
Figure 10 illustrates the equivalent noise model using this as-
sumption. Figure 11 is a plot of eni against equivalent source
resistance (Rseq) with all of the contributing voltage noise
source of Equation 3. This plot gives the expected eni for a
given (Rseq) which assumes Rf||Rg = Rseq for bias current
cancellation. The total equivalent output voltage noise (eno) is
eni*AV.
NOISE FIGURE
Noise Figure (NF) is a measure of the noise degradation
caused by an amplifier.
(4)
Equation 4: General Noise Figure Equation
30068021
Looking at the two parts of the NF expression (inside the log
function) yields:
FIGURE 10. Noise Model with Rf||Rg = Rseq
Si/ So→ Inverse of the power gain provided by the amplifier
As seen in Figure 11, eni is dominated by the intrinsic voltage
noise (en) of the amplifier for equivalent source resistances
below 15Ω. Between 15Ω and 2.5 kΩ, eni is dominated by the
thermal noise (et = √(4kT(2Rseq)) of the equivalent source re-
sistance Rseq; incidentally, this is the range of Rseq values
where the LMH6629 has the best (lowest) Noise Figure (NF)
for the case where Rseq = Rf || Rg.
No/ Ni→ Total output noise power, including the contribution
of RS, divided by the noise power at the input due to RS
To simplify this, consider Na as the noise power added by the
amplifier (reflected to its input port):
Si/ So→ 1/ G
No/ Ni→ G * (Ni+Na) / Ni (where G*(Ni +Na ) = No)
Substituting these two expressions into the NF expression:
Above 2.5 kΩ, eni is dominated by the amplifier’s current noise
(in = √(2) inRseq). When Rseq = 190Ω (i.e., Rseq = en/√(2) in),
the contribution from voltage noise and current noise of
LMH6629 is equal. For example, configured with a gain of
+10V/V giving a −3dB of 825 MHz and driven from Rseq = Rf
|| Rg = 20Ω (eni = 1.07 nV√Hz from Figure 11), the LMH6629
produces a total equivalent output noise voltage (eni * 10 V/V
(5)
Equation 5: Simplified Noise Figure Equation
The noise figure expression has simplified to depend only on
the ratio of the noise power added by the amplifier at its input
(considering the source resistor to be in place but noiseless
in getting Na) to the noise power delivered by the source re-
sistor (considering all amplifier elements to be in place but
noiseless in getting Ni).
* √(1.57 * 825 MHz)) of 385 μVrms
.
For a given amplifier with a desired closed loop gain, to min-
imize noise figure:
•
Minimize Rf || Rg
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20
•
Choose the Optimum RS (ROPT
)
LOW-NOISE TRANSIMPEDANCE AMPLIFIER
ROPT is the point at which the NF curve reaches a minimum
and is approximated by:
Figure 14 implements a high-speed, single-supply, low-noise
Transimpedance amplifier commonly used with photo-
diodes. The transimpedance gain is set by RF.
ROPT ≈ en/ in
Figure 12 is a plot of NF vs RS with the circuit of Figure 6 (Rf
= 240Ω, AV = +10V/V). The NF curves for both Unterminated
(RT = open) and Terminated systems (RT = RS) are shown.
Table 1 indicates NF for various source resistances including
RS = ROPT
.
30068011
30068079
FIGURE 14. 200MHz Transimpedance Amplifier
Configuration
FIGURE 12. Noise Figure vs. Source Resistance
TABLE 1. Noise Figure for Various Rs
Figure 15 shows the Noise Gain (NG) and transfer function
(I-V Gain). As with most Transimpedance amplifiers, it is re-
quired to compensate for the additional phase lag (Noise Gain
zero at fZ) created by the total input capacitance ( CD (diode
capacitance) + CCM (LMH6629 input capacitance) ) looking
into RF; this is accomplished by placing CF across RF to create
enough phase lead (Noise Gain pole at fP) to stabilize the
loop.
NF (Terminated)
(dB)
NF (Unterminated)
(dB)
RS (Ω)
50
8
4.1
3.2
1.1
ROPT
(ROPT = 750Ω)
(ROPT = 350Ω)
SINGLE-SUPPLY OPERATION
The LMH6629 can be operated with single power supply as
shown in Figure 13. Both the input and output are capacitively
coupled to set the DC operating point.
30068002
30068026
FIGURE 15. Transimpedance Amplifier Noise Gain &
Transfer Function
FIGURE 13. Single Supply Operation
21
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The optimum value of CF is given by Equation 6 resulting in
the I-V -3dB bandwidth shown in Equation 7, or around 200
MHz in this case (assuming GBWP= 4GHz with COMP pin =
HI for LLP-8 package). This CF value is a “starting point” and
CF needs to be tuned for the particular application as it is often
less than 1pF and thus is easily affected by board parasitics,
etc. For maximum speed, the LMH6629 COMP pin should be
HI (for LLP-8 package). This CF value is a “starting point” and
CF needs to be tuned for the particular application as it is often
less than 1pF and thus is easily affected by board parasitics,
etc. For maximum speed, the LMH6629 COMP pin should be
HI (or use the SOT23 package).
30068012
FIGURE 17. Transimpedance Amplifier Equivalent Input
Source Model
Equation 6: Optimum CF Value
(6)
(7)
From Figure 16, it is clear that with LMH6629’s extremely low-
noise characteristics, for RF < 2.5kΩ, the noise performance
is entirely dominated by RF thermal noise. Only above this
RF threshold, LMH6629’s input noise current (in) starts being
a factor and at no RF setting does the LMH6629 input noise
voltage play a significant role. This noise analysis has ignored
the possible noise gain increase, due to photo-diode capaci-
tance, at higher frequencies.
Equation 7: Resulting -3dB Bandwidth
Equation 8 provides the total input current noise density (ini)
equation for the basic Transimpedance configuration and is
plotted against feedback resistance (RF) showing all con-
tributing noise sources in Figure 16. The plot indicates the
expected total equivalent input current noise density (ini) for a
given feedback resistance (RF). This is depicted in the
schematic of Figure 17 where total equivalent current noise
density (ini) is shown at the input of a noiseless amplifier and
noiseless feedback resistor (RF). The total equivalent output
voltage noise density (eno) is ini*RF.
LOW-NOISE INTEGRATOR
Figure 18 shows a deBoo integrator implemented with the
LMH6629. Positive feedback maintains integration linearity.
The LMH6629’s low input offset voltage and matched inputs
allow bias current cancellation and provide for very precise
integration. Keeping RG and RS low helps maintain dynamic
stability.
30068028
FIGURE 16. Current Noise Density vs. Feedback
Resistance
30068029
FIGURE 18. Low-Noise Integrator
HIGH-GAIN SALLEN-KEY ACTIVE FILTERS
The LMH6629 is well suited for high-gain Sallen-Key type of
active filters. Figure 19 shows the 2nd order Sallen-Key low-
pass filter topology. Using component predistortion methods
discussed in OA-21 enables the proper selection of compo-
nents for these high-frequency filters.
Equation 7: Noise Equation for Transimpedance
(8)
Amplifier
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22
30068031
30068036
FIGURE 20. Low-Noise Magnetic Media Equalizer
FIGURE 19. Low Pass Sallen-Key Active Filter Topology
LOW-NOISE MAGNETIC MEDIA EQUALIZER
Figure 20 shows a high-performance low-noise equalizer for
such applications as magnetic tape channels using the
LMH6629. The circuit combines an integrator (used to limit
noise) with a bandpass filter (used to boost the response cen-
tered at a frequency or over a band of interest) to produce the
low-noise equalization. The circuit’s simulated frequency re-
sponse is illustrated in Figure 21.
In this circuit, the bandpass filter center frequency is set by
For higher selectivity, use high C values; for wider bandwidth,
use high L values, while keeping the product of L and C values
the same to keep fc intact. The integrator’s -3dB roll-off is set
by
30068032
FIGURE 21. Equalizer Frequency Response
LOW-NOISE SINGLE ENDED TO DIFFERENTIAL
CONVERTER / DRIVER
If
Many high-resolution data converters (ADC’s) require a dif-
ferential input driver. In order to preserve the ADC’s dynamic
range, the analog input driver must have a noise floor which
is lower than the ADC’s noise floor. For an ADC with N bits,
the quantization Signal-to-noise ratio (SNR) is 6.02* N + 1.76
in dB. For example, a 12-bit ADC has a SNR of 74 dB (= 5000
V/V). Assuming a full-scale differential input of 2Vpp (0.707
V_RMS), the quantization noise referred to the ADC’s input
is ~140 μV_RMS (= 0.707 V_RMS / 5000 V/V) over the band-
width “visible” to the ADC. Assuming an ADC input bandwidth
of 20 MHz, this translates to just 25 nV/RtHz (= 141µV_RMS /
SQRT(20 MHz * π/2)) noise density at the output of the driver.
Using an amplifier to form the single-ended (SE) to Differential
converter / driver for such an application is challenging, es-
pecially when there is some gain required. In addition, the
input driver’s linearity (harmonic distortion) must also be high
enough such that the spurs that get through to the ADC input
are below the ADC’s LSB threshold or -73 dBc (= 20*log (1/
212)) or lower in this case. Therefore, it is essential to use a
low-noise / low-distortion device to drive a high resolution
ADC in order to minimize the impact on the quantization noise
and to make sure that the driver’s distortion does not domi-
nate the acquired data.
the integrator and the bandpass filter frequency interaction is
minimized so that the operating frequencies of each can be
set independently. Lowering the value of R2 increases the
bandpass gain (boost) without affecting the integrator fre-
quencies. With the LMH6629’s wide Gain Bandwidth (4GHz),
the center frequency could be adjusted higher without worries
about loop gain limitation. This increases flexibility in tuning
the circuit.
23
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Figure 22 shows a ground referenced bipolar input (symmet-
rical swing around 0V) SE to differential converter used to
drive a high resolution ADC. The combination of LMH6629’s
low noise and the converter architecture reduces the impact
on the ADC noise.
30068055
FIGURE 22. Low-Noise Single-Ended (SE) to Differential Converter
In this circuit, the required gain dictates the resistor ratio “K”.
With “K” and the driver output CM voltage (VO_CM) known,
VSET can be established. Reasonable values for Rf and Rg
can be set to complete the design.
From a noise point of view, concentrating only on the domi-
nant noise sources involved, here is the expression for the
expected differential noise density at the input of the ADC:
In terms of output swing, with the LMH6629 output swing ca-
pability which requires ~0.85V of headroom from either rail,
the maximum total output swing into the ADC is limited to 6.6
VPP (=(5 – 2 x 0.85V) x 2); that is true with VO_CM set to mid-
rail between V+ and V-. It should also be noted that the
LMH6629’s input CMVR range includes the lower rail (V-) and
that is the reason there is great flexibility in setting Vo_CM by
controlling VSET. Another feature is that A1 and A2 inputs act
like “virtual grounds” and thus do not see any signal swing.
Note that due to the converter’s biasing, the source, VIN,
needs to sink a current equal to VSET / RIN.
(9)
Equation 9: Converter Noise Expression
en is the LMH6629 input noise voltage and eRin_thermal is the
thermal noise of RIN. The “23” and the “22” multipliers account
for the different instances of each noise source (2 for en, and
1 for eRin_thermal
.
Equation 9 evaluated for the circuit example of Figure 22 is
shown below:
Equation 10: Converter Noise Expression
The converter example shown in Figure 22 operates with a
noise gain of 6 (=1+ K / 2) and thus requires that the COMP
pin to be tied low (LLP-8 package only). The 1st order ap-
proximated small signal bandwidth will be 280 MHz (=1.7
GHz / 6V/V) which is computed using 1.7GHz as the GBWP
with COMP pin LO .
(10)
Evaluated
Because of the LMH6629’s low input noise voltage (en), noise
is dominated by the thermal noise of RIN. It is evident that the
input resistor, RIN, can be reduced to lower the noise with
lower input impedance as the trade-off.
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24
LAYOUT CONSIDERATIONS
microstrip line effect. Place input and output termination re-
sistors as close as possible to the input/output pins. Traces
greater than 1 inch in length should be impedance matched
to the corresponding load termination.
National Semiconductor offers evaluation board(s) to aid in
device testing and characterization and as a guide for proper
layout. As is the case with all high-speed amplifiers, accepted-
practice RF design technique on the PCB layout is mandato-
ry. Generally, a good high-frequency layout exhibits a
separation of power supply and ground traces from the in-
verting input and output pins. Parasitic capacitances between
these nodes and ground may cause frequency response
peaking and possible circuit oscillations (see Application Note
OA-15 for more information). Use high-quality chip capacitors
with values in the range of 1000 pF to 0.1F for power supply
bypassing. One terminal of each chip capacitor is connected
to the ground plane and the other terminal is connected to a
point that is as close as possible to each supply pin as allowed
by the manufacturer’s design rules. In addition, connect a
tantalum capacitor with a value between 4.7 μF and 10 μF in
parallel with the chip capacitor.
Symmetry between the positive and negative paths in the
layout of differential circuitry should be maintained to mini-
mize the imbalance of amplitude and phase of the differential
signal.
Component value selection is another important parameter in
working with high-speed / high-performance amplifiers.
Choosing external resistors that are large in value compared
to the value of other critical components will affect the closed
loop behavior of the stage because of the interaction of these
resistors with parasitic capacitances. These parasitic capac-
itors could either be inherent to the device or be a by-product
of the board layout and component placement. Moreover, a
large resistor will also add more thermal noise to the signal
path. Either way, keeping the resistor values low will diminish
this interaction. On the other hand, choosing very low value
resistors could load down nodes and will contribute to higher
overall power dissipation and high distortion.
Harmonic Distortion, especially HD2, is strongly influenced by
the layout and in particular can be affected by decoupling ca-
pacitors placed between the V+ and V- terminals as close to
the device leads as possible.
Signal lines connecting the feedback and gain resistors
should be as short as possible to minimize inductance and
25
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin LLP
NS Package Number SDA08A
SOT23-5 Package
NS Package Number MF05A
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26
Notes
27
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Notes
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