LM8805TLX-3.0/NOPB [NSC]
IC 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA9, LEAD FREE, MICRO SMD-9, Power Management Circuit;
| 型号： | LM8805TLX-3.0/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | IC 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA9, LEAD FREE, MICRO SMD-9, Power Management Circuit |
| 文件： | 总15页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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September 8, 2011
LM8805
Microprocessor Supervisory Circuits with Power Fail
Input, Low Line Output, Manual Reset and Watchdog Timer
General Description
Features
The LM8805 microprocessor supervisory circuit provides the
maximum flexibility for monitoring power supplies and battery
controlled functions in systems without backup batteries. The
LM8805 is available in a 9-bump micro SMD package.
Standard Reset Threshold voltages:
■
Rising 2.6V
Falling 2.3V
—
—
No external components required
■
■
■
■
■
■
■
Built-in features include the following:
Manual-Reset input
Reset: Reset is asserted during power-up, power-down, and
brownout conditions. RESET is guaranteed down to VCC of
1.0V.
RESET output
Precision supply voltage monitor
Separate Power Fail comparator
±0.5% Reset threshold accuracy at room temperature
Manual Reset Input: An input that asserts reset when taken
high.
Power-Fail Input: A 1.225V threshold detector for power fail
warning, or to monitor a power supply other than VCC
±2% Reset threshold accuracy over temperature
extremes
.
Low Line Output: This early power failure warning indicator
goes low when the supply voltage drops to a value which is
2% higher than the reset threshold voltage.
Reset assertion down to 1V VCC (RESET option only)
28 µA VCC supply current
■
■
■
Available in large bump micro SMD package
Watchdog Timer: The WDI (Watchdog Input) monitors one of
the µP's output lines for activity. If no output transition occurs
during the watchdog timeout period, reset is activated.
Applications
Embedded Controllers and Processors
■
■
■
■
Intelligent Instruments
Automotive Systems
Critical µP Power Monitoring
Typical Application
30123603
© 2011 National Semiconductor Corporation
301236
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Connection Diagram
Top View
(looking from the coating side)
micro SMD 9 Bump Package
TLA09
30123601
Pin Descriptions
Pin No.
Name
Function
micro SMD
A1
MR
Manual-Reset input. When MR is triggered RESET is latched low after time tMR until there is an event on
VCC
.
B1
C1
VCC
Power Supply input.
RESET
Reset Logic Output. Reset remains low whenever VCC is below the reset threshold. It remains low for
tRP after VCC rises above the reset threshold.
C2
C3
PFO
LLO
Power-Fail Logic Output. When PFI is below VPFT, PFO goes low; otherwise, PFO remains high.
Low-Line Logic Output. Early Power-Fail warning output. Low when VCC falls below VLLOT (Low-Line
Output Threshold). This output can be used to generate an NMI (Non-Maskable Interrupt) to provide an
early warning of imminent power-failure.
B3
A3
GND
WDI
Ground reference for all signals.
Watchdog Input Transition Monitor: If no transition activity occurs for a period exceeding tWD (Watchdog
Timeout Period), RESET is latched until there is an event on VCC
.
A2
B2
PFI
NC
Power-Fail Comparator Input. When PFI is less than VPFT (Power-Fail Reset Threshold), the PFO goes
low; otherwise, PFO remains high.
No Connect. Test input used at factory only. Leave floating.
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2
Block Diagram
30123605
Ordering Information LM8805
Order Number
LM8805TLE/NOPB
LM8805TLX/NOPB
LM8805TLE-3.0/NOPB
LM8805TLX-3.0/NOPB
Option
2.6V
Production Identification
Supplied as
V3
V3
V4
V4
250 Tape & Reel
3000 Tape & Reel
250 Tape & Reel
3000 Tape & Reel
2.6V
3.0V
3.0V
3
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Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Temperature Range
−40°C ≤ TJ ≤ 85°C
Thermal Properties (Note 1)
Junction-To-Ambient Thermal
Resistance
Supply Voltage (VCC
All Other Inputs
)
−0.3V to 6.0V
−0.3V to VCC + 0.3V
+150°C
Junction Temperature (TJ-MAX
)
θ
θ
J-A JEDEC Board
J-A 4Layer Board
110°C/W
68°C/W
ESD Ratings (Note 2)
Human Body Model
Machine Model
2.0kV
150V
Power Dissipation
(Note 3)
LM8805 Electrical Characteristics
Limits in the standard typeface are for TJ = 25°C and limits in boldface type apply over full operating range. Unless otherwise
specified: VCC = +2.2V to 5.5V.
Symbol
Parameter
Conditions
Min
1.0
Typ
Max
Units
POWER SUPPLY
VCC
Operating Voltage
Range: VCC
5.5
50
V
ICC
VCC Supply Current All inputs = VCC; all outputs floating
µA
28
RESET THRESHOLD
VRST
Reset Threshold
VCC falling
−0.5
+0.5
−2
+2
VRST
300
%
VCC falling: TA = 0°C to 70°C
−1.5
+1.5
VRSTH
tRP
Reset Threshold
Hysteresis
200
400
mV
Reset Timeout
Period
Reset Timeout Period = E, J, N, S
VCC falling at 1mV/µs
1
1.4
20
2
ms
µs
tRD
RESET
VOL
VCCto Reset Delay
RESET
VCC > 1.0V, ISINK = 50µA
0.3
0.3
0.3
0.3
0.4
VCC > 1.2V, ISINK = 100µA
VCC > 2.25V, ISINK = 900µA
VCC > 2.7V, ISINK = 1.2mA
VCC > 4.5V, ISINK = 3.2mA
VCC > 2.25V, ISOURCE = 300µA
VCC > 2.7V, ISOURCE = 500µA
VCC > 4.5V, ISOURCE = 800µA
V
VOH
RESET
0.8 VCC
0.8 VCC
VCC − 1.5V
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4
Symbol
WDI
Parameter
Conditions
Min
Typ
Max
Units
WDI
WDIT
tWD
Watchdog Input
Current
VWDI = VCC
−1
0.4
+1
1.5
µA
V
Watchdog Input
Threshold
Watchdog Timeout Watchdog Timeout Period
Period
90,000
128,000
160,000
ms
(Note 4)
PFI
VPFT
PFI Input Threshold
1.200
1.225
1.250
V
VPFTH
PFI/MR Threshold
Hysteresis
PFI/MR falling: VCC = VRST MAX to 5.5V
0.0032•VRST
mV
nA
IPFI
Input Current
−75
75
MR
VMRT
RMR
MR Input Threshold
0.4
1.5
V
MR Pull-down
Resistance
90
115
12
140
kΩ
tMD
tMR
MR to Reset Delay
MR Pulse Width
µs
µs
25
PFO, LLO
VOL
PFO, LLO Output
Voltage
VCC > 2.25V, ISINK = 900µA
VCC > 2.7V, ISINK = 1.2mA
VCC > 4.5V, ISINK = 3.2mA
VCC > 2.25V, ISOURCE = 300µA
VCC > 2.7V, ISOURCE = 500µA
VCC > 4.5V, ISOURCE = 800µA
0.3
0.3
0.4
V
VOH
0.8 VCC
0.8 VCC
VCC − 1.5V
LLO OUTPUT
VLLOT
LLO Output
Threshold
(VLLO − VRST, VCC
falling)
1.01•VRST
1.02•VRST
1.03•VRST
V
VLLOTH
Low-Line
0.0032•VRST
20
Comparator
Hysteresis
mV
µs
tCD
Low-Line
Comparator Delay
VCC falling at 1mV/µs
5
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed conditions.
Note 2: The Human Body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin.
Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, θJ-
A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperture is calculated using:
Where the value of θJ-A for the 9-bump micro SMD package is 110°C/W in a typical PC board.
Note 4: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
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6
Typical Performance Characteristics
Supply Current vs Supply Voltage
3.3V Supply Current vs Temperature
30123611
30123615
Normalized Reset Threshold Voltage vs Temperature
Reset Timeout Period vs VCC
30123612
30123632
Reset Timeout Period vs Temperature
Watchdog Timeout Period vs Temperature
30123610
30123613
7
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Max. Transient Duration vs Reset Comparator Overdrive
(VCC = 3.3V)
Low-Line Comparator Propagation
Delay vs Temperature
30123614
30123616
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8
WATCHDOG TIMER INPUT (WDI)
Circuit Information
The watchdog timer input monitors one of the
microprocessor's output lines for activity. Each time a transi-
tion occurs on this monitored line, the watchdog counter is
reset. However, if no transition occurs and the timeout period
is reached, the LM8805 assumes that the microprocessor has
locked up and the reset output is activated.
RESET OUTPUT
The Reset input of a µP initializes the device into a known
state. The LM8805 microprocessor supervisory circuit asserts
a forced reset output to prevent code execution errors during
power-up, power-down, and brownout conditions.
When tripped by the watchdog timer, the RESET pin will stay
asserted and ignore any further activity from the WDI input.
RESET can only be deasserted by a VCC voltage event. Refer
to Figure 1 for more details
RESET is guaranteed valid for VCC > 1V. Once VCC exceeds
the reset threshold, an internal timer maintains the output for
the reset timeout period. After this interval, reset goes high.
The LM8805 offers an active-low RESET.
WDI is a high impedance input.
Any time VCC drops below the reset threshold (such as during
a brownout), the reset activates. When VCC again rises above
the reset threshold, the internal timer starts. Reset holds until
VCC exceeds the reset threshold for longer than the reset
timeout period. After this time, reset releases.
SPECIAL PRECAUTIONS FOR THE MICRO SMD
PACKAGE
As with most integrated circuits, the LM8805 is sensitive to
exposure from visible and infrared (IR) light radiation. Unlike
a plastic encapsulated IC, the micro SMD package has very
limited shielding from light, and some sensitivity to light re-
flected from the surface of the PC board or long wavelength
IR entering the die from the side may be experienced. This
light could have an unpredictable affect on the electrical per-
formance of the IC. Care should be taken to shield the device
from direct exposure to bright visible or IR light during oper-
ation.
The Manual Reset input (MR) will initiate a forced reset also.
See the Manual Reset Input section.
RESET THRESHOLD
The LM8805 is available with a reset threshold of 2.3V with a
hysteresis of 300mV equating to a rising turn-on threshold of
2.60V.
MANUAL RESET INPUT (MR)
Many µP-based products require a manual reset capability,
allowing the operator to initiate a reset. The MR input is fully
debounced and provides an internal 115 kΩ pull-down. When
the MR input pulses high, reset is asserted after a typical de-
lay of 12 µs. Reset remains active until power is recycled and
a VCC rising edge is detected.
MICRO SMD MOUNTING
The micro SMD package requires specific mounting tech-
niques which are detailed in National Semiconductor Appli-
cation Note AN-1112. Referring to the section Surface Mount
Technology (SMT) Assembly Considerations, it should be
noted that the pad style which must be used with the 9-pin
package is the NSMD (non-solder mask defined) type.
POWER-FAIL COMPARATOR (PFI/PFO)
For best results during assembly, alignment ordinals on the
PC board may be used to facilitate placement of the micro
SMD device.
The PFI is compared to a 1.225V internal reference, VPFT. If
PFI is less than VPFT, the Power Fail Output PFO drops low.
The power-fail comparator signals a falling power supply, and
is driven typically by an external voltage divider that senses
either the unregulated supply or another system supply volt-
age.
LOW-LINE OUTPUT (LLO)
The low-line output comparator is typically used to provide a
non-maskable interrupt to a µP when VCC begins falling.
LLO monitors VCC and goes low when VCC falls below VLLOT
(typically 1.02 • VRST) with hysteresis of 0.0032 • VRST
.
9
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Timing Diagrams
30123628
FIGURE 1. LM8805 Reset Time with MR and WDI
30123629
FIGURE 2. LLO Output
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10
30123630
FIGURE 3. PFI Comparator Timing Diagram
11
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Physical Dimensions inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
1. EPOXY COATING
2. 63Sn/37Pb EUTECTIC BUMP
3. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD.
4. PIN 1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION. REMAINING PINS ARE NUMBERED COUNTER CLOCK-
WISE.
5. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS PACKAGE LENGTH AND X3 IS PACK-
AGE HEIGHT.
9 bump micro SMD Package
NS Package Number TLA09ZZA
The dimensions of X1, X2 and X3 are given below
X1 = 1.465mm
X2 = 1.465mm
X3 = 0.600mm
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12
Notes
13
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Notes
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相关型号：
LM8805TLX/NOPB
IC 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA9, LEAD FREE, MICRO SMD-9, Power Management Circuit
NSC
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