LM9011MX/NOPB [NSC]
SPECIALTY INTERFACE CIRCUIT, PDSO28, PLASTIC, SOIC-28;
| 型号： | LM9011MX/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | SPECIALTY INTERFACE CIRCUIT, PDSO28, PLASTIC, SOIC-28 光电二极管 接口集成电路 |
| 文件： | 总16页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2003
LM9011
Electronic Ignition Interface
General Description
Key Specifications
The LM9011 is an interface circuit which integrates the tim-
ing detection and logic control functions required for an
automotive electronic ignition system into one device.
Features
n Single 5V supply operation
n VR Sensor Interface with dynamic hysteresis
A VRS interface is provided for crankshaft position informa-
tion via a toothed-wheel.
n Four Channel Electronic Timing spark driver with output
diagnostics
n Electronic Timing Interface spark driver output voltage
from 5V to 16V
n One Non-Inverting voltage comparator with hysteresis
n Three Inverting voltage comparators with hysteresis
Four voltage comparators are provided for hardware diag-
nostics.
An electronic timing interface with output fault diagnostics is
provided to enable a micro-processor to drive an external
four channel ignition spark circuit.
The LM9011 is fully specified over the automotive tempera-
ture range of -40˚C to +125˚C, and is available in a 28 pin
Small Outline surface mount package.
Connection Diagram
Top View
10126401
Ordering Information LM9011M
See NS Package M28B
© 2003 National Semiconductor Corporation
DS101264
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Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 3)
Voltage
-0.3V to +7.0V
-0.3V to 26.5V
+/-3mA
VCC Voltage
4.75V to 5.25V
VCC to 26V
S_HI Voltage
S_HI Voltage
VR_HI and VR_LO Inputs
Comparator Inputs
Sx Outputs
-0.3V to S_HI +0.3V
-0.3V to VCC +0.3V
+/-2.75mA
-0.3V to +7.0V
-0.3V to +7.0V
+/-2000V
Comparator Inputs
VR_HI and VR_LO Inputs
Timing Interface Inputs
Thermal Resistances (M28B):
Junction to Case (θJ-C)
Junction to Ambient (θJ-C)
Timing Interface Inputs
ESD Susceptibility (Note 3)
Maximum Junction Temperature
Storage Temperature Range
Lead Soldering Information:
Vapor Phase (60 Seconds)
Infrared (15 Seconds)
-0.3V to VCC +0.3V
150˚C
15˚C/W
69˚C/W
-65˚C to +150˚C
215˚C
220˚C
DC Electrical Characteristics The following specifications apply for VCC = 5V, VRESET = VCC, VS_HI
=
VCC, -40˚C ≤ TA ≤ +125˚C, Application Circuit Figure 16, unless otherwise specified.
Symbol
Parameter
Conditions
RESET, IN_4 = VCC
Minimum
Maximum
Units
ENB, D0, D1, IN_1, IN_2, IN_3 =
0V
I
Supply Current
25
mA
CC
VR_HI = +12.5µA
VR_LO = -12.5µA
Comparators
TH1 Input Threshold
V
VIN _1 Decreasing from VCC to 0V
VCC X 0.435 VCC X 0.485
VCC X 0.435 VCC X 0.485
V
V
V
V
>
until VOUT_1 VCC/2
VTH
VTH
VTH
2
3
4
Input Threshold
Input Threshold
Input Threshold
VIN_2 Decreasing from VCC to 0V
>
until VOUT_2 VCC/2
VIN_3 Decreasing from VCC to 0V
VCC X 0.40
VCC X 0.45
150
VCC X 0.45
VCC X 0.50
>
until VOUT_3 VCC/2
VIN_4 Decreasing from VCC to 0V
<
until VOUT_4 VCC/2
VHYST
IBIAS
Input Hysteresis
All Comparators
400
750
mV
µA
Input Bias Current
IN_1, IN_2, IN_3 = 0V ≤ VIN≤VCC
IN_4 = 0V ≤ VIN_4 ≤ VCC-1V
ILOAD = -100µAV
VOH
VOL
Output High Voltage
Output Low Voltage
VCC -1
VCC -1
V
ILOAD = +100µAV
750
mV
VR Sensor Interface
VOH
Output High Voltage
ILOAD = -15µA
V
VR_HI= -1mA, VR_LO = +1mA
Load = +15µA
VOL
Output Low Voltage
750
mV
VR_HI=+1mA, VR_LO = -1mA
-40˚C ≤ TA≤ +25˚C
TA = +85˚C (Note 5)
TA = +125˚C
0.5
0.6
1.0
75
3.0
3.5
uA Pk-Pk
uA Pk-Pk
uA Pk-Pk
uA Pk
Minimum Detect Differential Input
Current (Note 4)
IDIFF(MIN)
5.0
I
I
HYS1
HYS2
Input Hysteresis (Note 4)
Input Hysteresis (Note 4)
IDIFF = 1mA pk-pk
250
625
IDIFF = 2.5mA pk-pk
185
uA Pk
Electronic Timing Interface
VIH
VIL
IIH
Input Logic 1 D0, D1, ENB, RESET
VCC X 0.7
V
V
Input Logic 0 D0, D1, ENB, RESET
Input High Current Inputs D0, D1,
RESET
VCC X 0.3
10
VIN = VCC
VIN = VCC
µA
IIH
Input High Current Input ENB
125
µA
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2
DC Electrical Characteristics The following specifications apply for VCC = 5V, VRESET = VCC, VS_HI = VCC
,
-40˚C ≤ TA ≤ +125˚C, Application Circuit Figure 16, unless otherwise specified. (Continued)
Symbol
Parameter
Input Low Current Inputs D0, D1,
ENB
Conditions
Minimum
3.75
14
Maximum
Units
IIL
VIN = 0V
VIN = 0V
-10
µA
IIL
Input Low Current Input RESET
Output High Voltage Outputs S1,
S2, S3, S4
-125
300
µA
V
VOH
ILOAD = -10mA, VS_HI = 5V
ILOAD = 1mA, VS_ HI = 5V
ILOAD = -10mA, VS_HI = 16V
ILOAD = 1mA, VS_HI =16V
ILOAD = -10mA, VS_HI =26V
ILOAD = 1mA, VS_HI =26V
VOL
VOH
VOL
VOH
VOL
Output Low Voltage Outputs S1,
S2, S3, S4
mV
V
Output High Voltage Outputs S1,
S2, S3, S4
Output Low Voltage Outputs S1,
S2, S3, S4
450
600
mV
V
Output High Voltage Outputs S1,
S2, S3, S4
22
Output Low Voltage Outputs S1,
S2, S3, S4
mV
VOH
VOL
FAULT Pin Output High Voltage
FAULT Pin Output Low Voltage
IFAULT = -100µA, no fault
IFAULT = 100µA, any fault
VCC -1
VCC X 0.2
-12
V
mV
V
750
VFAULT Fault Treshold Voltage Outputs S1, Sx Output Short Fault
S2, S3, S4
VCC X 0.5
IFOL
TRI-STATE Output Current Outputs VRESET = 0V, VS _HI = 5V
S1, S2, S3, S4 RLOAD = 10KΩ
-50
µA
AC Electrical Characteristics
The following specifications apply for VCC = 5V, VS_HI = VCC, VRESET = VCC, -40˚C≤TA≤+125˚C. The AC Timing Characteristics
are not production tested. Minimum and Maximum limits are guaranteed by device characterization.
Symbol
Parameter
Conditions
Minimum
Maximum
Units
Comparators
TRISE
TFALL
Output Rise Time
Output Fall Time
10% to 90%, CLOAD = 25pF
90% to10%, CLOAD = 25pF
5
5
µs
µs
VR Sensor Interface (Note 4)
TRISE
Output Rise Time
10% to 90%, CLOAD = 100pF,
RLOAD = 100KΩ
10
5
µs
µs
TFALL
Output Fall Time
90% to10%, CLOAD = 100pF,
RLOAD = 100kΩ
IDIFF = 5µA pk-pk, FVRS = 200Hz
IDIFF = 50µA pk-pk, FVRS = 2.5KHz
CLOAD = 100pF, RLOAD = 100KΩ
IDIFF = 5µA pk-pk
1
ms
µs
TDELAY Zero Crossing Delay Time (Note 6)
FMAX Maximum VRS Frequency
Electronic Timing Interface
10
50
KHz
T
RISE1
Sx Output Rise Time
Sx Rises10% to 90%
CLOAD = 6.8nF, RLOAD = 10KΩ
CLOAD = 12.7nF, RLOAD = 10KΩ
Sx Falls 90% to 10%
5
8
µs
µs
T
FALL1
Sx Output Fall Time
CLOAD = 6.8nF, RLOAD = 10KΩ
CLOAD = 12.7nF, RLOAD = 10KΩ
15
25
µs
µs
µs
µs
TSETUP
THOLD
SetupTime (Notes 7, 8 and 9)
Hold Time
1
0.5
3
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AC Electrical Characteristics (Continued)
The following specifications apply for VCC = 5V, VS_HI = VCC, VRESET = VCC, -40˚C≤TA≤+125˚C. The AC Timing Characteristics
are not production tested. Minimum and Maximum limits are guaranteed by device characterization.
Symbol
Parameter
Fault Delay Time
Conditions
Sx Output Short to Ground Fault
From ENB = 1 to FAULT ≤ 10%
CFAULT = 25pF
Minimum
Maximum
Units
TDF1
2
µs
T
DF2
Fault Delay Time
Sx Output Short to Battery Fault
From ENB = 0 to FAULT ≤ 10%
CFAULT = 25pF
2
2
µs
µs
TTRI
TRI-STATE Delay Time
From RESET = 0 to All Sx Outputs
Off
TRISE
2
Fault Pin Rise Time
False Fault Time
10% to 90%, CFAULT = 25pF
From ENB = 0 to FAULT ≥ 90%
CFAULT = 25pF
5
µs
TFF(OFF)
TFF(ON)
TUDF
CLOAD = 6.8nF, RLOAD = 10KΩ
CLOAD = 12.7nF, RLOAD = 10KΩ
From ENB = 1 to FAULT ≥ 90%
CFAULT = 25pF
25
30
µs
µs
False Fault Time
CLOAD = 6.8nF, RLOAD = 10KΩ
CLOAD = 12.7nF, RLOAD = 10KΩ
From ENB = 0 for 8uSec, to Valid
FAULT
8
µs
µs
10
Undefined Fault Time
CLOAD = 6.8nF, RLOAD = 10KΩ
CLOAD = 12.7nF, RLOAD = 10KΩ
20
25
µs
µs
Note 1: Absolute Maximum Ratings indicate the limits beyond which damage may occur.
Note 2: ESD Ratings is with Human Body Model: 100pF discharged through a 1500Ω resistor.
Note 3: Operating ratings indicate conditions for which the device is intended to be functional, but may not meet the guaranteed specific performance limits. For
guaranteed specifications and conditions, see the Electrical Characteristics.
Note 4: Tested per VR Sensor Interface test circuit. See Figure 8 and Figure 9.
Note 5: Minimum Detect Current is not production tested at +85C. Specifications is guaranteed through device characterization and Test Limits at 25˚C and 125˚C.
Note 6: VR Sensor Interface Tdelay, measured from VR input sine wave zero-crossing to VR_OUT going high. See Figure 9.
>
Note 7: Electronic Timing Interface Tsetup, minimum time between Vcc 4.75V and RESET = 1.
Note 8: Electronic Timing Interface Tsetup, minimum time between RESET = 1 and D0 = 1.
Note 9: Electronic Timing Interface Tsetup, minimum time between D0 / D1 = valid and ENB = 1.
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Typical Performance Characteristics
Supply Current vs Temperature
Ifol Source Current vs Temperature
10126403
10126404
VFault Threshold vs Temperature
Sx Source Current vs S_HI Voltage
10126405
10126406
Sx Sink Current vs S_HI Voltage
Sx Vol vs Sx Sink Current
10126407
10126408
5
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Typical Performance Characteristics (Continued)
VRS Interface Minimum Detect
vs Temperature
Sx Voh vs Sx Source Current
10126409
10126410
VRS Interface Minimum Detect
vs VR_BIAS
10126411
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Timing Diagrams
10126412
FIGURE 1. Electronic Timing Interface Timing Diagram
10126413
FIGURE 2. Fault Pin Timing During Sx Shorted to Ground
7
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Timing Diagrams (Continued)
10126414
FIGURE 3. Fault Pin Timing During Sx Shorted to Battery
10126415
FIGURE 4. False FAULT Time for Disabled Sx Output
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8
Timing Diagrams (Continued)
10126416
FIGURE 5. False FAULT Time for Enabled Sx Output
10126417
FIGURE 6. Time for Valid Fault Detection
9
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Timing Diagrams (Continued)
10126418
FIGURE 7. Electronic Timing Interface Typical Waveforms
10126419
FIGURE 8. VR Interface Test Circuit
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10
Timing Diagrams (Continued)
10126421
FIGURE 10. VR Sensor Interface Block Diagram
Differential voltages of 500mV peak-to-peak to 500V peak-
to-peak can be processed with the specified 100KΩ series
resistor on each input. Numerous variables will determine
the output voltage signal from a VR sensor across a fre-
quency range. The input resistors can be scaled from typi-
cally 50KΩ to 200KΩ to keep the differential input current
with-in the recommended range for a given VR Sensor out-
put voltage. Bypass capacitors can be added to form a low
pass filter to limit the differential input signal at the higher
frequencies.
The VR Sensor interface utilizes a dynamic hysteresis which
will increase the hysteresis level as the input signal from the
VR Sensor increases. The circuit requires two external com-
ponents to fully implement the hysteresis function: a capaci-
tor on VR_FC to filter and store the peak detector signals;
and a 150KΩ resistor on VR_BIAS to set a reference current
for the hysteresis circuit. The typical value range for the peak
detector storage capacitor is 0.1µF to 0.47µF.
10126420
FIGURE 9. VR Interface Timing Diagram
Circuit Description
The peak detector has an internal 3KΩ (typical) current
limiting resistor to Vcc for charging the storage capacitor. An
external resistor in parallel with the peak detector storage
capacitor is used to set the RC discharge rate of the peak
detector capacitor.
VR SENSOR INTERFACE
The differential inputs, VR_HI and VR_LO are low imped-
ance inputs with a DC voltage bias of one half of Vcc, Both
inputs require equal value series resistance on their respec-
tive pins to convert the VR sensor voltage to a differential
input current. The differential input current range is typically
2.5µA peak-to-peak to 2.5mA peak-to-peak. Each input has
active current limiting that will clamp the current at typically
+/-5mA. This is intended for short circuit protection and not
for input signal limiting.
For input levels greater than typically 10µA peak-to-peak the
voltage on the peak detector output pin VR_FC is used to
actively derive the hysteresis level. The active hysteresis will
typically be 30% of the peak input signal. As the input level
falls below typically 10µA peak-to-peak the hysteresis level
will begin to rise as the static hysteresis level takes effect.
The static hysteresis level is set by the current out of the
VR_BIAS pin and is a constant level of typically 1µA peak
with a VR_BIAS resistor of 150KΩ. This static hysteresis
level acts as the minimum detect threshold as there will be
no output if the input signal is not greater than the static
hysteresis level.
The VR_BIAS resistor can be scaled from typically 50KΩ to
500KΩ, but the practical range is typically 75KΩ to 300KΩ.
Increasing the resistance (i.e. reducing the current) will lower
the minimum hysteresis level. Conversely, reducing the re-
sistance will raise the minimum hysteresis level. Since the
VR_BIAS current is modified by the same square root circuit
used for the input signal, the relationship between the VR-
_BIAS resistor value and the minimum detect level is not
11
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their inverting-inputs are brought out. The remaining one
comparator has its inverting input tied to the internal voltage
reference, and its non-inverting input is brought out. All four
comparators include hysteresis to improve noise immunity.
The comparator outputs are internally pulled up to VCC. Any
un-used comparator should have its input connected to de-
vice ground.
Circuit Description (Continued)
linear. For VR_BIAS values greater than 500KΩ, the mini-
mum detect level is typically determined more by the internal
device offsets, and thermal effects.
10126422
FIGURE 11. Voltage Comparator Block Diagram
10126423
VOLTAGE COMPARATORS
The circuit includes four general purpose voltage compara-
tors that use an internal reference voltage to set their voltage
thresholds. Three of the comparators have their non-
inverting inputs tied to the internal reference voltage, and
FIGURE 12. Electronic Timing Interface Block Diagram
10126424
FIGURE 13. Output Fault Detection Block Diagram
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Circuit Description (Continued)
Electronic Timing Interface
Inputs
Output
RESET
ENB
D0
X
X
0
D1
X
X
0
S1
Tri
L
S2
Tri
L
S3
Tri
L
S4
Tri
L
0
1
1
1
1
1
X
0
1
1
1
1
H
L
L
L
L
1
0
H
L
L
L
0
1
L
H
L
L
1
1
L
L
H
FIGURE 14. Truth Table for Electronic Timing Interface
The Electronic Timing Interface provide signals to the spark
module from the micro-processor. The interface requires four
input data signals, and provides four output control chan-
nels.
Pins D0 and D1 are used select an output, and ENB will
enable the selected output. The outputs have have active
pull up to S_HI, and the active pull down to Ground. The
default not enabled output conditions is low, and the enabled
output condition is high. Only one output can be enabled
(high) at a time. The outputs are not latched in any state and
will follow the input selected with D0 and D1 as long as ENB
is high.
The interface also provides one output channel for diagnos-
tic information for any open or shorted loads on S1 to S4.
The RESET pin has an internal pull-up resistor to VCC of
typically 100KΩ, and the ENB pin has an internal pull-down
resistor to ground of typically 100KΩ.
To put the outputs into the TRI-STATE mode at power-on,
the RESET pin should be held low until VCC is above 4.75V.
This can be accomplished by micro-processor control, or by
adding a capacitor from the RESET pin to ground.
The detection of an output shorted to ground, or battery, is
dependent on the status of ENB. While ENB is logical 0, all
of the outputs are forced low and the Short to Battery fault
detection circuitry is active. A Short to Battery is detected by
monitoring the voltage on the output pins. If the voltage on
any output pin is above the Fault Threshold Voltage (VFAULT
)
The RESET pin is used to disable the spark driver outputs by
putting them in a TRI-STATE mode. While in the TRI-STATE
mode the Open Output Fault detection circuitry is active. An
the FAULT pin will go low. The output current sink is limited
to typically 8mA. The short to battery condition must be able
to provide enough current to overcome the current limit and
raise the output pin voltage above the VFAULT threshold.
open Output is detected by forcing a small current (IFOL
)
through the outputs to the loads, and monitoring the voltage
on the output pins rises above the Output Fault Threshold
Voltage (VFAULT) the FAULT pin will be forced low. The intent
is to detect an open wire condition, and not necessarily to
detect a local resistance threshold.
When ENB is logical 1, the selected output will be high and
the Short to Ground detection circuitry is active. A Short to
Ground is detected by monitoring the voltage on the output
pins. If the voltage on the selected output pin is below the
Fault Threshold Voltage (VFAULT) the FAULT pin will go low.
The output current source is from S_HI limited to typically
25mA to 50mA across the S_HI voltage range. The short to
ground condition must be allow enough resistance to allow
the output pin voltage to fall below the VFAULT threshold with
the output sourcing short circuit current. Typically, a short to
ground which has 100 Ohms of resistance, or more, can not
be reliably detected. Typically, a short to ground of 20 Ohms,
or less, can be reliably detected across the entire S_HI
voltage range and device operating temperature range. Note
that if any output has a Short to Battery fault, a Short to
Note that if any output has a Short to battery fault, the fault
pin will go low during this TRI-STATE mode. The internal
comparator is unable to discern why an output pin may be
above the Fault Threshold Voltage, only that it is. In any
case, a fault is reported, even if it is not the anticipated fault.
The TRI-STATE mode is a latched condition. For the outputs
to come out of the TRI-STATE mode, the RESET pin must be
high, and then the data input pin D0 must toggle from a low
state to a high state. The state of the outputs will now be set
by the data inputs D0 and D1, and the ENB input. If ENB is
low when the TRI-STATE mode is cleared, all of the outputs
will go low.
13
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Circuit Description (Continued)
10126425
FIGURE 15. FAULT Pin Output During Normal Operation
Ground cannot be detected. The internal logic is unable to
discern which output pin is above the Fault Threshold Volt-
age, only that a pin is. Thus, the logical requirement of an Sx
pin voltage above the Fault Threshold voltage is met and no
fault is reported.
pin cannot change instantly, the FAULT pin will go low during
the output transition times. The FAULT pin will stay low until
the output voltage rises above, or falls below, the active fault
threshold. See Figure 15.
When switching the outputs from the active mode to the
TRI-STATE mode the ENB should be taken low first. This will
take all of the outputs low. Then the RESET pin can be taken
low. This will eliminate false ’open’ faults that will be gener-
ated while waiting for the one output that was high, to
discharge any capacitance below the VFAULT threshold.
The output rise and fall times are basically a function of the
output current drive (source and sink) and the output load
characteristics. Due to the scaling of the output stages, and
variations in the value of S_HI, the fall time will typically be
two to ten times longer than the rise time for a given capaci-
tive load.
Since the output fault detection mode changes immediately
with the status of the ENB pin, and the voltage on the output
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14
Circuit Description (Continued)
10126426
FIGURE 16. Typical Application
15
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Physical Dimensions inches (millimeters)
unless otherwise noted
Note: Unless otherwise specified.
1. STANDARD LEAD FINISH TO BE 200 MICROINCHES / 5.08 MICROMETERS MINIMUM LEAD / TIN (SOLDER) ON COPPER.
2. DIMENSION DOES NOT INCLUDE MOLD FLASH.
3. REFERENCE JEDEC REGISTRATION MS-013, VARIATION AE, DATED MAY 1990.
28-LEAD MOLDED PLASTIC SMALL OUTLINE PACKAGE
NS Package Number M28B
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