LM9801 [NSC]
Greyscale/24-Bit Color Linear CCD Sensor Processor; 灰度/ 24位彩色线性CCD传感器处理器
| 型号： | LM9801 |
| 厂家： | 
National Semiconductor |
| 描述： | Greyscale/24-Bit Color Linear CCD Sensor Processor |
| 文件： | 总34页 (文件大小：512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1996
LM9801 8-Bit Greyscale/24-Bit Color Linear
CCD Sensor Processor
General Description
Features
Y
2.5 Million pixels/s conversion rate
The LM9801 is a high performance integrated signal proc-
essor/digitizer for linear CCD image scanners. The LM9801
performs all the analog processing (correlated double sam-
pling for black level and offset compensation, pixel-by-pixel
gain (shading) correction, and 8-bit analog-to-digital conver-
sion) necessary to maximize the performance of a wide
range of linear CCD sensors.
Y
Pixel-rate shading correction for individual pixels maxi-
mizes dynamic range and resolution, even on ‘‘weak’’
pixels
Y
Y
Implements Correlated Double Sampling for minimum
noise and offset error
Reference and signal sampling points digitally con-
trolled in 25 ns increments for maximum performance
Generates all necessary CCD clock signals
Compatible with a wide range of linear CCDs
Supports some Contact Image Sensors (CIS)
TTL/CMOS input/output compatible
The LM9801 can be digitally programmed to work with a
wide variety of CCDs from different manufacturers. An inter-
nal configuration register sets CCD and sampling timing to
maximize performance, simplifying the design and manufac-
turing processes.
Y
Y
Y
Y
The LM9801 can be used with parallel output color CCDs. A
signal inversion mode eases use with CIS sensors. For com-
plementary voltage reference see the LM4041.
Key Specifications
Y
Resolution
8 Bits
Y
Pixel Conversion Rate
2.5 MHz
Applications
Y
Y
a
a
g
Supply Voltage
5V
5%
Color and Greyscale Flatbed and Sheetfed Scanners
Y
Supply Voltage (Digital I/O)
a
Power Dissipation
Y
Fax and Multifunction Peripherals
g
g
3.3V
10% or 5V
5%
Y
Digital Copiers
Y
230 mW (max)
Y
General Purpose Linear CCD Imaging
Connection Diagrams
TL/H/12814–1
TL/H/12814–2
Ordering Information
s
s
a
Commercial (0 C
§
LM9801CCV
T
A
70 C)
§
Package
V52A 52-Pin Plastic Leaded Chip Carrier
VEG52A 52-Pin Thin Quad Flatpack
LM9801CCVF
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRETM is a trademark of National Semiconductor Corporation.
SPITM is a trademark of Motorola, Inc.
C
1996 National Semiconductor Corporation
TL/H/12814
RRD-B30M96/Printed in U. S. A.
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Block Diagram
TL/H/12814–3
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2
Absolute Maximum Ratings (Notes 1 and 2)
Operating Ratings (Notes 1 and 2)
Positive Supply Voltage (Va
V
A
V
)
Operating Temperature Range
T
MIN
T
A
s
s
T
e
AGND
e
e
V
D
D(I/O)
A
MAX
e
e
e
with Respect to GND
DGND
DGND
s
s
a
LM9801CCV, LM9801CCVF
0 C
§
T
70 C
§
6.5V
0.3V to Va 0.3V
(I/O)
a
a
4.75V to 5.25V
V
V
V
Supply Voltage
Supply Voltage
A
D
a
Voltage on any Input or Output Pin
Input Current at any Pin (Note 3)
Package Input Current (Note 3)
a
a
4.75V to 5.25V
g
g
25 mA
50 mA
a
a
2.7V to 5.25V
Supply Voltage
D(I/O)
–V
s
b
V
100 mV
100 mV
l
A
D
l
D(I/O)
e
Package Dissipation at T
25 C
§
(Note 4)
A
t
V
–V
A
ESD Susceptibility (Note 5)
Human Body Model
b
a
OS, REF IN Voltage Range
0.05V to V
0.05V
A
2000V
CD0–CD7, MCLK, SYNC, SDI, SCLK,
b
Soldering Information
Infrared, 10 seconds (Note 6)
a
CS, RD Voltage Range
0.05V to V
D(I/O)
0.05V
300 C
§
b
a
65 C to 150 C
Storage Temperature
§
§
Electrical Characteristics
The following specifications apply for AGND
e
20 MHz, R
e
e
e
e
a
e
a
DGND
DGND(I/O)
0V, V
V
5.0V , V
DC D(I/O)
5.0 or
A
D
a
e
a
Boldface limits apply for T
e
e
3.0V , REF IN
DC
1.225V , f
DC MCLK
25X. All LSB units are ADC LSBs unless otherwise specified.
S
e
e
e
e
T 25 C. (Notes 7, 8 and 11)
J
T
T
to T
; all other limits T
MAX
§
A
J
MIN
A
Typical
(Note 9)
Limits
Units
Symbol
Parameter
Conditions
(Note 10)
(Limits)
CCD SOURCE REQUIREMENTS FOR FULL SPECIFIED ACCURACY AND DYNAMIC RANGE (Note 11)
e
e
V
Maximum Peak CCD Differential
Signal Range
VGA Gain
VGA Gain
0 dB
9 dB
1.1
0.4
V (min)
V (min)
WHITE
V
RFT
Maximum CCD Reset FeedThrough Amplitude
2
V (min)
ADC CHARACTERISTICS
Resolution with No Missing Codes
8
Bits (min)
LSB (max)
LSB (max)
g
g
ILE
Integral Linearity Error (Note 12)
Differential Non-Linearity
1.5
1.0
DNL
PGA CHARACTERISTICS
Monotonicity
8
Bits (min)
V/V (min)
Gain
PGA Adjustment Range
e
PGA
255
2.95
2.8
Gain
e
PGA
0
Gain Error at any Gain (Note 14)
1.4
% (max)
VGA CHARACTERISTICS
Monotonicity
4
Bits (min)
dB (min)
Gain
VGA Adjustment Range
e
VGA
15
0
20log
8.95
0.42
8.5
Gain
#
e
J
VGA
Gain Error at any Gain (Note 15)
g
0.15
dB (max)
OFFSET TRIM CHARACTERISTICS
Offset DAC LSB Size
Offset DAC DNL
In Units of ADC LSBs
LSB
g
g
In Units of Offset DAC LSBs
In Units of ADC LSBs
0.25
0.9
1.6
2.5
LSB (max)
Offset Add Magnitude
LSB (min)
LSB (max)
2.0
3
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Electrical Characteristics (Continued)
e
DGND
20 MHz, R
to T
e
e
e
e
a
e a
D(I/O)
The following specifications apply for AGND
e
DGND(I/O)
0V, V
V
5.0V , V
5.0 or
e
25X. All LSB units are ADC LSBs unless otherwise specified.
A
D
DC
a
e
a
Boldface limits apply for T
3.0V , REF IN
DC
1.225V , f
DC MCLK
S
e
e
e
e
T
J
T
; all other limits T
MAX
T
25 C. (Notes 7, 8 and 11)
§
A
MIN
A
J
Typical
(Note 9)
Limits
Units
Symbol
Parameter
Conditions
(Note 10)
(Limits)
SYSTEM CHARACTERISTICS
Full Channel Gain Error
Pre-PGA Offset Error
Post-PGA Offset Error
e
e
g
g
3.0
VGA Gain
VGA Gain
Offset Add
1, PGA Gain
1, Offset DAC
0
1
0.6
% (max)
LSB
e
e
g
V
V
0
1
1
OS1
e
g
LSB
OS2
REFERENCE AND ANALOG INPUT CHARACTERSTICS
OS Input Capacitance
5
2
pF
e
OS Input Leakage Current
Measured with OS
2.45V
20
nA (max)
DC
R
REF
ADC Reference Ladder (REF OUT to
HI
500
X (min)
X (max)
950
REF IN) Impedance
1400
REF IN
Reference Voltage (Note 13)
1.19
1.26
V (min)
V (max)
1.225
DC and Logic Electrical Characteristics
e
20 MHz, R
e
e
e
e
a
e
to T
a
The following specifications apply for AGND
e a
DGND
DGND
(I/O)
0V, V
V
D
5.0V , V
DC D(I/O)
5.0 or
A
a
other limits T
e
25 C. (Notes 7 and 8)
e
e
e
T T
J
3.0V , REF IN
DC
1.225V , f
DC MCLK
25X. Boldface limits apply for T
; all
MAX
s
A
MIN
e
e
T
J
§
A
Typical
(Note 9)
Limits
Units
Symbol
Parameter
Conditions
(Note 10)
(Limits)
CD0–CD7, MCLK, SYNC, SDI, SCLK, CS, RD DIGITAL INPUT CHARACTERISTICS
e
e
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Input Leakage Current
Input Capacitance
V
V
5.25V
3.6V
2.0
2.0
V (min)
V (min)
IN(1)
D(I/O)
D(I/O)
e
e
V
IN(0)
V
V
4.75V
2.7V
0.8
0.7
V (max)
V (max)
D(I/O)
D(I/O)
e
e
I
V
V
V
D
0.1
mA
mA
IN
IN
b
DGND
0.1
IN
C
5
pF
IN
DD0–DD7, EOC, CCLK, SDO DIGITAL OUTPUT CHARACTERISTICS
e
e
e
e
e b
e b
V
Logical ‘‘1’’ Output Voltage
V
D(I/O)
V
D(I/O)
V
D(I/O)
V
D(I/O)
4.75V, I
4.75V, I
360 mA
10 mA
2.4
4.4
2.1
2.5
V (min)
V (min)
V (min)
V (min)
OUT(1)
OUT
OUT
e b
2.7V, I
2.7V, I
360 mA
10 mA
OUT
e b
OUT
e
e
e
1.6 mA
V
Logical ‘‘0’’ Output Voltage
V
V
5.25V, I
OUT
0.4
0.4
V (max)
V (max)
OUT(0)
D(I/O)
e
3.6V, I
OUT
1.6 mA
D(I/O)
e
e
I
TRI-STATE Output Current
É
(DD0–DD7 only)
V
V
DGND
0.1
b
0.1
mA
mA
OUT
OUT
V
D
OUT
C
OUT
TRI-STATE Output Capacitance
5
pF
w1, w2, RS, TR DIGITAL OUTPUT CHARACTERISTICS
e
e
e b
e b
V
Logical ‘‘1’’ Output Voltage
V
V
4.75V, I
4.75V, I
360 mA
10 mA
2.4
4.4
V (min)
V (min)
OUT(1)
D
OUT
D
OUT
e
e
1.6 mA
V
Logical ‘‘0’’ Output Voltage
V
D
5.25V, I
0.4
V (max)
OUT(0)
OUT
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4
DC and Logic Electrical Characteristics (Continued)
e
20 MHz, R
e
e
e
e
a
e
to T
a
The following specifications apply for AGND
e a
DGND
DGND
(I/O)
0V, V
V
D
5.0V , V
DC D(I/O)
5.0 or
A
a
other limits T
e
25 C. (Notes 7 and 8)
e
e
e
T T
J
3.0V , REF IN
DC
1.225V , f
DC MCLK
25X. Boldface limits apply for T
; all
MAX
s
A
MIN
e
e
T
J
§
A
Typical
Limits
Units
Symbol
Parameter
Conditions
(Note 9)
(Note 10)
(Limits)
POWER SUPPLY CHARACTERISTICS
I
I
I
Analog Supply Current
Digital Supply Current
Digital I/O Supply Current
Operating
Standby
25
50
32
8
mA (max)
A
mA
Operating
e
6
mA (max)
D
MCLK
0
65
mA
e
e
Operating, V
Operating, V
5.0V
3.0V
3.1
1.6
1.7
6
4
mA (max)
mA (max)
mA
D(I/O)
D(I/O)
D(I/O)
e
e
5.0V or 3.0V
MCLK
0, V
D(I/O)
AC Electrical Characteristics, MCLK Independent
e
e
e
e
e
e
e
a
e
5.0V , REF IN
DC
The following specifications apply for AGND
DGND
e
DGND
0V, V
V
D
V
(I/O)
A
D(I/O)
e
5 ns, R 25X, C (databus loading)
s
a
limits apply for T
e
e
to T
e
1.225V , f
DC MCLK
20 MHz, t
e
1/f
, t
MCLK
t
f
50 pF/pin. Boldface
MCLK
r
L
e
e
e
T
J
T
T
; all other limits T
MAX
25 C. (Notes 7 and 8)
§
A
J
MIN
A
Typical
(Note 9)
Limits
Units
Symbol
Parameter
Conditions
(Note 10)
(Limits)
f
Maximum MCLK Frequency
Minimum MCLK Frequency
20
1
MHz (min)
MHz (max)
MCLK
MCLK Duty Cycle
30
70
40
60
% (min)
% (max)
t
t
t
t
t
SYNC Setup of MCLK
5
10
20
0
ns (min)
ns (min)
ns (min)
ns (max)
A
Correction Data Valid to CLK Setup
Correction Data Valid to CLK Hold
RD High to DD0–DD7 TRI-STATE
14
CDSETUP
CDHOLD
b
12
, t
D1H D0H
5
15
Access Time Delay from RD Low to
DD0–DD7 Data Valid
DACC
15
30
20
ns (max)
f
Maximum SCLK Frequency
SCLK Duty Cycle
MHz (min)
SCLK
40
60
% (min)
% (max)
t
t
t
t
t
t
SDI Set-Up Time from SCLK
Rising Edge
SDI
3
2
10
15
50
ns (min)
ns (min)
ns (max)
SDI Hold Time from SCLK
Rising Edge
HDI
Delay from SCLK Falling Edge to
SDO Data Valid
DDO
HDO
DELAY
SETUP
25
30
5
e
e
50 pF
SDO Hold Time from SCLK
Falling Edge
R
L
3k, C
50
5
ns (max)
ns (min)
L
DELAY from SCLK Falling Edge to
CS Rising or Falling Edge
10
10
ns (min)
ns (min)
Set-Up Time of CS Rising or Falling
Edge to SCLK Rising Edge
0
5
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AC Electrical Characteristics, MCLK Independent (Continued)
e
e
e
e
e
e
e
a
e
5.0V , REF IN
DC
The following specifications apply for AGND
DGND
e
DGND
(I/O)
0V, V
V
D
V
A
D(I/O)
e
5 ns, R 25X, C (databus loading)
s
a
limits apply for T
e
e
to T
e
1.225V , f
DC MCLK
20 MHz, t
e
1/f
, t
MCLK
t
f
50 pF/pin. Boldface
MCLK
r
L
e
e
e
T
J
T
T
; all other limits T
MAX
25 C. (Notes 7 and 8)
§
A
J
MIN
A
Typical
(Note 9)
Limits
Units
Symbol
Parameter
Conditions
(Note 10)
(Limits)
e
e
e
e
e
e
t
t
t
, t
S1H S0H
Delay from CS Rising Edge to SDO
TRI-STATE
R
L
R
L
R
L
3k, C
3k, C
3k, C
50 pF
L
L
L
25
50
ns (max)
SDO Rise Time, TRI-STATE to High
SDO Rise Time, Low to High
50 pF
50 pF
20
20
ns
ns
RDO
FDO
SDO Fall Time, TRI-STATE to Low
SDO Fall Time, High to Low
20
20
ns
ns
AC Electrical Characteristics, MCLK Dependent
e
e
e
e
e
e
e
V
D(I/O)
a
e
5.0V , REF IN
DC
The following specifications apply for AGND
a
DGND
e
DGND
(I/O)
5 ns, R
0V, V
V
D
A
e
e
e
e
1.225V , f
DC MCLK
20 MHz, t
MCLK
1/f
, t
t
f
25X, C (databus loading) 50 pF/pin. Refer to Table
MCLK
r
s
L
e
e
T
2, Configuration Register Parameters, for limits labelled C.R. Boldface limits apply for T
e
25 C. (Notes 7 and 8)
T
to
MIN
A
J
e
T
; all other limits T
MAX
T
J
§
A
Typical
(Note 9)
Limits
Units
(Limits)
Symbol
Parameter
Conditions
(Note 10)
t
t
MCLK to first w1 High
w1, w2 Clock Period
50 ns
1
t
START
MCLK
Standard CCD Mode
Even/Odd CCD Mode
400 ns
800 ns
8
t
t
w
MCLK
16
MCLK
t
t
t
t
Transfer Pulse (TR) Width
w1 to TR, TR to w1 Guardband
Reset Pulse (RS) Width
C.R.
C.R.
C.R.
ms
ns
ns
TRWIDTH
GUARD
RSWIDTH
RS
Falling Edge of w1 to RS
Either Edge of w1 to RS
Standard CCD Mode
Even/Odd CCD Mode
C.R.
C.R.
C.R.
1
ns
ns
ns
t
t
t
Falling Edge of w1 to Ref. Sample
Either Edge of w1 to Ref. Sample
Standard CCD Mode
Even/Odd CCD Mode
S/HREF
S/HSIG
Falling Edge of w1 to Sig. Sample
Either Edge of w1 to Sig. Sample
Standard CCD Mode
Even/Odd CCD Mode
Sample Pulse Width
(Acquisition Time)
S/HWIDTH
50 ns
t
MCLK
t
t
t
t
t
SYNC Low Between Lines
SYNC Setup of w1 to End Line
CCLK Pulse Width
100 ns
2
2
t
(min)
SYNCLOW
MCLK
t
(max)
B
MCLK
250 ns
250 ns
5
t
CCLKWIDTH
DATAVALID
EOCWIDTH
MCLK
Data Valid Time from EOC Low
EOC Pulse Width
300
5
ns (min)
t
MCLK
w1 and w2 Frequency
Standard CCD Mode
Even/Odd CCD Mode
2.5 MHz
f
/8
Hz
Hz
MCLK
1.25 MHz
f
/16
MCLK
w1 and w2 Duty Cycle
50
%
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6
Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed lest
conditions.
e
e
e
e
0V, unless otherwise specified.
Note 2: All voltages are measured with respect to GND
AGND
DGND
DGND
(I/O)
k
l
V
Note 3: When the input voltage (V ) at any pin exceeds the power supplies (V
IN
GND or V
or V ), the current at that pin should be limited to 25 mA. The
D
IN
IN
A
50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to
two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
, i and the ambient temperature, T . The maximum
Jmax JA
A
e
e
board mounted is 52 C/W for the V52A PLCC package, and 70 C/W for the VEG52A TQFP package.
allowable power dissipation at any temperature is P
(T
–T )/i . T
JA Jmax
150 C for this device. The typical thermal resistance (i ) of this part when
§
D
Jmax
A
JA
§
§
Note 5: Human body model, 100 pF capacitor discharged through a 1.5 kX resistor.
Note 6: See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in any National Semiconductor
Linear Data Book for other methods of soldering surface mount devices.
Note 7: A Zener diode clamps the OS analog input to AGND as shown below. This input protection, in combination with the external clamp capacitor and the output
impedance of the CCD, prevents damage to the LM9801 from transients during power-up.
TL/H/12814–4
Note 8: To guarantee accuracy, it is required that V and V be connected together to the same power supply with separate bypass capacitors at each supply pin.
D
A
e
e
e
20 MHz, and represent most likely parametric norm.
MCLK
Note 9: Typicals are at T
T
A
25 C, f
§
J
Note 10: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 11: For CCDs, V is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. V
is defined as the peak CCD
BLACK
pixel output voltage for a white (full scale) image with respect to the reference level, V
WHITE
is defined as the peak positive deviation above V of the
BLACK
- V
BLACK
RFT
reset feedthrough pulse. For CIS, V
correctable range of pixel-to-pixel V
is defined as the peak CCD pixel output voltage for a white (full scale) image with respect to GND (0V). The maximum
WHITE
variation is defined as the maximum variation in V
(due to PRNU, light source intensity variation, optics, etc.) that
WHITE
the LM9801 can correct for using its internal PGA.
WHITE
CCD Output Signal
CIS Output Signal
TL/H/12814–6
TL/H/12814–5
Note 12: Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of
the ADC.
Note 13: Reference voltages below 1.19V may decrease SNR. Reference voltages above 1.26V may cause clipping errors inside the LM9801. The
LM4041EIM3-1.2 (SOT-23 package) or the LM4041EIZ-1.2 (TO-92 package) bandgap voltage references are recommended for this application.
Note 14: PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula
V
PGA code
256
256
255
e
a
e
b
(PGA RANGE 1)
e
and PGA RANGE the PGA adjustment range (in V/V) of the LM9801 under test.
Gain
1
C
where C
PGA
V
# J
Note 15: VGA Gain Error is the maximum difference between the measured gain for any VGA code and the ideal gain calculated by using the formula
VGA code
16
16
(VGA RANGE) and VGA RANGE
15
e
e
e
the VGA adjustment range (in dB) of the LM9801 under test.
Gain
VGA
(dB)
C
where C
Typical Performance Characteristics
w1, w2, RS, and TR Rise and Fall
Times Through a Series Resistance
vs Load Capacitance
TL/H/12814–8
7
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Pin Descriptions
CCD Driver Signals
Digital Coefficient I/O
w1
w2
RS
TR
Digital Output. CCD clock signal, phase 1.
Digital Output. CCD clock signal, phase 2.
Digital Output. Reset pulse for the CCD.
Digital Output. Transfer pulse for the CCD.
Analog I/O
CD0 (LSB)– Digital Inputs. Correction Coefficient
Databus. This is the 8-bit data path for the
gain adjust PGA, used during line scan.
CD7 (MSB)
CCLK
Digital Output. This is the signal that is used
to clock the Gain coefficients into the
LM9801. Data is latched on the rising edge
of CCLK.
OS
Analog Input. This is the OS (Output
Signal) from the CCD. The maximum peak
signal that can be accurately digitized is
equal to the voltage at REF IN, typically
1.225V.
Digital Output I/O
DD0 (LSB)– Digital Outputs. Pixel Output Databus. This
data bus outputs the 8-bit digital output data
during line scan.
DD7 (MSB)
REF IN
REF OUT
REF OUT
Analog Inputs. These two pins are the
system reference voltage inputs and
should be tied together to a 1.225V voltage
source and bypassed to AGND with a 0.1
mF monolithic capacitor.
EOC
Digital Output. This is the End of Conversion
signal from the ADC indicating that new
pixel data is available.
RD
Digital Input. Taking this input low places
the data stored in the output latch on the
bus. When this input is high the DD0–DD7
bus is in TRI-STATE.
Analog Output. This reference voltage is
developed internally by the LM9801, and is
equal to 3 times REF IN. It should be
bypassed to AGND with a 0.1 mF
monolithic capacitor.
HI
Analog Power
V
A
This is the positive supply pin for the analog
supply. It should be connected to a voltage
Analog Output. This reference voltage is
developed internally by the LM9801, and is
equal to 2 times REF IN. It should be
bypassed to AGND using a 0.1 mF
monolithic capacitor.
MID
a
source of 5V and bypassed to AGND with
a 0.1 mF monolithic capacitor in parallel with
a 10 mF tantalum capacitor.
AGND
This is the ground return for the analog
supply.
V
V
,
Analog Inputs/Outputs. These pins are
used for testing the device during
manufacture and should be left
unconnected.
TEST1
Digital Power
TEST2
V
D
This is the positive supply pin for the digital
supply. It should be connected to a voltage
a
General Digital I/O
source of 5V and bypassed to DGND with
a 0.1 mF monolithic capacitor.
MCLK
SYNC
Digital Input. This is the 20 MHz (typical)
master system clock.
DGND
This is the ground return for the digital
supply.
Digital Input. A low-to-high transition on this
input begins a line scan operation. The line
scan operation terminates when this input
is taken low.
V
D(I/O)
This is the positive supply pin for the digital
supply for the LM9801’s I/O. It should be
a
with a
connected to a voltage source of 3V to
a
5V and bypassed to DGND
(I/O)
Configuration Register I/O
0.1 mF monolithic capacitor. If the supply for
this pin is different than the supply for V
SDI
Digital Input. Serial Data Input pin.
Digital Output. Serial Data Output pin.
A
and V , it should also be bypassed with a
D
10 mF tantalum capacitor.
SDO
SCLK
Digital Input. This is the serial data clock,
used to clock data in through SDI and out
through SDO. SCLK is asynchronous to
MCLK. Input data is latched and output
data is changed on the rising edge of
SCLK.
DGND
NC
This is the ground return for the digital
supply for the LM9801’s I/O.
(I/O)
NC
All pins marked NC (no connect) should be
left floating. Do not tie NC pins to ground.,
power supplies, or any other potential or
signal.
CS
Digital Input. This is the Chip Select signal
for writing to the Configuration Register
through the serial interface. This input must
be low in order to communicate with the
Configuration Register. This pin is used for
serial I/O only–it has no effect on any
other section of the chip.
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8
Timing Diagrams
TL/H/12814–9
DIAGRAM 1. Line Scan Timing Overview
TL/H/12814–10
DIAGRAM 2. Pixel Pipeline Timing Overview
9
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Timing Diagrams (Continued)
TL/H/12814–11
DIAGRAM 3. Timing for Start of Line Scan
TL/H/12814–12
DIAGRAM 4. Timing for End of Line/Start of Next Line
TL/H/12814–13
DIAGRAM 5. TR Pulse Timing
TL/H/12814–14
DIAGRAM 6. RS Pulse Polarity
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10
Timing Diagrams (Continued)
TL/H/12814–15
Note: Clamp signal only active during optical black pixels at beginning of line.
DIAGRAM 7. CCD Timing
TL/H/12814–16
Note: Clamp signal only active during optical black pixels at beginning of line.
DIAGRAM 8. CCD Timing (Even/Odd CCDs)
11
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Timing Diagrams (Continued)
TL/H/12814–17
e
e
e
e
i 16
Note: i
value programmed in Dummy Pixel Register - 1 (for example: Dummy Pixel Register
value programmed in Optical Black Register.
17
x
x
16 dummy pixels).
j
DIAGRAM 9. Dummy Pixel and Optical Black Pixel Timing
TL/H/12814–18
DIAGRAM 10. Coefficient Data Timing
TL/H/12814–19
DIAGRAM 11. Output Data Timing
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12
Timing Diagrams (Continued)
TL/H/12814–20
DIAGRAM 12. Data Timing (Output and Coefficient Data Sharing Same Bus)
Serial Configuration Register Timing Diagrams
TL/H/12814–21
DIAGRAM 13a. Configuration Register Write Timing using CS, Continuous SCLK (16-Bit Word)
TL/H/12814–22
DIAGRAM 13b. Configuration Register Read Timing using CS, Continuous SCLK (16-Bit Word)
13
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Serial Configuration Register Timing Diagrams (Continued)
TL/H/12814–23
TL/H/12814–24
TL/H/12814–25
DIAGRAM 14. SDO Timing
DIAGRAM 15a. Configuration Register Write Timing with CS Continuously Low (16-Bit Word)
DIAGRAM 15b. Configuration Register Write Timing with CS Continuously Low (Two 8-Bit Bytes)
TL/H/12814–26
DIAGRAM 15c. Configuration Register Read Timing with CS Continuously Low (16-Bit Word)
TL/H/12814–27
DIAGRAM 15d. Configuration Register Read Timing with CS Continuously Low (Two 8-Bit Bytes)
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14
TABLE I. Configuration Register Address Table
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Standard
Mode or
Even/Odd
Mode
RS
RS
Pulse
Width
Pulse
Polarity
RS Pulse Position
0
0
0
MODE
RSW1
RSW0
RSPOL
RSPOS3
SS3
RSPOS2
RSPOS1
RSPOS0
SS0
Sample Reference Position
Sample Signal Position
(Maximum Register Value is 14)
0
0
0
1
1
0
SR3
SR2
SR1
SR0
SS2
SS1
w1
w2
RS
TR
TR–w1
TR
TR Pulse Width
Enable
Enable
Enable
Enable
Guardband
Polarity
w1EN
w2EN
RSEN
TREN
TRW1
TRW0
TRGRD
TRPOL
Signal
Dummy Pixels (Minimum Register Value is 2)
BLS4 BLS3 BLS2
Polarity
0
1
1
SIGPOL
BLL7
BLS6
BLL6
BLS5
BLS1
BLL1
BLS0
BLL0
Optical Black Pixels (Minimum Register Value is 1)
1
1
0
0
0
1
BLL5
BLL4
BLL3
BLL2
PGA Gain Coefficient
GAIN7
GAIN6
GAIN5
GAIN4
GAIN3
GAIN2
GAIN1
GAIN0
PGA Gain
Source
Offset DAC
Sign
Power-
down
Offset
Add
VGA Gain
MSB
VGA
Gain
VGA
Gain
VGA Gain
LSB
1
1
1
1
0
1
PGASRC
ODSIGN
PD
OFFADD
VGA3
VGA2
VGA1
VGA0
Offset DAC
MSB
Offset DAC
Offset DAC
Offset DAC
LSB
Test Modes
VOS3
VOS2
VOS1
VOS0
0
0
0
0
TABLE II. Configuration Register Parameters
Control Bits
Parameter
Result
MODE
MODE
e
e
0
1
Standard CCD (w frequency
Even/Odd CCD (w frequency
f
/8)
MCLK
f
/16)
MCLK
RS1
RS0
0
0
1
1
0
1
0
1
1 t (50 ns)
MCLK
RS Pulse Width
2 t
(100 ns)
(150 ns)
(200 ns)
MCLK
MCLK
MCLK
(t
)
RSWIDTH
3 t
4 t
RSPOL
RS Pulse Polarity
0
1
RS
RS
e
e
e
e
50 ns).
MCLK
Note: t
1/f
1 MCLK period. Examples given in parenthesis are for f
20 MHz (t
MCLK
MCLK
MCLK
15
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TABLE II. Configuration Register Parameters (Continued)
Parameter
Control Bits
Result
RSPOS3
RSPOS2
RSPOS1
RSPOS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.0t
0.5t
1.0t
1.5t
2.0t
2.5t
3.0t
3.5t
4.0t
4.5t
5.0t
5.5t
6.0t
6.5t
7.0t
7.5t
(0 ns)
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
(25 ns)
(50 ns)
(75 ns)
(100 ns)
(125 ns)
(150 ns)
(175 ns)
(200 ns)
(225 ns)
(250 ns)
(275 ns)
(300 ns)
(325 ns)
(350 ns)
(375 ns)
RS Pulse Position
(t
RS
)
SR3
SR2
SR1
SR0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.0t
0.5t
1.0t
1.5t
2.0t
2.5t
3.0t
3.5t
4.0t
4.5t
5.0t
5.5t
6.0t
6.5t
7.0t
(0 ns)
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
(25 ns)
(50 ns)
(75 ns)
(100 ns)
(125 ns)
(150 ns)
(175 ns)
(200 ns)
(225 ns)
(250 ns)
(275 ns)
(300 ns)
(325 ns)
(350 ns)
Sample Reference
Position (t
)
S/HREF
Not Valid
SS3
SS2
SS1
SS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.0t
0.5t
1.0t
1.5t
2.0t
2.5t
3.0t
3.5t
4.0t
4.5t
5.0t
5.5t
6.0t
6.5t
7.0t
7.5t
(0 ns)
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
(25 ns)
(50 ns)
(75 ns)
(100 ns)
(125 ns)
(150 ns)
(175 ns)
(200 ns)
(225 ns)
(250 ns)
(275 ns)
(300 ns)
(325 ns)
(350 ns)
(375 ns)
Sample Signal
Position (t
)
S/HSIG
e
e
e
e
50 ns).
MCLK
Note: t
1/f
1 MCLK period. Examples given in parenthesis are for f
20 MHz (t
MCLK
MCLK
MCLK
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16
TABLE II. Configuration Register Parameters (Continued)
Parameter
Control Bits
Result
w1EN
w1 Enable
0
1
w1 Output Off
w1 Output On
w2EN
w2 Enable
RS Enable
TR Enable
0
1
w2 Output Off
w2 Output On
RSEN
0
1
RS Output Off
RS Output On
TREN
0
1
TR Output Off
TR Output On
TRW1
TRW0
0
0
1
1
0
1
0
1
20 t
30 t
40 t
50 t
(1.0 ms)
(1.5 ms)
(2.0 ms)
(2.5 ms)
MCLK
MCLK
MCLK
MCLK
TR Pulse Width
(t
)
TRWIDTH
TR-w1
Guardband
(t
TRGRD
0
1
1 t
(50 ns)
MCLK
)
GUARD
2 t
MCLK
(100 ns)
TRPOL
TR Polarity
0
1
TR
TR
SIGPOL
Signal Polarity
0
1
Positive (CIS)
Negative (CCD)
BLS6
BLS5
BLS4
BLS3
BLS2
BLS1
BLS0
Dummy Pixels
Dummy Pixels
0
0
0
0
#
1
1
1
0
0
0
0
#
1
1
1
0
0
0
0
#
1
1
1
0
0
0
0
#
1
1
1
0
0
0
0
#
1
1
1
0
0
1
1
#
0
1
1
0
1
0
1
#
1
0
1
Not Valid
Note: Minimum
Register Value is 2.
Actual number of
dummy pixels in CCD
should be one less
than number in this
register.
Not Valid
1
2
#
124
125
126
BLL7
BLL6
BLL5
BLL4
BLL3
BLL2
BLL1
BLL0
Optical Black Pixels
0
0
0
0
#
1
1
1
0
0
0
0
#
1
1
1
0
0
0
0
#
1
1
1
0
0
0
0
#
1
1
1
0
0
0
0
#
1
1
1
0
0
0
0
#
1
1
1
0
0
1
1
#
0
1
1
0
1
0
1
#
1
0
1
Not Valid
1
2
Optical Black Pixels
Note: Minimum
3
Register Value is 1.
#
253
254
255
e
e
e
e
50 ns).
MCLK
Note: t
1/f
1 MCLK period. Examples given in parenthesis are for f
20 MHz (t
MCLK
MCLK
MCLK
17
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TABLE II. Configuration Register Parameters (Continued)
Parameter
Control Bits
Result
[
dB V/V
(typical)
]
GAIN7
GAIN6
GAIN5
GAIN4
GAIN3
GAIN2
GAIN1
GAIN0
0
0
0
#
1
1
1
0
0
0
#
1
1
1
0
0
0
#
1
1
1
0
0
0
#
1
1
1
0
0
0
#
1
1
1
0
0
0
#
1
1
1
0
0
1
#
0
1
1
0
1
0
#
1
0
1
0.00 1.000
0.07 1.008
0.13 1.015
#
9.35 2.935
9.37 2.942
9.40 2.950
Internal PGA
Gain Coefficient
PGA Gain
Coefficient
Source
PGASRC
0
1
Internal
External
Offset DAC
Sign
ODSIGN
0
1
Negative
Positive
PD
Power Down
Offset Add
0
1
Operating
Powered Down
OFF ADD
E
0
1
Offset 0 LSB
Ea
Offset
2 LSB
[
dB V/V
(typical)
]
VGA3
VGA2
VGA1
VGA0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.00 1.00
0.60 1.07
1.20 1.15
1.79 1.23
2.39 1.32
2.99 1.41
3.59 1.51
4.19 1.62
4.79 1.74
5.38 1.86
5.98 1.99
6.58 2.13
7.18 2.29
7.78 2.45
8.38 2.62
8.97 2.81
VGA Gain
e
e
e
e
50 ns).
MCLK
Note: t
1/f
1 MCLK period. Examples given in parenthesis are for f
20 MHz (t
MCLK
MCLK
MCLK
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18
TABLE II. Configuration Register Parameters (Continued)
Parameter
Control Bits
Result
Offset (LSB)
(typical)
ODSIGN
VOS3
VOS2
VOS1
VOS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.00
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
0.42
0.84
1.26
1.68
2.10
2.52
2.94
3.36
3.78
4.20
4.62
5.04
5.46
5.88
6.30
Offset DAC
0.00
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
0.42
0.84
1.26
1.68
2.10
2.52
2.94
3.36
3.78
4.20
4.62
5.04
5.46
5.88
6.30
e
e
e
e
50 ns).
MCLK
Note: t
1/f
1 MCLK period. Examples given in parenthesis are for f
20 MHz (t
MCLK
MCLK
MCLK
Block Diagram of LM9801-Based System
TL/H/12814–28
Note: Power supplies and bypass capacitors not shown for clarity.
FIGURE 1. LM9801 System Block Diagram
19
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Applications Information
1.0 THEORY OF OPERATION
An approximately 2 LSB (29 mV) offset can be added at the
output of the PGA stage if necessary to ensure that the
offset is greater than zero. This eliminates the possibility of
a negative offset clipping the darkest output pixels. For
more information on the Offset Add Bit, see Section 4.8.
The LM9801 removes errors from and digitizes a linear CCD
pixel stream, while providing all the necessary clock signals
to drive the CCD. Offset and gain errors for individual pixels
are removed at the pixel rate. Offset errors are removed
through correlated double sampling (CDS). Gain errors
(which may come from any combination of PRNU, uneven
Finally, the output of the PGA is digitized by the ADC and
made available on the DD0–DD7 bus (Section 4.9).
4
illumination, cos effect, RGB filter mismatch, etc.) are re-
Three reference voltages are used throughout the signal
path: the externally supplied REF IN (1.225V), and the inter-
moved through the use of a 8-bit programmable gain ampli-
fier (PGA) in front of the ADC.
nally generated REF OUT
(3.675V).
(2.45V) and REF OUT
HI
MID
1.1 The Analog Signal Path
(See Block Diagram)
1.2 The CCD Clocking Signals
To maximize the flexibility of the LM9801, the CCD’s w1,
w2, RS, and TR pulses are internally generated, with a wide
range of options, making these signals compatible with
most commercial linear CCDs. In many cases, these output
signals can drive the CCD clock inputs directly, with only
series resistors (for slew rate control) between the
LM9801’s outputs and the CCD clock inputs.
The analog output signal from the CCD is connected to the
OS input of the LM9801 through a 0.01 mF (typical, see
Section 4.2, Clamp Capacitor Selection) DC blocking capac-
itor. During the CCD’s optical black pixel segment at the
beginning of every line, this input is clamped to the REF
OUT
voltage (approximately 2.45V). This DC restore op-
MID
eration fixes the reference level of the CCD pixel stream at
REF OUT
.
MID
1.3 The Digital Interface
The signal is then buffered and fed to
a
digitally-pro-
There are three main sections to the digital interface of the
LM9801: a serial interface to the Configuration Register,
where all device programming is done, an 8 bit-wide input
databus for gain correction coefficients with a synchronous
clock output (CCLK), and an 8-bit output databus for the
final pixel output data with a synchronous end of conversion
output signal (EOC) and an output enable input (RD). Please
note that the CS input affects only the serial I/O–it has no
effect on the output databus, input coefficient bus, or any
other section of the LM9801.
grammed 4-bit VGA (variable gain amplifier). The gain of the
VGA is digitally programmable in 16 steps from 1V/V to
3V/V. The VGA is used to compensate for peak white CCD
outputs less than the 1.225V full-scale required by the
LM9801 for maximum dynamic range. When used with par-
allel output CCDs, the VGA can fine-tune the amplitude of
the red, green, and blue signals. For a detailed explanation
of the VGA, see Section 4.3.
The output of the VGA goes into the CDS (Correlated Dou-
ble Sampling) stage, consisting of two sample/hold amplifi-
ers: S/H Ref (Reference) and S/H Signal. The reference
level of the signal is sampled and held by the S/H Ref cir-
cuit and the active pixel data is sampled and held by the S/
H Signal circuit. The output of S/H Ref is subtracted from
the S/H Signal output and amplified by 2. The full-scale
signal range at this point is approximately 2.45Vp-p. CDS
reduces or eliminates many sources of noise, including re-
set noise, flicker noise, and both high and low frequency
pixel-to-pixel offset variation. For more information on the
CDS stage, see Section 4.4.
2.0 DIGITAL INTERFACE
2.1 Reading and Writing to the Configuration Register
Communication with the Configuration Register is done
through a standard MICROWIRETM serial interface. This in-
terface is also compatible with the Motorola SPITM standard
and is simple enough to easily be implemented in custom
hardware if desired.
The serial interface timing is shown in Diagrams 13a–13b
and Diagrams 15a–15d. Data is sent serially, LSB first.
(Please note that some microcontrollers output data MSB
first. When using these microcontrollers the bits in the con-
figuration register are effectively reversed.) Input data is
latched on the rising edge of SCLK, and output data chang-
es on the falling edge of SCLK. CS must be low to enable
serial I/O.
At this point an offset voltage can be injected by the 5-bit (4
a
bits
sign) Offset DAC. This voltage is designed to com-
pensate for any small fixed DC offset introduced by the CDS
S/Hs and the x2 amplifier. The LSB size of the DAC is ap-
proximately 0.42 ADC LSBs (4 mV). The adjustment range
g
is 6.3 ADC LSBs. For a detailed explanation of the Offset
DAC, see Section 4.6.
If SCLK is only clocked when sending or receiving data from
the LM9801, and held low at all other times, then CS can be
tied low permanently as shown in Diagrams 15a–15d. If
SCLK is continuous, then CS must be used to determine the
beginning and the end of a serial byte or word (see Dia-
grams 13a–13b). Note that CS must make its high-to-low
and low-to-high transitions when SCLK is low, otherwise the
internal bit counter may receive an erroneous pulse, causing
an error in the write or read operation.
The next stage is the PGA. This is a programmable gain
amplifier that changes the gain at the pixel rate to correct
for gain errors due to PRNU, uneven illumination (such as
4
cos effect), RGB filter mismatch, etc. The gain adjustment
range is 0 dB to 9 dB (1V/V to 3V/V) with 8 bits of resolu-
tion. The gain data (correction coefficients) is provided on
the CD0–CD7 bus. The gain may also be fixed at any value
between 0 dB and 9 dB with the PGA Gain Coefficient
configuration register. For additional information on the
PGA, see Section 4.7.
Data may be transmitted and received in two 8-bit bytes
(typical with microcontroller interfaces) or one 16-bit word
(for custom serial controllers).
http://www.national.com
20
Applications Information (Continued)
The Configuration Register is programmed by sending a
control byte to the serial port. This byte indicates whether
this is a read or a write operation, and gives the 3-bit ad-
dress of the register bank to be read from or written to. If
this is a read operation, the next 8 SCLKs will output the
data at the requested location on the SDO pin. If this is a
write operation, the data to be sent to the specified location
should be clocked in on the SDI input during the next 8
SCLKs. Data is sent and received using the LSB (Least Sig-
nificant Bit) first format.
control slew rate and isolate the driver from the large load
capacitances. The values of these resistors are usually giv-
en in the CCD’s datasheet.
4.0 ANALOG INTERFACE
4.1 Voltage Reference
The two REF IN pins should be connected to
g
a
1.225V 2% reference voltage capable of sinking between
2 mA and 5 mA of current coming from the 500X–1400X
resistor string between REF OUT
HI
and REF IN. The
For maximum system reliability, each configuration register
location can be read back and verified after a write.
LM4041-1.2 1.225V bandgap reference is recommended for
this application as shown in Figure 2. The inexpensive ‘‘E’’
grade meets all the requirements of the application and is
available in a TO-92 (LM4041EIZ-1.2) package as well as a
SOT-23 package (LM4041EIM3-1.2) to minimize board
space.
If the serial I/O to the configuration register falls out of sync
for any reason, it can be reset by sending 8 or more SCLKs
with CS held high.
2.2 Writing Correction Coefficient Data on the
CD0–CD7 Bus
Due to the transient currents generated by the LM9801’s
ADC, PGA, and CDS circuitry, the REF IN pins, the REF
Correction coefficient data for each pixel is latched on the
rising edge of the CCLK output signal (see Diagram 10).
Note that there is a 3 pixel latency between when the coeffi-
cient data is latched and when the output data is available.
As Diagram 2, Pixel Pipeline Timing Overview shows, coeffi-
cient data for pixel n is latched shortly before the output
data for pixel n-2 becomes available on the output databus
(DD0–DD7). Note that there is no way to provide a correc-
tion coefficient for pixel 1, the first pixel in the CCD array.
This is not a problem since the first several pixels of the
CCD are used for clamping.
OUT
MID
pin and the REF OUT pin should all be bypassed
HI
to AGND with 0.1 mF monolithic capacitors.
2.3 Reading Output Data on the DD0–DD7 Bus
The corrected digital output data representing each pixel is
available on the DD0–DD7 databus. The data is valid after
the falling edge of the EOC output. The RD input takes the
databus in and out of TRI-STATE. RD can be held low at all
times if there are no other devices needing the bus, or it can
be used to TRI-STATE the bus between pixels, allowing oth-
er devices access to the bus. Diagram 12, Data Timing (Out-
put and Coefficient Data Sharing Same Bus), shows how
EOC can be tied to RD to automatically multiplex between
coefficient data and conversion data.
TL/H/12814-29
FIGURE 2. Voltage Reference Generation
4.2 Clamp Capacitor Selection
This section is very long because it is relatively complicated
to explain, but the answer is short and simple: A clamp ca-
pacitor value of 0.01 mF should work in almost all applica-
tions. The rest of this section describes exactly how this
value is selected.
2.4 MCLK
This is the master clock input that controls the LM9801. The
pixel conversion rate is fixed at 1/8 of this frequency. Many
of the timing parameters are also relative to the frequency
of this clock.
2.5 SYNC
This input signals the beginning of a line. When SYNC goes
high, the LM9801 generates a TR pulse, then begins con-
verting pixels until the SYNC line is brought low again. Since
there is no pixel counter in the LM9801, it will work with
CCDs of any length.
3.0 DIGITAL CCD INTERFACE
TL/H/12814–30
FIGURE 3. OS Clamp Capacitor and Internal Clamp
3.1 Buffering w1, w2, RS, and TR
The output signal of many CCDs rides on a large DC offset
(typically 8V to 10V) which is incompatible with the
LM9801’s 5V operation. To eliminate this offset without re-
sorting to additional higher voltage components, the output
The LM9801 can drive the w1, w2, RS, and TR inputs of
many CCDs directly, without the need for external buffers
between the LM9801 and the CCD. Most linear CCDs de-
signed for scanner applications require 0V to 5V signal
swings into 20 pF to 500 pF input loading. Series resistors
are typically inserted between the driver and the CCD to
21
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Applications Information (Continued)
of the CCD is AC coupled to the LM9801 through a DC
e
amount of time (per pixel) that the clamp is on, R
Where n
the number of optical black pixels, t
is the
is the
DARK
OUT
blocking capacitor, C
CLAMP
(the CCD’s DOS output is not
used). The value of this capacitor is determined by the leak-
age current of the LM9801’s OS input and the output imped-
ance of the CCD. The leakage through the OS input deter-
mines how quickly the capacitor value will drift from the
output impedance of the CCD, and accuracy is the ratio of
the worst-case initial capacitor voltage to the desired final
capacitor voltage. For example, if a CCD has 18 black refer-
ence pixels, the output impedance of the CCD is 1500X, the
LM9801 is configured to clamp for 300 ns, the worst case
initial voltage across the capacitor is 10V, and the desired
clamp value of REF OUT
, which then determines how
many pixels can be processed before the droop causes er-
MID
e
e
100),
g
rors in the conversion ( 0.1V is the recommended limit).
voltage after clamping is 0.1V (accuracy
then:
10/0.1
The output impedance of the CCD determines how quickly
the capacitor can be charged to the clamp value during the
black reference period at the beginning of every line.
18 300 ns
1500X In(100)
514 pF
e
e
C
CLAMP MAX
The minimum clamp capacitor value is determined by the
maximum droop the LM9801 can tolerate while converting
one CCD line. The following equation takes the maximum
leakage current into the OS input, the maximum allowable
droop (100 mV), the number of pixels on the CCD, and the
The final value for C
CLAMP
C
should be less than or equal to
. A value of
, but no less than C
CLAMP MAX CLAMP MIN
470 pF will work in this example.
In some cases, depending primarily on the choice of CCD,
pixel conversion rate (f
clamp capacitor value:
/8) and provides the minimum
MCLK
C
C
may actually be less than the
, meaning that the capacitor cannot be charged
CLAMP
MAX
CLAMP MIN
i
e
e
C
dt
to its final voltage during the black pixels at the beginning of
a line and hold its voltage without drooping for the duration
of that line. This is usually not a problem because in most
applications the CCD is clocked continuously as soon as
power is applied. In this case, a larger capacitor can be
CLAMP MIN
dV
leakage current (A) number of pixels
max droop (V) conversion rate (Hz)
For example, if the OS input leakage current is 20 nA worst-
case, the CCD has 2700 active pixels, the conversion rate is
used (guaranteeing that the C
CLAMP MIN
requirement is
met), and the final clamp voltage is forced across the ca-
pacitor over multiple lines. This equation calculates how
many lines are required before the capacitor settles to the
desired accuracy:
e
0.1V, the minimum clamp capacitor value is:
2.5 MHz (f
MCLK
20 MHz), and the max droop desired is
20 nA 2700
e
C
CLAMP MIN
0.1V 2.5 MHz
216 pF
R
C
OUT CLAMP
Initial Voltage
Final Voltage
e
e
lines
In
n
t
DARK
#
J #
J
The maximum size of the clamp capacitor is determined by
the amount of time available to charge it to the desired val-
ue during the optical black portion of the CCD output. The
internal clamp is on for each pixel from the rising edge of
the S/H ref pulse to the falling edge of the S/H signal pulse
(see Diagrams 7 and 8). This time can be calculated using
the values stored in the Sample Signal and Sample Refer-
ence configuration registers and the MCLK frequency. For
normal CCDs:
Using the values shown before and a clamp capacitor value
of 0.01 mF, this works out to be:
1500X 0.01 mF
10V
e
e
lines
In
12.8 lines
18 300 ns
0.1V
#
J # J
At a 2.5 MHz conversion rate, this is about 14 ms.
In this example a 0.01 mF capacitor takes 14 ms after pow-
er-up to charge to its final value, but its droop across all
subsequent lines is now less than 2 mV (using the previous
a
2
SS–SR
example’s values). This wide margin is the reason a C
value of 0.01 mF will work in most applications.
CLAMP
e
t (s)
DARK
2f
MCLK
(Hz)
And for even/odd CCDs:
4.3 VGA
a
18
2f
SS–SR
(Hz)
The LM9801 has a VGA (Variable Gain Amplifier) that can
be used to increase the amplitude of the CCD signal prior to
sampling, correction, and digitization. The gain of the VGA is
0 dB to 9 dB and is determined by the codes in the 4-bit
VGA Gain register, as given by the equation:
e
t
(s)
DARK
MCLK
Where SS is the value in the Sample Signal Position register
(0–15), SR is the value in the Sample Reference Position
register (0–14), f
is the MCLK frequency, and t
MCLK
the amount of time (per pixel) that the clamp is on.
is
DARK
VGA code
e
Gain
VGA
(dB)
9.55
The following equation takes the number of optical black
pixels, the amount of time (per pixel) that the clamp is
closed, the CCD’s output impedance, and the desired accu-
racy of the final clamp voltage and provides the maximum
clamp capacitor value that allows the clamp capacitor to
settle to the desired accuracy within a single line:
16
This gain may be changed at the line rate (not the pixel rate)
by writing to the configuration register. You can write to the
configuration register to change the gain at any time, but if
you write during a line, the remaining pixels of that line may
be corrupted. It is best to change the gain after all active
pixels have been read out or while SYNC is low.
t
1
e
e
C
CLAMP MAX
R In(accuracy)
n
t
(s)
DARK
R
(X) In(accuracy)
OUT
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22
Applications Information (Continued)
4.4 Correlated Double Sampler (CDS)
Figure 4 shows the output stage of a typical CCD and the
resulting output waveform:
TL/H/12814–32
FIGURE 5. CIS vs CCD Output Signals
While CIS devices do not usually have a reference level with
which to perform correlated double sampling, many have a
very repeatable reset level which can be used as a black
reference allowing the LM9801 to perform pseudo CDS on
the signal. When the Signal Polarity bit is set to a zero, the
LM9801 expects a positive going signal, typically from a CIS
device. When the Signal Polarity bit is set to a one, the
LM9801 expects a negative going signal, typically from a
CCD sensor.
TL/H/12814–31
4.6 Offset DAC
FIGURE 4. CDS
The 4 bit plus sign Offset DAC is used to compensate for
DC offsets due to the correlated double sampling stage.
The offset can be corrected in 31 steps of 0.42 ADC LSB
Capacitor C1 converts the electrons coming from the CCD’s
shift register to an analog voltage. The source follower out-
put stage (Q2) buffers this voltage before it leaves the CCD.
Q1 resets the voltage across capacitor C1 in between every
pixel at intervals 2 and 5. When Q1 is on, the output signal
(OS) is at its maximum. After Q1 turns off (period 3), the OS
level represents the residual voltage across C1
b
a
6.3 LSBs. Note that the DAC
size between 6.3 and
comes betore the PGA, so any offset errors at this stage are
multiplied by the gain of the PGA. The calibration procedure
described in Section 5.0 demonstrates how to use the DAC
to eliminate offset errors before scanning begins.
(V
). V includes charge injection from Q1,
RESIDUAL
RESIDUAL
Note that this DAC is programmed during LM9801 calibra-
tion/configuration and is not meant to compensate for pixel-
to-pixel CCD offset errors. CDS cancels the pixel-rate offset
errors.
thermal noise from the ON resistance of Q1, and other
sources of error. When the shift register clock (w1) makes a
low to high transition (period 4), the electrons from the next
pixel flow into C1. The charge across C1 now contains the
voltage proportional to the number of electrons plus
4.7 Programmable Gain Amplifier (PGA)
V
, an error term. If OS is sampled at the end of
RESIDUAL
The PGA provides 8 bits of pixel-to-pixel gain correction
over a 0 dB to 9 dB (x1 to x3) range. After the input signal is
sampled and held by the CDS stage, it is amplified by the
gain indicated by the data (‘‘PGA Code’’) on the CD0–CD7
databus using the formula:
period 3 and that voltage is subtracted from the OS at the
end of period 4, the V term is canceled and the
RESIDUAL
noise on the signal is reduced. ( V
a
[
]
V
SIGNAL
). This is the principal of Correlated
SIGNAL
RESIDUAL
b
e
V
V
RESIDUAL
Double Sampling.
V
PGA code
256
e
a
Gain
1
1.95
The LM9801 implements CDS with two switched-capacitor
S/H amplifiers. The S/Hs acquire a signal within a 50 ns
window which can be placed anywhere in the pixel period
with 25 ns precision. See Diagrams 7 and 8 for more de-
tailed timing information.
V
# J
4.8 Offset Add Bit
In addition to the Offset DAC, there is a bit in the configura-
tion register which, when set, adds a positive 2 LSB offset at
the output of the PGA. This offset ensures that any offset
between the output of the PGA and the ADC is positive, so
that no dark level information is lost due to negative offsets.
The calibration procedure described in Section 5.0 demon-
strates how to set this bit.
4.5 CIS Mode
The LM9801 provides some support for CIS (Contact Image
Sensor) devices by offering a sampling mode for capturing
positive going signals, as opposed to the CCD’s negative
going signal.
23
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Applications Information (Continued)
4.9 ADC
The ADC converts the normalized analog output signal to
an 8-bit digital code. The EOC output goes from high to low
to indicate that a new conversion is ready. ADC data can be
latched by external memory on the rising edge of EOC. The
RD input takes the ADC’s output buffer in and out of
TRI-STATE. RD may be tied to EOC in many applications,
putting the data on the bus only when EOC is low, and al-
lowing other data on the bus (such as CD0–CD7 correction
data) at other times. In this way the output data and correc-
tion coefficient data can share the same databus (see Dia-
gram 12).
TL/H/12814–33
FIGURE 6. Offset Calibration
ply by turning off the scanner’s illumination). If this voltage is
known with a PGA gain of 1.00V/V (0 dB) and 2.95V/V
(9 dB), then the offset errors (V and V ) can be deter-
OS1 OS2
mined from the following two equations:
5.0 CALIBRATION
Calibration of a CCD scanner is done to normalize the pixels
of a linear CCD so that each pixel produces the same digital
output code at the output of the scanner when presented
with the same image light intensity. This intensity ranges
from black (no light) to white (maximum light intensity). The
CCD’s analog output may have large pixel-to-pixel DC off-
sets (corresponding to errors on black signals) and pixel-to-
pixel variations in their output voltage given the same white
image (corresponding to errors on brighter signals). If these
offsets are subtracted from each pixel, and each pixel is
given its own gain setting to correct for different efficiencies,
then these errors can be eliminated.
e
e
a
a
a
V
1(V
OS1
V
)
V
V
DAC2
ADC1
ADC2
DAC1
OS2
e
a
e
(PGA gain
1)
V
a
a
V
2.95(V
OS1
)
V
V
DAC2
DAC1
OS2
(PGA gain
2.95)
Solving for V
and V
:
OS2
OS1
e
e
V
V
(V
–V
)/1.95–V
DAC1
OS1
ADC2
ADC1
(2.95V
–V
)/1.95–V
ADC2 DAC2
OS2
ADC1
These equations were used to produce this procedure for
cancelling the LM9801’s offset errors. Please note that all
voltages and measurements are in units of ADC LSBs to
simplify calibration.
Ideally the digital output code for any pixel would be zero for
a black image, and some code near fullscale for an image
with maximum brightness. For an 8-bit system like the
LM9801, that code might be 250. This code will be called
the Target Code.
e
1. Set the VGA Gain to 1V/V (VGA code
0 LSBs).
2. Set the Offset DAC (V
) to its maximum value
DAC1
6.3 LSBs) to ensure the total offset is positive and
a
therefore measurable by the ADC.
(
The LM9801 eliminates these global and pixel-to-pixel off-
set and gain errors with its Correlated Double Sampling
(CDS), Offset DACs, Variable Gain Amplifier, and pixel-rate
Programmable Gain Amplifier. This section describes how
to program the LM9801 and the coefficient RAM being used
with it to eliminate these errors.
3. Set the Offset Add bit (V ) to 0.
DAC2
e
4. Set the PGA Gain to 1V/V (PGA code
5. Digitize a black line.
0).
6. Calculate the average (in ADC LSBs) of all the valid
pixels in the black line and store that number as V
.
ADC1
Calibration of a LM9801-based system requires 3 steps.
The first, described in Section 5.1, Offset Calibration, takes
a black image and normalizes the digital output code for
each pixel to a code at or near 0.
e
7. Set the PGA Gain to 2.95V/V (PGA code
8. Digitize a black line.
255).
9. Calculate the average (in ADC LSBs) of all the valid
pixels in the black line and store that number as V
The second step, Section 5.2, Coarse Gain (VGA) Calibra-
tion, finds the optimum gain setting that places the output
voltage of all the pixels within the 9 dB adjustment range of
the PGA.
.
ADC2
10. Calculate V
:
OS1
e
V
(V
–V
ADC2
)/1.95–6.3
ADC1
OS1
11. Program the Offset DAC register using the formula:
The final step, described in Section 5.3, PGA Correction
Coefficients (Shading Calibration), describes how to calcu-
late the gain required to normalize the output of each pixel
to the desired output code (the Target code).
e
–V
Offset DAC code
-(V
)(15/6.3)
OS1
e
e
a
(V
(6.3
)/1.95)(15/6.3)
ADC2
ADC1
a
15
1.22(V
–V )
ADC2
ADC1
(Note: This calculation can be done as
5.1 Offset Calibration
a
15
39(V
–V
)/32
This procedure corrects for static offsets generated by the
CCD and the LM9801. Because the LM9801 uses CDS to
eliminate the pixel-to-pixel offset errors of the CCD, no pix-
el-rate offset correction is required.
ADC1
ADC2
for ease of programming in 8-bit microcontrollers)
l
k
12. If 3V
If 3V
V
V
, then set the Offset Add bit to 0.
, set the Offset Add bit to 1.
ADC1
ADC1
ADC2
ADC2
To use the Offset DAC and Offset Add bit for offset correc-
) must first be deter-
OS2
13. The final value of the offset present at the ADC input
can be used for the shading calibration calculations.
Calculate the final value of the ADC input offset
tion, the offset errors (V
and V
OS1
mined, as shown in Figure 6. This is done be measuring the
voltage at the PGA output, using the ADC with a black im-
age on the CCD (a black image can usually be created sim-
(V
) using:
OFFSET
e
e
V
V
(3V
–V
)/2
(if the Offset Add bit is 0), or
OFFSET
ADC1
ADC2
a
2
(3V
–V
ADC2
)/2
OFFSET
ADC1
(if the Offset Add bit is 1)
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24
Applications Information (Continued)
5.2 Coarse Gain Calibration
The LM9801’s PGA corrects for up to 9 dB of varIation in
the CCD output signal’s white level intensity. That 9 dB
range has to be centered inside the 9 dB window of correc-
tion as shown in Figure 7. The window’s upper limit is deter-
mined by the Target code, and the lower limit by the Target
code divided by 2.8 (this corresponds to the minimum gain
range of the PGA). To allow proper calibration, the ampli-
tude of all the pixels in the CCD should be inside this range
when those pixels are scanning an image corresponding to
the Target code. The placement of the pixels inside the 9
dB window can be controlled by any of three ways: chang-
ing the gain of the VGA, changing the integration time of the
CCD, or changing the intensity of the light source.
TL/H/12814–34
FIGURE 7. CCD Input Signal In Range
Figure 8 is a flowchart of one technique to find the optimum
VGA gain setting during calibration. Calibration begins with
a VGA gain setting of 1V/V and increments the VGA gain
until one of the four possible results occur. Result 1 is the
desired outcome, where the signal falls into the range
shown in Figure 7 and the VGA calibration has been suc-
cessful.
In most designs, the output waveform of the CCD can be
brought into the 9 dB correction range of the PGA by adjust-
ing the gain of the VGA. This is the next step in system
calibration.
TL/H/12814–35
FIGURE 8. VGA Calibration Flowchart
25
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Applications Information (Continued)
There are several conditions that can cause the VGA gain
calibration routine to fail. Result 2, ‘‘Signal is too strong:
Decrease light intensity or integration time’’ is shown in Fig-
ure 9. This condition indicates that the amplitude of one or
more of the white pixels coming from the CCD is greater
than the maximum input voltage that the LM9801 is capable
of accepting (about 1.2Vp-p). In this case the amplitude of
the analog CCD output must be reduced before it enters the
LM9801’s OS input to prevent clipping. This can be done by
reducing the intensity of the light source or shortening the
integration time of the CCD.
The final problem that can occur during VGA calibration
(Result 4) is the ‘‘Signal too weak: increase light intensity or
integration time’’ condition, shown in Figure 11. In this case,
even with the VGA gain set to a maximum of 2.8, the ampli-
tude of one or more pixels is less than the minimum required
for shading correction. The solution is to increase the inten-
sity of the light source or lengthen the integration time of the
CCD to increase the CCD’s output amplitude.
To ensure that a scanner system is manufacturable, the re-
sult of the VGA calibration must always be State 1. States 2,
3, and 4 must be eliminated either by ensuring that the total
variation in light intensity (from all sources) from system to
system to a maximum of 9 dB, or by being able to adjust the
light source’s intensity and/or the CCD’s light integration
time.
5.3 PGA Correction Coefficients (Shading Calibration)
Once the input signal has been centered inside the range
the LM9801 can correct for, correction coefficients must be
generated for each pixel to compensate for the gain error of
that pixel.
TL/H/12814–36
1. Set Offset DAC and Add Bit as determined in Section
5.1.
FIGURE 9. CCD Input Signal Too Strong
The second possible failure mode of the VGA calibration
(Result 3) occurs if there is ‘‘Too much variation’’ in the
amplitude of the pixels coming from the CCD (Figure 10).
The LM9801 can correct for up to a 2.8 to 1 variation in pixel
amplitude. If the variation is greater than this than it must be
reduced before it can perform shading correction on all the
pixels. Typically this is done by using a better light source
that has more uniform illumination, higher quality lenses, or
other opto-mechanical techniques to reduce variation
across all the active pixels.
2. Set the VGA gain to the value determined in Section 5.2.
3. Set the PGA gain to 0 dB.
4. Scan a reference line corresponding to all white or light
grey and store it in memory.
5. Calculate the required gain correction coefficients for
each pixel using the formula:
256
Target Code
e
b
1
Correction Coefficient
n
1.95 Uncorrected Code
#
J
n
Where Uncorrected Code is the ADC output code for pix-
n
0 dB, Target Code is the number
e
el n with the PGA gain
that corresponds to the desired output from the ADC with
the given reference line input, and Correction Coefficient
n
is the gain correction number that is sent to the CD0–CD7
correction databus to provide gain correction for pixel n
when digitizing a line with the LM9801’s PGA gain correc-
tion operating.
If it is difficult or undesirable to do the division, subtraction,
and multiplication operations shown above for every pixel,
then a lookup table can be generated in advance that will
return the Correction Coefficient for any Uncorrected Code.
This table can be stored in ROM or RAM and can speed up
the calibration process. The disadvantage of this technique
is that the Target Code must be fixed when the table is
generated, so only one Target Code can be used (unless
multiple tables are generated).
TL/H/12814–37
FIGURE 10. CCD Input Signal Range Too Wide
All the Correction Coefficients must be stored and sent to
the LM9801 through the CD0–CD7 databus for every line
scanned.
TL/H/12814–38
FIGURE 11. CCD Input Signal Too Weak
http://www.national.com
26
Applications Information (Continued)
6.0 POWER SUPPLY CONSIDERATIONS
6.1 General
6.3 Power Down Mode
Setting the Power Down bit to a ‘‘1’’ puts the device in a low
power standby mode. The CCD outputs (w1, w2, RS, and
TR) are pulled low and the analog sections are turned off to
conserve power. The digital logic will continue to operate if
MCLK continues and SYNC is held high, so for minimum
power dissipation MCLK should be stopped when the
LM9801 enters the Power Down mode. Recovery from Pow-
er Down typically takes 50 ms (the time required for the
reference voltages to settle to 0.5 LSB accuracy).
a
The LM9801 should be powered by a single 5V source
(unless 3V-compatible digital I/O is requiredÐsee Section
6.2). The analog supplies (V ) and the digital supplies (V
and V
A
D
) are brought out individually to allow separate
D(I/O)
bypassing for each supply input. They should not be pow-
ered by two or more different supplies.
a
In systems with separate analog and digital 5V supplies,
all the supply pins of the LM9801 should be powered by the
7.0 COLOR
a
analog 5V supply. Each supply input should be bypassed
to its respective ground with a 0.1 mF capacitor located as
close as possible to the supply input pin. A single 10 mF
tantalum capacitor should be placed near the V supply pin
A
to provide low frequency bypassing.
There are two primary ways to use the LM9801 in a color
system with a triple output (RGB) CCD. The first is to use
one LM9801 with an external multiplexer. This is the sim-
plest solution. The second technique is to use one LM9801
per RGB color.
To minimize noise, keep the LM9801 and all analog compo-
nents as far as possible from noise generators, such as
switching power supplies and high frequency digital busses.
If possible, isolate all the analog components and signals
7.1 Parallel Output CCD, One LM9801
Figure 12 is an example of how to use a single LM9801 with
a triple-output RGB CCD. In this case an entire line of red is
digitized, followed by an entire line of green, then blue. This
solution provides a 2.5 Mpixels/sec (for an effective 830k
RGB pixels/sec after de-interleaving) pixel rate using a high
performance triple output color CCD.
(OS, reference inputs and outputs, V , AGND) on an analog
A
ground plane, separate from the digital ground plane. The
two ground planes should be tied together at a single point,
preferably the point where the power supply enters the PCB.
6.2 3V Compatible Digital I/O
The Mux 1 multiplexer, located between the CCD’s OS out-
puts and the LM9801’s OS input, selects the color to be
digitized according to the states of the A and B inputs (de-
scribed below). The multiplexer’s speed requirements are
minimal because the mux switches at the line rate, not the
pixel rate. Also, since the output of the mux goes into a high
impedance, low-capacitance input, the ON resistance of the
mux is not critical. The 74HC4052 is a good choice for this
application.
If 3V digital I/O operation is desired, the V
D(I/O)
pin may be
g
10% supply.
g
powered by a separate 3V
10% or 3.3V
In this case, all the digital I/O pins (CD0–CD7, CCLK,
MCLK, DD0–DD7, EOC, RD, SYNC, CS, SCLK, SDO, and
SDI) will be 3V compatible. The CCD clock signals (w1, w2,
RS, and TR) remain 5V outputs, powered by V . In this case
D
the V
input should be bypassed to DGND with a
(I/O)
D(I/O)
parallel combination of a 0.1 mF capacitor and a 10 mF tan-
talum capacitor.
TL/H/12814–39
FIGURE 12. Parallel Output CCD Application Circuit
27
http://www.national.com
Applications Information (Continued)
TL/H/12814–40
FIGURE 13. Parallel Output CCD Timing
7.2 Parallel Output CCD, Three LM9801s
To maximize the integration time for the Red, Green, and
Blue photodiodes, the transfer (TR) pulses should be stag-
gered as shown in Figure 13. This is done by a demultiplex-
er (Mux 2) between the TR output of the LM9801 and the
transfer gate inputs of the CCD. If the CCD’s transfer gate
input capacitance is relatively low (see the CCD datasheet
for this specification and the requirements for TR pulse rise
and fall time), then the other half of the 74HC4052 may be
used to switch the TR pulses as shown. If the TR gate input
capacitance is so large that the minimum TR rise and fall
times can not be met because of the 200X max on resist-
ance of the 74HC4052’s switches, then the 74HC4052 can
not be used to multiplex the TR output and should be re-
placed with an active device such as the 74HC155 dual 2-
to-4 demultiplexer.
Figure 14 uses three LM9801s to achieve a 7.5 Mpixel/sec
(2.5M RGB pixels/sec) pixel rate. The three LM9801s are
synchronized by applying the same MCLK and SYNC sig-
nals to all three devices. One LM9801 provides the clock
signals required for the CCD. Since the coefficient data for
all three LM9801s will be latched simultaneously on the ris-
ing edge of CCLK, the correction coefficient bus must either
be at least 24 bits wide (8 correction coefficient bits by 3
LM9801s) or run at a 7.5 MHz rate and be latched into a
buffer between the correction coefficient databus and each
LM9801. Similarly, the output data for all three LM9801s will
be available simultaneously at the 3 output databusses.
Since each LM9801 is dedicated to one color, the VGA gain
does not change during line scan.
Two signals (A and B) must be generated to choose which
color is going to be digitized and receives the TR pulse.
These signals can be as simple as the output of a two bit
counter that counts from 0 to 2 (0, 1, 2, 0, 1, 2, etc.). This
counter should be incremented after the end of the previous
line and before the first transfer pulse of the next line. Also,
since each color will need a different VGA gain, the appro-
priate VGA gain value for each color should be sent to the
LM9801 during this time.
TL/H/12814–41
FIGURE 14. Parallel Output CCD, Three LM9801
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28
Applications Information (Continued)
The Mode is set to Even/Odd, RS Pulse Width is set to its
minimum value, and RS polarity is positive. The timing,
shown in Figure 16, is determined by the RS, SR, and SS
registers. The RS pulse position (RS) is set to 10, dividing
the pixel period so that the signal portion is available for the
first 5 MCLKs following a w1 clock edge and theblack refer-
ence portion appears during the last 2 MCLKs (following the
1 MCLK wide reset pulse). Sample Reference (SR) is set to
14, so it samples the black reference just before the next w1
clock edge. Sample Signal (SS) is set to 8, so it samples the
black reference just before the next reset pulse. These val-
ues can be adjusted to account for differences in CCDs,
CCD data delays, settling time, etc., but this is often not
necessary.
8.0 A TYPICAL GREYSCALE APPLICATION
Figure 15 shows the interface between the LM9801 and a
typical greyscale even/odd output CCD, the TCD1250. The
interface for most other CCDs will be similar, the only differ-
ence being the values for the series resistors (if required).
The clamp capacitor value is determined as shown in Sec-
tion 4.2. The resistor values are usually given in the CCD’s
datasheet. If the datasheet’s requirement is given as a par-
ticular rise/fall time, the resistor can be chosen using the
graph of w1, w2, RS and TR Rise Times Through a Series
Resistance vs Load Capacitance graph in the Typical
Performance Characteristics section. Given the required
rise time and the input capacitance of the input being driven,
the resistor value can be estimated from the graph.
TL/H/12814–43
FIGURE 16. Typical Even/Odd Timing
All 4 digital outputs (w1, w2, RS, and TR) are enabled. The
TR pulse width is set to the minimum, 20 MCLKs, as is the
guardband between w1 and TR. Either of these settings can
be increased if necessary.
The TR polarity is positive, as is the RS polarity. Some
CCDs may require one or both of these signals to be invert-
ed, in which case the corresponding bit can be set to a ‘‘1’’.
If there is an inverting buffer between the LM9801 and the
CCD, these bits may be used to correct the output polarity
at the CCD. Note that if w1 and w2 are inverted, then w2
should be used as w1 at the CCD, and w1 should be used
as w2 at the CCD (Figure 17).
TL/H/12814–42
FIGURE 15. Greyscale CCD Interface Example
These are the Configuration Register parameters recom-
mended for use as a starting point for most even/odd
CCDs:
e
Mode
1 (Even/Odd mode)*
e
RS Pulse Width
0 (1 MCLK)
e
RS Pulse Polarity
RS Pulse Position
0*
10
e
e
Sample Reference Position
14
e
e
Sample Signal Position
8
TL/H/12814–44
w1/w2/RS/TR Enable
1/1/1/1
FIGURE 17. w1 and w2 After Inversion
e
TR Pulse Width
TR-w1 Guardband
0
Since this is a CCD sensor, the Signal Polarity is set to a 1
(inverted) to match the CCD’s output signal. The number of
dummy pixels and optical black reference pixels are given in
the CCD’s datasheet. The dummy pixel register should be
programmed with the number of dummy pixels in the CCD
e
0
e
TR Polarity
0*
e
e
Signal Polarity
Dummy Pixels
1
2*
a
1 (for example, if the CCD has 16 dummy pixels then the
e
Optical Black Pixels
5*
register should contain 17). The optical black reference reg-
ister should be programmed with the number of optical
black pixels in the CCD.
(*Value given in CCD datasheet)
29
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Applications Information (Continued)
The PGA gain coefficient register and PGA Gain Source bit
are used during calibration (see Section 5.0). The Power
Down bit should be set to 0 for normal operation. The Offset
Add bit is also programmed during calibration.
The final ‘‘trick’’ required to interface a CIS to the LM9801 is
the generation of optical black pixels for the LM9801 to
clamp to at the beginning of a line. Unlike CCDs, CIS devic-
es do not have a sequence of optical black pixels at the
beginning of a lineÐthe first pixel out of a CIS is valid image
data. There are several ways to create black pixels for the
LM9801 to clamp to.
The VGA and Offset DAC bits are programmed during cali-
bration (Section 5.0). The Test Mode bits should always be
set to ‘‘0’’.
9.0 TYPICAL CIS APPLICATION
Many CIS sensors (such as those made by Dyna Image
Corporation) have only one clock input, a transfer signal,
and an output signal that is referred to ground (Figure 18).
Figure 19 shows the analog and digital circuitry required to
connect a typical Dyna CIS to the LM9801.
TL/H/12814–47
FIGURE 20. CIS Interface Digital Timing
The simplest solution is to physically place a light shield
(black plastic, tape or metal) over the first 10 or so pixels.
This reduces the voltage output of the CIS to nearly 0V,
which is adequate for the LM9801 to clamp to. This has the
side effect of slightly reducing the number of active pixels
available for image capture.
A second option is to artifically generate ‘‘black’’ pixels by
holding the CLOCK input high for 10 or so RS pulses(Figure
21). This forces the output voltage to zero for the time that
the CLOCK input is high, and only one active image pixel is
lost. The BLACK signal could be generated by the ASIC/ex-
ternal logic that generates a pulse on the first rising edge of
RS after the TR pulse.
TL/H/12814–45
FIGURE 18. CIS Waveforms
TL/H/12814–46
FIGURE 19. Minimum CIS Interface
Because the CIS requires only one clock with a duty cycle of
less than 50%, the LM9801’s RS output is used as the
CIS’s CLK source. w1 and w2 are not used. The 74HC74
D flip-flop is used to lengthen the transfer pulse (SI, or ‘‘Shift
In’’ on the CIS) so that it overlaps the first RS pulse and
meets the timing requirement of the CIS (see Figure 20).
TL/H/12814–48
FIGURE 21. Generating Artificial Black Pixels
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30
Applications Information (Continued)
Suggested timing for CIS devices is:
10.0 HINTS AND COMMON SYSTEM DESIGN
PROBLEMS
e
Mode
0 (Standard Mode)*
e
RS Pulse Width
0 (2 MCLKs)
10.1 Reading and Writing to the Configuration Register
e
RS Pulse Polarity
used)*
RS Pulse Position
0 (or 1 if circuit of Figure 21 is
The Configuration Register sends and receives data LSB
(Least Significant Byte) first. Some microcontrollers send
out data MSB (Most Significant Byte) first. The order of the
bits must be reversed to when using these microcontrollers.
e
0
e
Sample Reference Position
2
Note: Unlike the LM9800, the SYNC pin does not have to be held high to
e
e
Sample Signal Position
14
0/0/1/1
send or receive data to or from the Configuration Register.
w1/w2/RS/TR Enable
10.2 Setting the Dummy and Optical Black Pixel
Registers
e
TR Pulse Width
TR-w1 Guardband
0
e
0
The minimum value in the Dummy Pixels register is 2 (a
value of 0 or 1 will cause errors in the EOC and CCLK tim-
ing). Note that the value in this register should be equal to 1
plus the actual number of dummy pixels in the CCD. For
example, if the CCD being used with the LM9801 has 12
dummy pixels, this register should be set to 13. The mini-
mum number in the Optical Black Pixels register is 1.
e
TR Polarity
1*
e
e
Signal Polarity
Dummy Pixels
0
2
e
Optical Black Pixels
10
(*Value given in CCD datasheet)
As CIS sensors approach pixel rates of 1 MHz and above
(corresponding to MCLK frequencies of 8 MHz and above),
the voltage during the reset level becomes less stable, mak-
ing it difficult to perform CDS on the output (Figure 22). The
solution is to create the ground reference externally, short-
ing the LM9801’s input to ground for half of the time using
the w1 clock, as shown in Figure 23.
10.3 Stretching the TR-w1 Guardband
Some CCDs (Sony’s ILX514, ILX518, and ILX524, for exam-
ple) require a TR to w1 guardband greater than the 100 ns
(2 MCLKs) provided by the LM9801. The circuit shown in
Figure 24 produces a 1 ms wROG (transfer) pulse with a
guardband between the end of the wROG pulse and the
next edge of w1. This is done by setting the LM9801’s TR
pulse width register to 2 ms and using the 74HC4538 to
generate a 1 ms pulse inside that TR period to send to the
CCD.
TL/H/12814–49
FIGURE 22. High Speed CIS Waveforms
TL/H/12814–51
FIGURE 24. Stretching the TR-w1 Guardband
TL/H/12814–50
FIGURE 23. High Speed CIS Interface
31
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Applications Information (Continued)
Figure 25 shows a different technique for increasing the TR-
w1 guardband and/or increasing the length of the TR pulse
by stopping the s MCLK during the TR period. When TR
initially goes high, the first one-shot (U1A) triggers, effec-
&
tively disabling the LM9801’s MCLK for
2 ms, thereby
&
programmed in the configuration register. On the falling
lengthening the TR pulse width by
2 ms over the value
edge of TR, the second one-shot (U1B) fires, disabling the
&
guardband by that amount.
LM9801’s MCLK for
1 ms and increasing the TR-w1
TL/H/12814–52
FIGURE 25. Stretching TR and the TR-w1 Guardband
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32
Physical Dimensions inches (millimeters) unless otherwise noted
52-Pin Plastic Leaded Chip Carrier (PLCC)
Order Number LM9801CCV
NS Package Number V52A
33
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
52-Pin Thin Quad Flatpak
Order Number LM9801CCVF
NS Package Number VEG52A
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