LMC1983CIV
更新时间：2024-09-18 01:55:29
品牌：NSC
描述：Digitally-Controlled Stereo Tone and Volume Circuit with Three Selectable Stereo Inputs
概述
规格参数
数据手册LMC1983CIV 概述
Digitally-Controlled Stereo Tone and Volume Circuit with Three Selectable Stereo Inputs 数字控制立体声音调和音量电路的三种可选择立体声输入 音频控制集成电路
LMC1983CIV 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 包装说明： | QCCJ, LDCC28,.5SQ | Reach Compliance Code： | unknown |
| ECCN代码： | EAR99 | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.7 | 信道分离： | 80 dB |
| 商用集成电路类型： | TONE CONTROL CIRCUIT | 谐波失真： | 0.5% |
| JESD-30 代码： | S-PQCC-J28 | JESD-609代码： | e0 |
| 长度： | 11.43 mm | 频带数量： | 2 |
| 信道数量： | 2 | 功能数量： | 1 |
| 端子数量： | 28 | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | QCCJ | 封装等效代码： | LDCC28,.5SQ |
| 封装形状： | SQUARE | 封装形式： | CHIP CARRIER |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 电源： | 9 V |
| 认证状态： | Not Qualified | 座面最大高度： | 4.57 mm |
| 子类别： | Audio Control ICs | 最大压摆率： | 25 mA |
| 最大供电电压 (Vsup)： | 12 V | 最小供电电压 (Vsup)： | 6 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | INDUSTRIAL | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | J BEND | 端子节距： | 1.27 mm |
| 端子位置： | QUAD | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 11.43 mm | Base Number Matches： | 1 |
LMC1983CIV 数据手册
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PDF下载August 1992
LMC1983
Digitally-Controlled Stereo Tone and Volume Circuit with
Three Selectable Stereo Inputs
n Three pairs of stereo inputs
n Loudness compensation
n 40 position 2 dB/step volume attenuator plus mute
n Independent left and right volume controls
n Low noise-suitable for use with DNR® and Dolby® noise
reduction
General Description
The LMC1983 is a monolithic integrated circuit that provides
volume, balance, tone (bass and treble), loudness controls
and selection between three pairs of stereo inputs. These
functions are digitally controlled through a three-wire com-
munication interface. There are two digital inputs for easy in-
n External processor loop
n Signal handling suitable for compact discs
n Pop-free switching
n Serially programmable: INTERMETAL bus (IM) interface
n 6V to 12V single supply operation
n 28 Pin DIP or PLCC Package
terface to other audio peripherals such as stereo decoders.
The LMC1983 is designed for line level input signals
(300 mV–2V) and has a maximum gain of −0.5 dB. Volume
is set at minimum and tone controls are flat when supply volt-
age is first applied.
Low noise and distortion result from using analog switches
and poly-silicon resistor networks in the signal path.
Additional tone control can be achieved using the LMC835
stereo 7-band graphic equalizer connected to the
LMC1983’s SELECT OUT/SELECT IN external processor
loop.
Applications
n Stereo television
n Music reproduction systems
n Sound reinforcement systems
n Electronic music (MIDI)
n Personal computer audio control
Features
n Low noise and distortion
Block Diagram
DS011279-1
DNR® is a registered trademark of National Semiconductor Corporation.
Dolby® is a registered trademark of Dolby Labs.
© 1999 National Semiconductor Corporation
DS011279
www.national.com
Absolute Maximum Ratings (Notes 1,
2)
Lead Temperature
N Package,
(Soldering, 10 Seconds)
+260˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V Package,
(Vapor Phase, 60 Seconds)
215˚C
220˚C
2 kV
Infrared, (15 Seconds)
Supply Voltage (V+ − GND)
Voltage at any Pin
15V
ESD Susceptability (Note 5)
GND − 0.2V to V+ + 0.2V
Operating Ratings (Notes 1, 2)
Input Current at any Pin
(Note 3)
5 mA
20 mA
Temperature Range
TMIN ≤ TA ≤ TMAX
−40˚C ≤ TA ≤ +85˚C
6V to 12V
Package Input Current (Note 3)
Power Dissipation (Note 4)
Junction Temperature
LMC1983CIN, LMC1983CIV
Supply Voltage Range (V+ − V−)
500 mW
+125˚C
Storage Temperature
−65˚C to +150˚C
Electrical Characteristics
The following specifications apply for V+ 9V, fIN 1 kHz, input signal (300 mV) applied to INPUT 1, volume 0 dB, bass
=
=
=
=
=
=
=
0 dB, treble 0 dB, and loudness is off unless otherwise specified. All limits apply for TA TJ +25˚C.
Symbol
Parameter
Conditions
Typical
Limit
Unit
(Note 6) (Note 7)
(Limit)
IS
Supply Current
15
25
mA (max)
Vrms (min)
VIN
Input Voltage
Clipping Level (1.0% THD),
2.3
2.0
Select Out (Pins 7, 22)
Left and Right channels;
Output Pins 13, 16
THD
Total Harmonic Distortion
=
VIN 0.3 Vrms
;
0.008
0.4
0.1
1.0
1.0
0.5
% (max)
% (max)
% (max)
% (max)
=
fIN 100 Hz, 1 kHz, 10 kHz
=
VIN 2.0 Vrms
;
=
fIN 100 Hz, 1 kHz
=
VIN 2.0 Vrms
;
0.5
=
fIN 10 kHz
=
VIN 0.5 Vrms; Bass and Treble
0.07
Tone Controls Set at Maximum
=
VIN 0.3 Vrms; Volume
Attenuator at −20 dB, Bass and Treble
Tone Controls Set at Maximum
0.06
2.0
18
0.15
4.0
20
% (max)
mV (max)
mV (max)
=
DC Shifts
VIN 0.3 Vrms; between Any
Two Adjacent Control Settings
=
VIN 0.3 Vrms
;
All Mode and Input Positions
Pins 7, 22, (470Ω to Ground at Input)
Pins 13, 16
ROUT
AC Output Impedance
AC Input Impedance
150
26
200
40
Ω (max)
Ω (max)
kΩ (max)
kΩ (min)
dB (max)
RIN
Pins 4, 5, 23, 24, 25
50
72
35
Volume Attenuator Range
Pins 13, 16; Volume
0.5
80
1.5
Attenuation at
0100010XXX000000 (0 dB)
0100010XXX101XXX (80 dB);
(Relative to Attenuation at
78
82
dB (min)
dB (max)
the 0 dB Setting)
Volume Step Size
All Volume Attenuation Settings from
0100010XXX101XXX (80 dB) to
0100010XXX000000 (0 dB) (Note 9)
2.0
1.5
2.5
dB (min)
dB (min)
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2
Electrical Characteristics (Continued)
The following specifications apply for V+ 9V, fIN 1 kHz, input signal (300 mV) applied to INPUT 1, volume 0 dB, bass
=
=
=
=
=
=
=
0 dB, treble 0 dB, and loudness is off unless otherwise specified. All limits apply for TA TJ +25˚C.
Symbol
Parameter
Conditions
Typical
Limit
Unit
(Note 6) (Note 7)
(Limit)
All Volume Attenuation Settings from
0100010XXX100110 (76 dB) to
0100010XXX000000 (0 dB)
±
±
±
Channel-to-Channel
Tracking Error
0.1
1.5
2.0
dB (min)
dB (min)
from
0100010XXX101XXX (80 dB) to
0100010XXX100111 (78 dB)
=
Mute Attenuation
Bass Gain Range
VIN 1.0 Vrms
105
86
dB (max)
dB (min)
dB (max)
dB (max)
dB (min)
dB (max)
dB (min)
dB (max)
dB (max)
dB (min)
dB (max)
=
±
±
±
fIN 100 Hz, Pins 13, 16
12
10.0
14.0
=
±
±
1.5
1.5
Bass Tracking Error
Bass Step Size
fIN 100 Hz, Pins 13, 16
0.1
=
fIN 100 Hz, Pins 13, 16
2.0
(Relative to Previous Level)
2.5
=
±
±
±
Treble Gain Range
fIN 10 kHz, Pins 13, 16
12
10.0
14.0
=
±
±
Treble Tracking Error
Treble Step Size
fIN 10 kHz, Pins 13, 16
0.1
1.5
1.5
2.5
=
fIN 10 kHz, Pins 13, 16
2.0
(Relative to Previous Level)
Frequency Response
Loudness
VIN Applied to Input 1 and Input 2;
=
±
±
1.0
fIN 20 Hz − 20 kHz
0.1
dB (max)
(Relative to Signal Amplitude at 1 kHz)
=
Volume Attenuator 40 dB, Loudness
on (See Figure 5 )
Gain at 100 Hz (Referenced
to Gain at 1 kHz)
11.5
6.5
95
13.5
9.5
8.5
4.5
90
dB (max)
dB (min)
dB (max)
dB (min)
dB (min)
Gain at 10 kHz (Referenced
to Gain at 1 kHz)
=
VIN 1.0 Vrms, A Weighted,
Signal-to-Noise Ratio
=
Measured at 1 kHz, RS 470Ω
Channel Balance
All Volume Settings
0.2
80
1.0
60
dB (max)
dB (min)
Channel Separation
Input Pins 4, 25: Output Pins 13, 16;
=
VIN 1.0 Vrms (Note 8)
Input-Input Isolation
470Ω to AC Ground on Unused Input
95
32
60
28
dB (min)
dB (min)
V+ 9 VDC; 200 mVrms, 100 Hz
=
PSSR Power Supply Rejection
Ratio
Sinewave Applied to Pin 26
fCLK
Clock Frequency
5.0
1.3
2.9
0.4
1.2
1.0
2.0
5.5
0.8
3.5
2.0
0.8
MHz (max)
V (min)
VIN(1)
Logic “1” Input Voltage
Pins 1, 27, 28 (IM Bus)
Pins 2, 3
V (min)
VIN(0)
Logic “0” Input Voltage
Pins 1, 27, 28 (IM Bus)
Pins 2, 3
V (max)
V (max)
V (min)
VOUT(1) Logic “1” Output Voltage
VOUT(0) Logic “0” Output Voltage
Pin 28 (IM Bus)
Pin 28 (IM Bus)
0.4
V (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the deivce may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are specified with respect to ground.
−
+
<
>
V ) the absolute value of the current at that pin should be
Note 3: When the input voltage (V ) at any pin exceeds the power supply voltages (V
IN IN
V
or V
IN
limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply voltages with 5 mA current limit to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T , θ , and the ambient temperature T . The maximum
JMAX JA
=
− T )/θ or the number given in the Absolute Maximum Ratings, whichever is lower. For the LMC1983CIN, T
JMAX
A
=
allowable power dissipation is P
(T
JMAX
D
A
JA
+125˚C, and the typical junction-to-ambient thermal resistance, when board mounted, is 67˚C/W.
3
www.national.com
Electrical Characteristics (Continued)
Note 5: Human body model; 100 pF discharged through a 1.5 kΩ resistor.
=
Note 6: Typicals are at T
+25˚C and represent the most likely parametric norm.
J
Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: The Input-Input Isolation is tested by driving one input and measuring the output when the undriven input are selected.
Note 9: The Volume Step Size is defined as the change in attenuation between any two adjacent volume attenuation settings. The nominal Volume Step Size is 2 dB.
Typical Performance Characteristics
Supply Current
vs Supply Voltage
Output Voltage
vs Supply Voltage
THD vs
Load Impedance
DS011279-11
DS011279-12
DS011279-13
DS011279-16
DS011279-19
THD vs
Load Impedance
CCIR Output Noise
vs Volume Setting
Channel Separation
vs Frequency
DS011279-14
DS011279-15
THD vs VIN
(VOUT Constant)
Mute Gain
vs Frequency
THD vs Frequency
DS011279-18
DS011279-17
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4
Typical Performance Characteristics (Continued)
Tone Control Response
Loudness Response
Select Input Impedance
vs Frequency
with Equal Bass and
vs Frequency
Treble Control Settings
DS011279-21
DS011279-22
DS011279-20
Connection Diagram
DS011279-2
Top View
Order Number LMC1983CIN
See NS Package Number N28B
DS011279-10
Top View
Order Number LMC1983CIV
See NS Package Number V28A
5
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tween this pin and ground to provide
an AC ground for the internal
half-supply voltage reference.
Pin Description
CLK (1)
The INTERMETAL (IM) Bus clock is
applied to the CLOCK pin. This input
accepts a TTL or CMOS level signal.
The input is used to clock the DATA
signal. A data bit must be valid on the
rising clock edge.
GROUND (15)
V+ (26)
This pin is connected to analog
ground.
This is the power supply connection.
The LMC1983 is operational with sup-
ply voltages from 6V to 12V. This pin
should be bypassed to ground through
a 1.0 µF capacitor.
DIGITAL INPUT
1 & 2 (2, 3)
Internally tied high to V+ through a
30 kΩ pull-up resistor, these inputs al-
low a peripheral device to place any
single-bit, active low digital information
onto the IM Bus. It is then sent out to
the controlling device through the
DATA pin. Examples of such informa-
tion could include indication of the
presence of a Second Audio Program
(SAP) or an FM stereo carrier.
ID (27)
This is the IDENTITY digital input that,
when low, signals the LMC1983 to re-
ceive, from a controlling device, a de-
vice address (40H–47H), present on
the DATA line.
DATA (28)
This is the serial data input for commu-
nications sent by a controller. The con-
troller must have open drain outputs
used with external pull-up resistors.
The data rate has a maximum fre-
quency of 1 MHz. The LMC1983 re-
quires 16 bits of data to control or
change a function: the first 8 bits select
the LMC1983 and one of eight func-
tions. The final eight bits set the func-
tion to a desired value. The data must
be valid on the rising edge of the
CLOCK input signal.
INPUTS 1, 2 & 3
These are the LMC1983’s three stereo
(4, 25; 5, 24; 6, 23) input pairs.
SELECT OUT
(7, 22)
The selected INPUT signal is available
at this output. This feature allows ex-
ternal signal processors such as noise
reduction or graphic equalizers to be
used. This output can typically sink
1 mA. These pins should be capaci-
tively coupled to pins 8 and 21, re-
spectively, if no external processor is
used.
SELECT IN
(8, 21)
These are the inputs that an external
signal processor uses to return a sig-
nal to the LMC1983. These pins
should be capacitively coupled to pins
7 and 22, respectively, if no external
processor is used.
General Information
The LMC1983 is a CMOS/bipolar building block intended for
high fidelity audio signal processing. It is designed for line
level inputs signals (300 mV − 2V) and has a maximum gain
of −0.5 dB. While the LMC1983 is manufactured with CMOS
processing, NPN transistors are used to build low noise op
amps. The combination of CMOS switches, bipolar op amps,
and poly-silicon resistors make it possible to achieve an or-
der of magnitude quality improvement over other bipolar cir-
cuits that use analog multipliers to accomplish gain adjust-
ment. Internal circuits set the volume to minimum, tone
controls to flat, the mute to on, and all other functions off
when power is first applied. Individual left and right volume
controls are software programmed to achieve the stereo bal-
ance function. Figure 1 shows the connection diagram of a
typical LMC1983 application.
TONE IN
(9, 20)
These are the inputs to the tone con-
trol amplifier. See the Application Infor-
mation section titled “Tone Control Re-
sponse”.
TONE OUT
(10, 19)
Tone control amplifier output. See the
Application Information section titled
“Tone Control Response”.
OP AMP
OUT (11, 18)
These outputs are used with external
tone control capacitors. Internally, this
output is applied to the volume attenu-
ators.
The LMC1983 has internal decoding logic that allows a mi-
croprocessor (µP) or microcontroller (µC) to communicate di-
rectly to the audio control circuitry through an INTERMETAL
(IM) Bus interface. This three-wire interface consists of a
bi-directional DATA line, a Clock (CLK) input line, and an
Identity (ID) line. Address and function selection data (8 bits)
are serially shifted from the controller to the LMC1983. This
is followed by 8 bits of function value data. Data present in
the internal shift register is latched and the instruction is
executed.
LOUDNESS
(12, 17)
The output signal on these pins is a
voltage taken from the volume attenu-
ator’s −40 dB tap point. An external
R–C network is connected to these
pins.
MAIN
OUTPUT
(13, 16)
The output signal from these pins
drives a stereo power amplifier. The
output can typically sink 1 mA.
BYPASS (14)
A 10 µF capacitor is connected be-
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6
General Information (Continued)
DS011279-3
FIGURE 1. Typical Application
Application Information
INPUT SELECTOR
The output signal at pins 7 and 22 can be used to drive ex-
teral audio processing circuits such as noise reduction
(LM1894–DNR or Dolby) or graphic equalizers (LMC835). It
is important that if any noise reduction is used it be placed
ahead of any tone controls or equalizers in the external cir-
cuit path to preserve the frequency spectrum of the selected
input signal. Otherwise, any frequency equalization could
prevent the proper operation of the noise reduction circuit. If
no external processor is used, a capacitor should be used to
couple the SELECT OUT signals directly to pins 8 and 21,
respectively.
The LMC1983’s input selector and mode control are shown
in Figure 2. The input selector selects one of three stereo
signal sources or a mute function with typical attenuation of
100 dB. The selected signals are then sent to a mode control
matrix. As shown in Table 1, the matrix provides normal ste-
reo or can direct any given channel to both LEFT or RIGHT
SELECT OUTPUTs. The third matrix mode is normal stereo.
The control matrix output is buffered and appears on each
channel’s respective SELECT OUT pin (7, 22). Switching
noise is kept to a minimum when mute is selected by using
a 50 kΩ bias resistor.
MINIMUM LOAD IMPEDANCE
Noise performance is optimized through the use of emitter
followers in the mode control matrix’s output. Internal 50 kΩ
resistors are connected to each input selector pin to provide
the proper bias point for the emitter follower buffers. Each in-
The LMC1983 employs emitter-followers to buffer the se-
lected stereo channels. The buffered signals are available at
pins 7 and 22 (SELECT OUT). The SELECT OUT buffers op-
erate with a typical bias current of 1 mA.
ternal 50 kΩ bias resistor is connected to
a common
half-supply (V+/2) source. This produces a voltage at pins 7
and 22 (SELECT OUT) that is 1.4V below V+/2 (typically
The Electrical Specifications table lists a maximum input sig-
nal of 2.0 Vrms (2.8 Vpeak) for 1% THD at the SELECT OUT
pins. This distortion level is achieved when the minimum AC
load impedance seen by the SELECT OUT pins is 2.5 kΩ
(2.5V/1 mA). Using lower load impedances results in clipping
3.1V with V+ 9V). Since a DC voltage is present at the in-
=
put pins (4, 5, 6, 23, 24, and 25), input signals should be AC
coupled through a 1 µF capacitor.
7
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The SELECT IN pins have an input impedance that varies
with the BASS and TREBLE control settings. The input im-
pedance is 100 kΩ at DC and 19 kΩ at 1 kHz when the con-
trols are set at 0 dB. Minimum input impedance of 30.4 kΩ at
DC and 16 kΩ at 1 kHz occurs when maximum boost is se-
lected. At 10 kHz the minimum input impedance, with the
tone controls flat, is 6.8 kΩ and, with the tone controls at
maximum boost, is 2.5 kΩ.
Application Information (Continued)
at lower output levels. If the load impedance is DC-coupled,
an increased quiescent current can flow. Latch-up may occur
if the total emitter current exceeds 5 mA. Thus, maximum
output voltage can be increased and much lower distortion
levels can be achieved using load impedances of at least
25 kΩ.
INPUT IMPEDANCE
The input impedance of pins 4, 5, 6, 23, 24 and 25 is defined
by internal bias resistors and is typically 50 kΩ.
DS011279-4
FIGURE 2. Input and Mode Select Circuitry
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8
Application Information (Continued)
TABLE 1. IM Bus Programming Codes for LMC1983
Address
(A7–A0)
01000000
Function
Data
Function
Selected
INPUT1
INPUT2
INPUT3
MUTE
Input Select + Mute
XXXXXX00
XXXXXX01
XXXXXX10
XXXXXX11
XXXXXXX0
XXXXXXX1
XXXX0000
XXXX0011
XXXX0110
XXXX1001
XXXX11XX
XXXX0000
XXXX0011
XXXX0110
XXXX1001
XXXX11XX
XX000000
XX010100
XX101XXX
XX11XXXX
XX000000
XX010100
XX101XXX
XX11XXXX
XXXXX100
XXXXX101
XXXXX11X
XXXXXXD1D0
01000001
01000010
Loudness
Bass
Loudness OFF
Loudness ON
−12 dB
−6 dB
FLAT
+6 dB
+12 dB
−12 dB
−6 dB
01000011
Treble
FLAT
+6 dB
+12 dB
0 dB
01000100
01000101
Left Volume
Right Volume
Mode Select
−40 dB
−80 dB
−80 dB
0 dB
−40 dB
−80 dB
−80 dB
Left Mono
Stereo
01000110
01000111
Right Mono
=
D0 Digital Input 1
Read Digital Input 1
or
=
D1 Digital Input 2
Digital Input 2
on IM Bus
9
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C3 and C2 sets the mid-frequency gain. Symmetrical tone
Application Information (Continued)
=
response is achieved when C2
C3. However, with
=
EXTERNAL SIGNAL PROCESSING
C2 2(C3) and the tone controls set to “flat”, the frequency
response will be flat at 20 Hz and 20 kHz, and +6 dB at
1 kHz.
The SELECT OUT pins (7 and 22) enable greater system
design flexibility by providing a means to implement an ex-
ternal processing loop. This loop can be used for noise re-
duction circuits such as DNR (LM1894) or multi-band
graphic equalizers (LMC835). If both are used, it is important
to ensure that the noise reduction circuitry precede the
equalization circuits. Failure to do so results in improper op-
eration of the noise reduction circuits. The system shown in
Figure 3 utilizes the external loop to include DNR and a
multi-band equalizer.
The frequency where a tone control begins to deviate from a
flat response is referred to as the turn-over frequency. With
=
=
C
C2 C3, the LMC1983’s treble turn-over frequency is
nominally
The bass turn-over frequency is nominally
TONE CONTROL RESPONSE
Bass and treble tone controls are included in the LMC1983.
The tone controls use just two external capacitors for each
stereo channel. Each has a corner frequency determined by
the value of C2 and C3 (see Figure 4 ) and internal resistors
in the feedback loop of the internal tone amplifier. The
maximum-boost or cut is determined by the data sent to the
LMC1983 (see Table 1).
when maximum boost is chosen. The inflection points (the
frequencies where the boost or cut is within 3 dB of the final
value) are for treble and bass
The typical tone control response shown in Typical Perfor-
=
=
mance Curves were generated with C2 C3 0.0082 µF
and show the response for each step. When modifying the
tone control response it is important to note that the ratio of
DS011279-5
FIGURE 3. System Block Diagram Utilizing the External Processing Loop (One Channel Shown)
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10
The LMC1983’s loudness function uses external compo-
nents R1, R2, C4 and C5, as shown in Figure 5, to select the
frequencies where bass and treble boost begin. The amount
of boost is dependent on the volume attenuator’s setting.
The loudness characteristic, with the volume attenuator set
at 40 dB, has a transfer function of
Application Information (Continued)
The external components R1 and C4 can be eliminated and
pin 11(18) left open if bass boost is the only desired loudness
characteristic.
DS011279-6
FIGURE 4. The Tone Control Amplifier
Increasing the values of C2 and C3 decreases the turnover
and inflection frequencies: i.e., the Tone Control Response
Curves shown in Typical Performance Curves will shift left
when C2 and C3 are increased and shift right when C2 and
DS011279-7
FIGURE 5. Loudness Control Circuit
=
=
C3 are decreased. With C2 C3 0.0082, 2 dB steps are
achieved at 100 Hz and 10 kHz. Changing C2 and C3 to
0.01 µF shifts the 2 dB per step frequency to 72 Hz and
8.3 kHz. If the tone control capacitors’ size is decreased
SERIAL DATA COMMUNICATION
The LMC1983 uses the INTERMETAL serial bus (IM Bus)
standard. Serial data information is sent to the LMC1983
over a three wire IM Bus consisting of Clock (CLK), Data
(DATA), and Identity (ID). The DATA line is bidirectional and
the CLK and ID lines are unidirectional from the micropro-
cessor or micontroller to the LMC1983. The LMC1983’s bidi-
rectional capability is accomplished by using an open drain
output on the DATA line and an external 1 kΩ pull-up resistor.
=
=
these frequencies will increase. With C2 C3 0.0068 µF
the 2 dB steps take place at 130 Hz and 11.2 kHz.
LOUDNESS
The human ear has less sensitivity to high and low frequen-
cies relative to its sensitivity to mid-range frequencies be-
tween 2 kHz and 6 kHz for any given acoustic level. The low
and high frequency sensitivity decreases faster than the sen-
sitivity to the mid-range frequencies as the acoustic level
drops. The LMC1983’s loudness function can be used to
help compensate for the decreased sensitivity by boosting
the gain at low and high frequencies as the volume control
attenuation increases (see the curve labeled “Gain vs Fre-
quency with Loudness Active”).
The LMC1983 responds to address values from 01000000
(40H) through 01000111 (47H). The addresses select one of
the eight available functions (see Table 1). The IM Bus’ lines
have a logic high standby state when using TTL logic levels.
As shown in Figure 6, data transmission is initiated by low
levels on CLK and ID. Next, eight address bits are sent. This
address information includes the code to select one of the
LMC1983’s desired functions. Each address bit is clocked in
on the rising edge of CLK. The ID line is taken high after the
eight bits of address data are received by the LMC1983.
DS011279-8
FIGURE 6. LMC1983’s INTERMETAL Serial Bus Timing
The controlling system continues toggling the CLK line eight
more times. Data that determines the selected function’s op-
erating point is written into, or single bit information on DIGI-
Table 1 also details the serial data structure, range, and bit
assignments that sets each function’s operating point. The
volume and tone controls’ function control data binarily incre-
ments from zero to maximum as the function’s operating
point changes from 80 dB attenuation to 0 dB attenuation
(volume) or −12 dB to +12 dB (tone controls). Note that not
all data bits are needed by each function. The extra bits
shown as “X”s (“don’t cares”) are position holders and have
TAL INPUT
1 or DIGITAL INPUT 2 is read from, the
LMC1983. Finally, the end of transmission is signaled by
pulsing the ID line low for a minimum of 3 µs. The transmit-
ted function data is latched and the function changes to its
new setting.
11
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DIGITAL I/O
Application Information (Continued)
The LMC1983’s two Digital Input pins, 2 and 3, provide
single-bit communication between a peripheral device and
the controller over the IM Bus. Each pin has an internal
30 kΩ pull-up resistor. Therefore, these pins should be con-
nected to open collector/drain outputs. The type of informa-
tion that could be received on these lines and retrieved by a
controller include FM stereo pilot indication, power on/off,
Secondary Audio Program (SAP), etc.
no affect on a respective control. They are necessary to
properly position the data in the LMC1983’s internal data
shift register. Unexpected results may take place if these bits
are not sent.
The LMC1983’s internal data shift register can handle either
a 16-bit word or two 8-bit serial data transmissions. It is the
final 8 bits of data received before the ID line goes high that
are used as the LMC1983 selection and function addresses.
The final eight bits after the ID line returns high are used to
change a function’s operating point. CLK must be stopped
when the final 8 data bits are received. The data stored in the
internal data latch remains unchanged until the ID is pulsed,
signifying the end of data transmission. When ID is pulsed,
the new data in the data shift register is latched into the data
latch and the selected function takes on a new operating
point.
According to Table 1, the logic state of DIGITAL INPUT 1 and
DIGITAL INPUT 2 is latched and can be retrieved over the IM
Bus using the read command (47H). The single-bit informa-
tion sent on the IM Bus is active low since these lines are in-
ternally pulled high.
A complete description and more information concerning the
IM Bus is given in the appendix of ITT’s CCU2000
datasheet.
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12
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number LMC1983CIN
NS Package Number N28B
Order Number LMC1983CIV
NS Package Number V28A
13
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Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
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Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
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Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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