LMC6572BIMMX [NSC]
Low Voltage (2.7V and 3V) Operational Amplifier; 低电压（ 2.7V和3V ）运算放大器
| 型号： | LMC6572BIMMX |
| 厂家： | 
National Semiconductor |
| 描述： | Low Voltage (2.7V and 3V) Operational Amplifier |
| 文件： | 总13页 (文件大小：432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1996
LMC6572 Dual/LMC6574 Quad
Low Voltage (2.7V and 3V) Operational Amplifier
General Description
Low voltage operation and low power dissipation make the
LMC6574/2 ideal for battery-powered systems.
Features
(Typical unless otherwise noted)
n Guaranteed 2.7V and 3V Performance
3V amplifier performance is backed by 2.7V guarantees to
ensure operation throughout battery lifetime. These guaran-
tees also enable analog circuits to operate from the same
3.3V supply used for digital logic.
n Rail-to-Rail Output Swing (within 5 mV of supply rail,
100 kΩ load)
n Ultra-Low Supply Current: 40 µA/Amplifier
n Low Cost
Battery life is maximized because each amplifier dissipates
only micro-watts of power.
n Ultra-Low Input Current: 20 fA
=
=
@
n High Voltage Gain VS 2.7V, RL 100 kΩ: 120 dB
n Specified for 100 kΩ and 5 kΩ loads
n Available in MSOP Package
The LMC6574/2 does not sacrifice functionality for low volt-
age operation. The LMC6574/2 generates 120 dB of
open-loop gain just like a conventional amplifier, but the
LMC6574/2 can do this from a 2.7V supply.
Applications
n Transducer Amplifier
n Portable or Remote Equipment
n Battery-Operated Instruments
n Data Acquisition Systems
These amplifiers are designed with features that optimize
low voltage operation. The output voltage swings rail-to-rail
to maximize signal-to-noise ratio and dynamic signal range.
The common-mode input voltage range extends from
800 mV below the positive supply to 100 mV below ground.
n Medical Instrumentation
n Improved Replacement for TLV2322 and TLV2324
This device is built with National’s advanced Double-Poly
Silicon-Gate CMOS process.
LMC6572 is also available in MSOP package which is al-
most half the size of a SO-8 device.
Connection Diagrams
8-Pin DIP/SO/MSOP
14-Pin DIP/SO
DS011934-1
Order Number LMC6572AIN, LMC6572BIN,
LMC6572AIM, LMC6572BIM or LMC6572BIMM
See NS Package Number N08E, M08A or MUA08A
DS011934-2
Order Number LMC6574AIN, LMC6574BIN,
LMC6574AIM or LMC6574BIM
See NS Package Number N14A or M14A
© 1999 National Semiconductor Corporation
DS011934
www.national.com
Ordering Information
Package
Temperature Range
Industrial, −40˚C to +85˚C
LMC6572AIN, LMC6572BIN
LMC6572AIM, LMC6572BIM
LMC6572AIMX, LMC6572BIMX
LMC6572BIMM
NSC Drawing
Transport
Media
8-Pin Molded DIP
8-Pin Small Outline
N08E
M08A
Rail
Rail
Tape and Reel
Rail
8-Pin Mini SO
MUA08A
LMC6572BIMMX
Tape and Reel
Rail
14-Pin Molded DIP
14-Pin Small Outline
LMC6574AIN, LMC6574BIN
LMC6574AIM, LMC6574BIM
LMC6574AIMX, LMC6574BIMX
N14A
M14A
Rail
Tape and Reel
www.national.com
2
Absolute Maximum Ratings (Note 1)
Junction Temperature (Note 4)
150˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings (Note 1)
Supply Voltage
2.7V ≤ V+ ≤ 11V
ESD Tolerance (Note 2)
Differential Input Voltage
Voltage at Input/Output Pin
2000V
Supply Voltage
(V+) +0.3V,
(V−) −0.3V
12V
Junction Temperature Range
LMC6572AI, LMC6572BI
LMC6574AI, LMC6574BI
±
−40˚C ≤ TJ ≤ +85˚C
−40˚C ≤ TJ ≤ +85˚C
Thermal Resistance (θJA
)
Supply Voltage (V+ − V−)
Current at Input Pin
N Package, 8-Pin Molded DIP
M Package, 8-Pin Surface Mount
MSOP Package, 8-Pin Mini SO
N Package, 14-Pin Molded DIP
M Package, 14-Pin Surface Mount
115˚C/W
193˚C/W
217˚C/W
81˚C/W
±
5 mA
±
Current at Output Pin (Note 3)
Current at Power Supply Pin
Lead Temperature
10 mA
35 mA
126˚C/W
(Soldering, 10 Seconds)
Storage Temperature Range
260˚C
−65˚C to +150˚C
2.7V DC Electrical Characteristics
+
−
+
=
=
= = =
>
0V, VCM VO V /2 and RL 1MΩ. Bold-
Unless otherwise specified, all limits guaranteed for TJ 25˚C. V
2.7V, V
face limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Typ
(Note 5)
LMC6574AI LMC6574BI
LMC6572AI LMC6572BI
Units
Limit
(Note 6)
3
Limit
(Note 6)
7
V+ 2.7V and 3V
0.5
1.5
mV
Max
=
VOS
TCVOS
IB
Input Offset Voltage
3.5
7.5
Input Offset Voltage
Average Drift
µV/˚C
Input Current
0.02
0.01
pA
Max
pA
10
6
10
6
IOS
Input Offset Current
Max
Tera Ω
pF
>
1
RIN
CIN
Input Resistance
Common-Mode
Input Capacitance
Common Mode
Rejection Ratio
3
CMRR
0V ≤ VCM ≤ 3.5V
75
75
63
60
60
57
dB
Min
dB
V+ 5V
=
+PSRR Positive Power Supply
Rejection Ratio
2.7V ≤ V+ ≤ 5V,
67
60
V− 0V
65
58
Min
dB
=
−PSRR Negative Power Supply
Rejection Ratio
−2.7V ≤ V− ≤ −5V,
83
75
67
V+ 0V
73
65
Min
V
=
VCM
Input Common-Mode
Voltage Range
V+ 2.7V and 3V
=
−0.1
V+ − 0.8
1000
500
−0.05
0
V+ − 1.0
V+ − 1.3
−0.05
0
V+ − 1.0
V+ − 1.3
for CMRR ≥ 50 dB
Max
V
Min
V/mV
=
AV
Large Signal
Voltage Gain
RL 100 kΩ
Sourcing
Sinking
(Note 7)
V/mV
3
www.national.com
2.7V DC Electrical Characteristics (Continued)
+
−
+
=
=
= = =
>
0V, VCM VO V /2 and RL 1MΩ. Bold-
Unless otherwise specified, all limits guaranteed for TJ 25˚C. V
2.7V, V
face limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Typ
(Note 5)
LMC6574AI LMC6574BI
LMC6572AI LMC6572BI
Units
Limit
(Note 6)
2.68
2.66
0.03
0.05
2.55
2.45
0.15
0.25
2.98
2.96
0.03
0.05
2.85
2.75
0.15
0.25
4.0
Limit
(Note 6)
2.65
2.62
0.06
0.09
2.45
2.35
0.25
0.35
2.95
2.93
0.06
0.09
2.75
2.65
0.25
0.35
3.0
V+ 2.7V
2.695
0.005
2.66
0.04
2.995
0.005
2.96
0.04
6.0
V
Min
V
=
VO
Output Swing
+
=
RL 100 kΩ to V /2
Max
V
V+ 2.7V
=
+
=
RL 5 kΩ to V /2
Min
V
Max
V
V+ 3V
=
+
=
RL 100 kΩ to V /2
Min
V
Max
V
V+ 3V
=
+
=
RL 5 kΩ to V /2
Min
V
Max
mA
Min
mA
Min
µA
=
Sourcing, VO 0V
ISC
Output Short
Circuit Current
3.0
2.0
=
Sinking, VO 2.7V
4.0
3.0
2.5
2.0
1.5
IS
Supply Current
Quad Package
160
240
240
+
V+ +2.7V, VO V /2
280
280
Max
µA
=
=
Quad Package
+
160
240
240
V+ +3V, VO V /2
280
280
Max
µA
=
=
Dual Package
+
80
120
120
V+ +2.7V, VO V /2
140
140
Max
µA
=
=
Dual Package
+
80
120
120
V+ +3V, VO V /2
140
140
Max
=
=
2.7V AC Electrical Characteristics
+
−
+
=
=
=
= =
>
0V, VCM VO V /2 and RL 1 MΩ. Bold-
Unless otherwise specified, all limits guaranteed for TJ 25˚C, V
2.7V, V
face limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Typ
(Note 5)
LMC6574AI LMC6574BI
LMC6572AI LMC6572BI
Units
Limit
(Note 6)
30
Limit
(Note 6)
30
V+ 2.7V and 3V
(Note 8)
90
V/ms
Min
MHz
Deg
dB
=
SR
Slew Rate
10
10
V+ 3V
0.22
60
=
GBW
φm
Gain-Bandwidth Product
Phase Margin
Gm
Gain Margin
12
Amp-to-Amp Isolation
Input-Referred
(Note 9)
=
120
45
dB
√
nV/ Hz
en
in
F
1 kHz
=
Voltage Noise
VCM 1V
=
√
pA/ Hz
Input-Referred
F
1 kHz
0.002
www.national.com
4
2.7V AC Electrical Characteristics (Continued)
+
−
+
=
=
= = =
>
0V, VCM VO V /2 and RL 1 MΩ. Bold-
Unless otherwise specified, all limits guaranteed for TJ 25˚C, V
2.7V, V
face limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Typ
(Note 5)
LMC6574AI LMC6574BI
LMC6572AI LMC6572BI
Units
Limit
Limit
(Note 6)
(Note 6)
Current Noise
Total Harmonic Distortion
=
=
T.H.D.
F
10 kHz, AV −2
0.05
%
=
=
RL 10 kΩ, VO 1.0 VPP
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in-
tended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: Human body model, 1.5 kΩ in series with 100 pF.
Note 3: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150˚C.
Note 4: The maximum power dissipation is
a
function of
T , θ , and T . The maximum allowable power dissipation at any ambient temperature is
J(Max) JA A
=
P
(T
J(Max)
− T )/θ . All numbers apply for packages soldered directly into a PC board.
D
A
JA
Note 5: Typical values represent the most likely parametric norm.
Note 6: All limits are guaranteed by testing or statistical analysis.
+
=
=
1.5V and R connected to 1.5V. For Sourcing tests, 1.5V ≤ V ≤ 2.5V. For Sinking tests, 0.5V ≤ V ≤ 1.5V.
Note 7:
V
3V, V
CM
L
O
O
Note 8: Connected as Voltage Follower with 1.0V step input. Number specified is the slower of the positive and negative slew rates.
+
=
=
=
2 V
O PP
Note 9: Input referred, V
3V and R
100 kΩ connected to 1.5V. Each amp excited in turn with 1 KHz to produce V
.
L
=
=
Typical Performance Characteristics VS +3V, TA 25˚C, Unless otherwise specified
Supply Current vs
Supply Voltage (Dual Package)
Input Current vs
Temperature
Sourcing Current vs
Output Voltage
DS011934-18
DS011934-19
DS011934-20
Sinking Current vs
Output Voltage
Output Voltage Swing vs
Supply Voltage
Input Voltage Noise vs
Frequency
DS011934-23
DS011934-21
DS011934-22
5
www.national.com
=
=
Typical Performance Characteristics VS +3V, TA 25˚C, Unless otherwise specified (Continued)
Crosstalk Rejection vs
Frequency
Positive PSRR vs
Frequency
Negative PSRR vs
Frequency
DS011934-24
DS011934-25
DS011934-26
CMRR vs Frequency
Input Voltage vs
Output Voltage (VS
Open Loop Frequency
Response
=
±
1.5)
DS011934-27
DS011934-28
DS011934-29
Open Loop Frequency
Response vs Temperature
Maximum Output Swing
vs Frequency
ZOUT vs Frequency
DS011934-32
DS011934-30
DS011934-31
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6
=
=
Typical Performance Characteristics VS +3V, TA 25˚C, Unless otherwise specified (Continued)
Slew Rate
vs Supply Voltage
Non-Inverting Large Signal
Pulse Response
Non-Inverting Small Signal
Pulse Response
DS011934-34
DS011934-35
DS011934-33
Inverting Large Signal
Pulse Response
Inverting Small Signal
Pulse Response
Stability
vs Capacitive Load
DS011934-36
DS011934-37
DS011934-38
Stability
Stability
Stability
vs Capacitive Load
vs Capacitive Load
vs Capacitive Load
DS011934-39
DS011934-40
DS011934-41
7
www.national.com
=
=
Typical Performance Characteristics VS +3V, TA 25˚C, Unless otherwise specified (Continued)
Bandwidth vs
Capacitive Load
Capacitive Load
vs Phase Margin
Capacitive Load
vs Gain Margin
DS011934-45
DS011934-46
DS011934-44
Applications Hints
1.0 LOW VOLTAGE AMPLIFIER TOPOLOGY
The LMC6574/2 incorporates a novel op-amp design topol-
ogy that enables it to maintain rail-to-rail output swing even
when driving a large load. Instead of relying on a push-pull
unity gain output buffer stage, the output stage is taken di-
rectly from the internal integrator, which provides both low
output impedance and large gain. Special feed-forward com-
pensation design techniques are incorporated to maintain
stability over a wider range of operating conditions than tra-
ditional micropower op-amps. These features make the
LMC6574/2 both easier to design with, and provide higher
speed than products typically found in this ultra-low power
class.
DS011934-6
FIGURE 1. Cancelling the Effect of Input Capacitance
2.0 COMPENSATING FOR INPUT CAPACITANCE
3.0 CAPACITIVE LOAD TOLERANCE
It is quite common to use large values of feedback resis-
tance for amplifiers with ultra-low input current, like the
LMC6574/2.
Direct capacitive loading will reduce the phase margin of
many op-amps. A pole in the feedback loop is created by the
combination of the op-amp’s output impedance and the ca-
pacitive load. This pole induces phase lag at the unity-gain
crossover frequency of the amplifier resulting in either an os-
cillatory or underdamped pulse response. With a few exter-
nal components, op amps can easily indirectly drive capaci-
tive loads, as shown in Figure 2.
Although the LMC6574/2 is highly stable over a wide range
of operating conditions, a large feedback resistor will react
even with small values of capacitance at the input of the
op-amp to reduce phase margin. The capacitance at the in-
put of the op-amp comes from transducers, photodiodes and
circuit board parasitics.
The effect of input capacitance can be compensated for by
adding a capacitor, Cf, around the feedback resistors (as in
Figure 1) such that:
or
R1 CIN ≤ R2 Cf
Since it is often difficult to know the exact value of CIN, Cf can
be experimentally adjusted so that the desired pulse re-
sponse is achieved. Refer to the LMC660 and LMC662 for a
more detailed discussion on compensating for input capaci-
tance.
When high input impedances are demanded, guarding of the
LMC6574/2 is suggested. Guarding input lines will not only
reduce leakage, but lowers stray input capacitance as well.
(See Printed-Circuit-Board Layout for High Impedance
Work).
DS011934-7
FIGURE 2. LMC6574/2 Noninverting Gain of 10
Amplifier, Compensated to Handle Capacitive Loads
In the circuit of Figure 2, R1 and C1 serve to counteract the
loss of phase margin by feeding the high frequency compo-
www.national.com
8
Applications Hints (Continued)
nent of the output signal back to the amplifier’s inverting in-
put, thereby preserving phase margin in the overall feedback
loop.
4.0 PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC6574/2, typically less
than 20 fA, it is essential to have an excellent layout. Fortu-
nately, the techniques of obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even though it may sometimes appear accept-
ably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
DS011934-9
Inverting Amplifier
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6574/2’s inputs and
the terminals of capacitors, diodes, conductors, resistors, re-
lay terminals, etc. connected to the op-amp’s inputs, as in
Figure 3. To have a significant effect, guard rings should be
placed on both the top and bottom of the PC board. This PC
foil must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 1012Ω, which is nor-
mally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of the input. This
would cause a 250 times degradation from the LMC6574/2’s
actual performance. However, if a guard ring is held within
5 mV of the inputs, then even a resistance of 1011Ω would
cause only 0.05 pA of leakage current. See Figure 4 for typi-
cal connections of guard rings for standard op-amp
configurations.
DS011934-10
Non-Inverting Amplifier
DS011934-11
Follower
FIGURE 4. Typical Connections of Guard Rings
The designer should be aware that when it is inappropriate
to lay out a PC board for the sake of just a few circuits, there
is another technique which is even better than a guard ring
on a PC board: Don’t insert the amplifier’s input pin into the
board at all, but bend it up in the air and use only air as an in-
sulator. Air is an excellent insulator. In this case you may
have to forego some of the advantages of PC board con-
struction, but the advantages are sometimes well worth the
effort of using point-to-point up-in-the-air wiring. See Figure
5.
DS011934-8
FIGURE 3. Example of Guard Ring in P.C. Board
Layout
DS011934-12
(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board).
FIGURE 5. Air Wiring
9
www.national.com
Applications Hints (Continued)
5.0 SPICE MACROMODEL
A spice macromodel is available for the LMC6574/2. This
model includes accurate simulation of:
•
•
•
•
•
input common-mode voltage range
frequency and transient response
GBW dependence on loading conditions
quiescent and dynamic supply current
output swing dependence on loading conditions
and many more characteristics as listed on the macromodel
disk.
DS011934-15
Contact your local National Semiconductor sales office to
obtain an operational amplifier spice model library disk.
FIGURE 8. 1 Hz Square Wave Oscillator
Typical Single-Supply Applications
DS011934-13
FIGURE 6. Low-Power Two-Op-Amp
Instrumentation Amplifier
DS011934-16
FIGURE 9. Adder/Subtractor Circuit
DS011934-14
FIGURE 7. Sample and Hold
DS011934-17
FIGURE 10. Low Pass Filter
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10
Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin Small Outline Package
Order Package Number LMC6572AIM or LMC6572BIM
NS Package Number M08A
14-Pin Small Outline Package
Order Package Number LMC6574AIM or LMC6574BIM
NS Package Number M14A
11
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Lead Mini-Small Outline Molded Package, JEDEC
Order Number LMC6572BIMM or LMC6572BIMMX
NS Package Number MUA08A
8-Pin Molded Dual-In-Line Package
Order Number LMC6572AIN or LMC6572BIN
NS Package Number N08E
www.national.com
12
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Pin Molded Dual-In-Line Package
Order Number LMC6574AIN or LMC6574BIN
NS Package Number N14A
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COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Tel: 1-800-272-9959
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