概述
规格参数
数据手册LMC662EM 概述
CMOS Dual Operational Amplifier CMOS双路运算放大器 运算放大器
LMC662EM 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | SOIC | 包装说明： | SOP, SOP8,.25 |
| 针数： | 8 | Reach Compliance Code： | unknown |
| ECCN代码： | EAR99 | HTS代码： | 8542.33.00.01 |
| 风险等级： | 5.45 | 放大器类型： | OPERATIONAL AMPLIFIER |
| 架构： | VOLTAGE-FEEDBACK | 最大平均偏置电流 (IIB)： | 0.00006 µA |
| 25C 时的最大偏置电流 (IIB)： | 0.00006 µA | 最小共模抑制比： | 63 dB |
| 标称共模抑制比： | 83 dB | 频率补偿： | YES |
| 最大输入失调电压： | 6500 µV | JESD-30 代码： | R-PDSO-G8 |
| JESD-609代码： | e0 | 长度： | 4.9 mm |
| 低-偏置： | YES | 低-失调： | NO |
| 微功率： | YES | 负供电电压上限： | -8 V |
| 标称负供电电压 (Vsup)： | 功能数量： | 2 | |
| 端子数量： | 8 | 最高工作温度： | 125 °C |
| 最低工作温度： | -40 °C | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装等效代码： | SOP8,.25 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 电源： | 5/15 V |
| 认证状态： | Not Qualified | 座面最大高度： | 1.75 mm |
| 最小摆率： | 0.8 V/us | 标称压摆率： | 1.1 V/us |
| 子类别： | Operational Amplifier | 最大压摆率： | 1.9 mA |
| 供电电压上限： | 8 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | AUTOMOTIVE | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 标称均一增益带宽： | 1400 kHz | 最小电压增益： | 50000 |
| 宽度： | 3.9 mm | Base Number Matches： | 1 |
LMC662EM 数据手册
通过下载LMC662EM数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载April 1998
LMC662
CMOS Dual Operational Amplifier
n Ultra low input bias current: 2 fA
General Description
n Input common-mode range includes V−
n Operating range from +5V to +15V supply
The LMC662 CMOS Dual operational amplifier is ideal for
operation from a single supply. It operates from +5V to +15V
and features rail-to-rail output swing in addition to an input
common-mode range that includes ground. Performance
limitations that have plagued CMOS amplifiers in the past
are not a problem with this design. Input VOS, drift, and
broadband noise as well as voltage gain into realistic loads
(2 kΩ and 600Ω) are all equal to or better than widely ac-
cepted bipolar equivalents.
=
n ISS 400 µA/amplifier; independent of V+
n Low distortion: 0.01% at 10 kHz
n Slew rate: 1.1 V/µs
n Available in extended temperature range (−40˚C to
+125˚C); ideal for automotive applications
n Available to a Standard Military Drawing specification
This chip is built with National’s advanced Double-Poly
Silicon-Gate CMOS process.
Applications
n High-impedance buffer or preamplifier
n Precision current-to-voltage converter
n Long-term integrator
See the LMC660 datasheet for a Quad CMOS operational
amplifier with these same features.
n Sample-and-hold circuit
n Peak detector
n Medical instrumentation
n Industrial controls
Features
n Rail-to-rail output swing
n Specified for 2 kΩ and 600Ω loads
n High voltage gain: 126 dB
n Low input offset voltage: 3 mV
n Low offset voltage drift: 1.3 µV/˚C
n Automotive sensors
Connection Diagram
8-Pin DIP/SO
DS009763-1
Ordering Information
Package
Temperature Range
NSC
Transport
Media
Drawing
Military
Extended
Industrial Commercial
8-Pin
LMC662AMJ/883
J08A
M08A
N08E
Rail
Ceramic DIP
8-Pin
LMC662EM LMC662AIM LMC662CM
LMC662EN LMC662AIN LMC662CN
Rail,
Tape and Reel
Rail
Small Outline
8-Pin
Molded DIP
8-Pin
Side Brazed
Ceramic DIP
LMC662AMD
D08C
Rail
© 1999 National Semiconductor Corporation
DS009763
www.national.com
Absolute Maximum Ratings (Note 3)
ESD Tolerance (Note 8)
1000V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings(Note 3)
Temperature Range
LMC662AMJ/883,
LMC662AMD
±
Differential Input Voltage
Supply Voltage (V+ − V−)
Output Short Circuit to V+
Output Short Circuit to V−
Lead Temperature
Supply Voltage
16V
−55˚C ≤ TJ ≤ +125˚C
−40˚C ≤ TJ ≤ +85˚C
0˚C ≤ TJ ≤ +70˚C
−40˚C ≤ TJ ≤ +125˚C
4.75V to 15.5V
(Note 12)
(Note 1)
LMC662AI
LMC662C
LMC662E
(Soldering, 10 sec.)
260˚C
Supply Voltage Range
Power Dissipation
Thermal Resistance (θJA) (Note 11)
8-Pin Ceramic DIP
8-Pin Molded DIP
8-Pin SO
Storage Temp. Range
Voltage at Input/Output Pins
Current at Output Pin
Current at Input Pin
−65˚C to +150˚C
(V+) +0.3V, (V−) −0.3V
(Note 10)
±
18 mA
100˚C/W
101˚C/W
165˚C/W
100˚C/W
±
5 mA
Current at Power Supply Pin
Power Dissipation
35 mA
(Note 2)
150˚C
8-Pin Side Brazed Ceramic DIP
Junction Temperature
DC Electrical Characteristics
+
=
=
Unless otherwise specified, all limits guaranteed for TJ 25˚C. Boldface limits apply at the temperature extremes. V
5V,
Units
V− 0V, VCM 1.5V, VO 2.5V and RL 1M unless otherwise specified.
=
=
=
>
Parameter
Conditions
Typ
LMC662AMJ/883 LMC662AI LMC662C LMC662E
(Note 4)
LMC662AMD
Limit
Limit
(Note 4)
3
Limit
(Note 4)
6
Limit
(Note 4)
6
(Notes 4, 9)
Input Offset Voltage
1
3
mV
max
3.5
3.3
6.3
6.5
Input Offset Voltage
Average Drift
1.3
µV/˚C
Input Bias Current
0.002
0.001
20
100
20
pA
max
pA
4
2
2
1
60
60
Input Offset Current
100
max
TeraΩ
dB
>
Input Resistance
Common Mode
1
0V ≤ VCM ≤ 12.0V
83
70
68
70
68
63
62
63
60
V+ 15V
min
dB
=
Rejection Ratio
Positive Power Supply
Rejection Ratio
5V ≤ V+ ≤ 15V
83
70
70
63
63
=
VO 2.5V
68
68
62
60
min
dB
Negative Power Supply
Rejection Ratio
0V ≤ V− ≤ −10V
94
84
84
74
74
82
83
73
70
min
V
Input Common-Mode
Voltage Range
V+ 5V & 15V
=
−0.4
V+ − 1.9
2000
500
−0.1
0
−0.1
0
−0.1
0
−0.1
0
For CMRR ≥ 50 dB
max
V
V+ − 2.3
V+ − 2.6
400
300
180
70
V+ − 2.3
V+ − 2.5
440
400
180
120
220
200
100
60
V+ − 2.3
V+ − 2.4
300
200
90
V+ − 2.3
V+ − 2.6
200
100
90
min
V/mV
min
V/mV
min
V/mV
min
V/mV
min
=
Large Signal
Voltage Gain
RL 2 kΩ (Note 5)
Sourcing
Sinking
80
40
=
RL 600Ω (Note 5)
1000
200
150
100
35
150
100
50
100
75
Sourcing
Sinking
50
250
40
20
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2
DC Electrical Characteristics (Continued)
+
=
=
Unless otherwise specified, all limits guaranteed for TJ 25˚C. Boldface limits apply at the temperature extremes. V
5V,
Units
V− 0V, VCM 1.5V, VO 2.5V and RL 1M unless otherwise specified.
=
=
=
>
Parameter
Conditions
Typ
(Note 4)
LMC662AMJ/883 LMC662AI LMC662C LMC662E
LMC662AMD
Limit
(Notes 4, 9)
4.82
4.77
0.15
0.19
4.41
4.24
0.50
0.63
14.50
14.40
0.35
0.43
13.35
13.02
1.16
1.42
16
Limit
(Note 4)
4.82
4.79
0.15
0.17
4.41
4.31
0.50
0.56
14.50
14.44
0.35
0.40
13.35
13.15
1.16
1.32
16
Limit
(Note 4)
4.78
4.76
0.19
0.21
4.27
4.21
0.63
0.69
14.37
14.32
0.44
0.48
12.92
12.76
1.45
1.58
13
Limit
(Note 4)
4.78
4.70
0.19
0.25
4.27
4.10
0.63
0.75
14.37
14.25
0.44
0.55
12.92
12.60
1.45
1.75
13
V+ 5V
4.87
0.10
4.61
0.30
14.63
0.26
13.90
0.79
22
V
min
V
=
Output Swing
+
=
RL 2 kΩ to V /2
max
V
V+ 5V
=
+
=
RL 600Ω to V /2
min
V
max
V
V+ 15V
=
+
=
RL 2 kΩ to V /2
min
V
max
V
V+ 15V
=
+
=
RL 600Ω to V /2
min
V
max
mA
min
mA
min
mA
min
mA
min
mA
max
=
Sourcing, VO 0V
Output Current
V+ 5V
12
14
11
9
=
=
Sinking, VO 5V
21
16
16
13
13
12
14
11
9
=
Output Current
Sourcing, VO 0V
40
19
28
23
23
V+ 15V
19
25
21
15
=
=
Sinking, VO 13V
39
19
28
23
23
(Note 12)
19
24
20
15
Supply Current
Both Amplifiers
0.75
1.3
1.3
1.6
1.6
=
VO 1.5V
1.8
1.5
1.8
1.9
AC Electrical Characteristics
+
=
=
5V,
Unless otherwise specified, all limits guaranteed for TJ 25˚C. Boldface limits apply at the temperature extremes. V
V− 0V, VCM 1.5V, VO 2.5V and RL 1M unless otherwise specified.
=
=
=
>
Parameter
Conditions
Typ
(Note
4)
LMC662AMJ/883
LMC662AMD
Limit
LMC662AI
LMC662C
LMC662E
Units
Limit
(Note 4)
0.8
Limit
(Note 4)
0.8
Limit
(Note 4)
0.8
(Notes 4, 9)
0.8
Slew Rate
(Note 6)
1.1
V/µs
min
MHz
Deg
dB
0.5
0.6
0.7
0.4
Gain-Bandwidth Product
Phase Margin
1.4
50
Gain Margin
17
Amp-to-Amp Isolation
Input-Referred Voltage Noise
(Note 7)
130
22
dB
=
=
=
F
F
F
1 kHz
1 kHz
10 kHz, AV −10
Input-Referred Current Noise
Total Harmonic Distortion
0.0002
=
=
=
RL 2 kΩ, VO 8 VPP
0.01
%
V+ 15V
=
3
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AC Electrical Characteristics (Continued)
Note 1: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts
±
can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of 30 mA over long term may adversely affect reliability.
=
D
Note 2: The maximum power dissipation is a function of T
(T –T )/θ
, θ , and T . The maximum allowable power dissipation at any ambient temperature is P
J(max) JA
A
.
JA
J(max)
A
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is in-
tended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed.
Note 4: Typical values represent the most likely parametric norm. Limits are guaranteed by testing or correlation.
+
=
=
=
7.5V and R connected to 7.5V. For Sourcing tests, 7.5V ≤ V ≤ 11.5V. For Sinking tests, 2.5V ≤ V ≤ 7.5V.
Note 5:
Note 6:
V
V
15V, V
CM
L
O
O
+
15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
+
+
=
=
=
13 V
O PP
Note 7: Input referred. V
15V and R
10 kΩ connected to V /2. Each amp excited in turn with 1 kHz to produce V
.
L
Note 8: Human body model, 1.5 kΩ in series with 100 pF.
Note 9: A military RETS electrical test specification is available on request. At the time of printing, the LMC662AMJ/883 RETS spec complied fully with the boldface
limits in this column. The LMC662AMJ/883 may also be procured to a Standard Military Drawing specification.
=
Note 10: For operating at elevated temperatures the device must be derated based on the thermal resistance θ with P
(T –T )/θ .
J A JA
JA
D
Note 11: All numbers apply for packages soldered directly into a PC board.
+
+
Note 12: Do not connect output to V when V is greater than 13V or reliability may be adversely affected.
=
=
±
Typical Performance Characteristics VS
7.5V, TA 25˚C unless otherwise specified
Supply Current vs
Supply Voltage
Input Bias Current
Offset Voltage
DS009763-26
DS009763-25
DS009763-24
Output Characteristics
Current Sinking
Output Characteristics
Current Sourcing
Input Voltage Noise
vs Frequency
DS009763-27
DS009763-28
DS009763-29
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4
=
=
±
Typical Performance Characteristics VS
7.5V, TA 25˚C unless otherwise specified (Continued)
CMRR vs Frequency
Open-Loop Frequency
Response
Frequency Response vs
Capacitive Load
DS009763-30
DS009763-31
DS009763-32
Non-Inverting Large Signal
Pulse Response
Stability vs
Capacitive Load
Stability vs
Capacitive Load
DS009763-33
DS009763-34
DS009763-35
Note: Avoid resistive loads of less than 500Ω,
as they may cause instability.
Note: Avoid resistive loads of less than 500Ω,
as they may cause instability.
Application Hints
AMPLIFIER TOPOLOGY
The topology chosen for the LMC662, shown in Figure 1, is
unconventional (compared to general-purpose op amps) in
that the traditional unity-gain buffer output stage is not used;
instead, the output is taken directly from the output of the in-
tegrator, to allow rail-to-rail output swing. Since the buffer
traditionally delivers the power to the load, while maintaining
high op amp gain and stability, and must withstand shorts to
either rail, these tasks now fall to the integrator.
As a result of these demands, the integrator is a compound
affair with an embedded gain stage that is doubly fed forward
(via Cf and Cff) by a dedicated unity-gain compensation
driver. In addition, the output portion of the integrator is a
push-pull configuration for delivering heavy loads. While
sinking current the whole amplifier path consists of three
gain stages with one stage fed forward, whereas while
sourcing the path contains four gain stages with two fed
forward.
DS009763-4
FIGURE 1. LMC662 Circuit Topology (Each Amplifier)
The large signal voltage gain while sourcing is comparable
to traditional bipolar op amps, even with a 600Ω load. The
gain while sinking is higher than most CMOS op amps, due
to the additional gain stage; however, under heavy load
(600Ω) the gain will be reduced as indicated in the Electrical
Characteristics.
5
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the following value of feedback capacitor is recommended:
Application Hints (Continued)
COMPENSATING INPUT CAPACITANCE
The high input resistance of the LMC662 op amps allows the
use of large feedback and source resistor values without los-
ing gain accuracy due to loading. However, the circuit will be
especially sensitive to its layout when these large-value re-
sistors are used.
If
Every amplifier has some capacitance between each input
and AC ground, and also some differential capacitance be-
tween the inputs. When the feedback network around an
amplifier is resistive, this input capacitance (along with any
additional capacitance due to circuit board traces, the
socket, etc.) and the feedback resistors create a pole in the
feedback path. In the following General Operational Amplifier
Circuit, Figure 2, the frequency of this pole is
the feedback capacitor should be:
Note that these capacitor values are usually significantly
smaller than those given by the older, more conservative for-
mula:
where CS is the total capacitance at the inverting input, in-
cluding amplifier input capacitance and any stray capaci-
tance from the IC socket (if one is used), circuit board traces,
etc., and RP is the parallel combination of RF and RIN. This
formula, as well as all formulae derived below, apply to in-
verting and non-inverting op-amp configurations.
When the feedback resistors are smaller than a few kΩ, the
frequency of the feedback pole will be quite high, since CS is
generally less than 10 pF. If the frequency of the feedback
pole is much higher than the “ideal” closed-loop bandwidth
(the nominal closed-loop bandwidth in the absence of CS),
the pole will have a negligible effect on stability, as it will add
only a small amount of phase shift.
DS009763-6
However, if the feedback pole is less than approximately 6 to
10 times the “ideal” −3 dB frequency, a feedback capacitor,
CF, should be connected between the output and the invert-
ing input of the op amp. This condition can also be stated in
terms of the amplifier’s low-frequency noise gain: To main-
tain stability, a feedback capacitor will probably be needed if
C
consists of the amplifier’s input capacitance plus any stray capacitance
S
from the circuit board and socket. C compensates for the pole caused by
F
C
and the feedback resistor.
S
FIGURE 2. General Operational Amplifier Circuit
Using the smaller capacitors will give much higher band-
width with little degradation of transient response. It may be
necessary in any of the above cases to use a somewhat
larger feedback capacitor to allow for unexpected stray ca-
pacitance, or to tolerate additional phase shifts in the loop, or
excessive capacitive load, or to decrease the noise or band-
width, or simply because the particular circuit implementa-
tion needs more feedback capacitance to be sufficiently
stable. For example, a printed circuit board’s stray capaci-
tance may be larger or smaller than the breadboard’s, so the
actual optimum value for CF may be different from the one
estimated using the breadboard. In most cases, the value of
CF should be checked on the actual circuit, starting with the
computed value.
where
is the amplifier’s low-frequency noise gain and GBW is the
amplifier’s gain bandwidth product. An amplifier’s
low-frequency noise gain is represented by the formula
CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LMC662 may oscillate when
its applied load appears capacitive. The threshold of oscilla-
tion varies both with load and circuit gain. The configuration
most sensitive to oscillation is a unity-gain follower. See the
Typical Performance Characteristics.
regardless of whether the amplifier is being used in an invert-
ing or non-inverting mode. Note that a feedback capacitor is
more likely to be needed when the noise gain is low and/or
the feedback resistor is large.
If the above condition is met (indicating a feedback capacitor
will probably be needed), and the noise gain is large enough
that:
The load capacitance interacts with the op amp’s output re-
sistance to create an additional pole. If this pole frequency is
sufficiently low, it will degrade the op amp’s phase margin so
that the amplifier is no longer stable at low gains. As shown
in Figure 3, the addition of a small resistor (50Ω to 100Ω) in
series with the op amp’s output, and a capacitor (5 pF to 10
pF) from inverting input to output pins, returns the phase
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6
ures 6, 7, 8 for typical connections of guard rings for stan-
dard op-amp configurations. If both inputs are active and at
high impedance, the guard can be tied to ground and still
provide some protection; see Figure 9.
Application Hints (Continued)
margin to
a
safe value without interfering with
lower-frequency circuit operation. Thus, larger values of ca-
pacitance can be tolerated without oscillation. Note that in all
cases, the output will ring heavily when the load capacitance
is near the threshold for oscillation.
DS009763-5
FIGURE 3. Rx, Cx Improve Capacitive Load Tolerance
Capacitive load driving capability is enhanced by using a pull
up resistor to V+ Figure 4. Typically a pull up resistor con-
ducting 500 µA or more will significantly improve capacitive
load responses. The value of the pull up resistor must be de-
termined based on the current sinking capability of the ampli-
fier with respect to the desired output swing. Open loop gain
of the amplifier can also be affected by the pull up resistor
(see Electrical Characteristics).
DS009763-16
FIGURE 5. Example, using the LMC660,
of Guard Ring in P.C. Board Layout
DS009763-23
FIGURE 4. Compensating for Large Capacitive Loads
with a Pull Up Resistor
DS009763-17
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
FIGURE 6. Guard Ring Connections: Inverting
Amplifier
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC662, typically less
than 0.04 pA, it is essential to have an excellent layout. For-
tunately, the techniques for obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even though it may sometimes appear accept-
ably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
DS009763-18
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC662’s inputs and the
terminals of capacitors, diodes, conductors, resistors, relay
terminals, etc. connected to the op-amp’s inputs. See Figure
5. To have a significant effect, guard rings should be placed
on both the top and bottom of the PC board. This PC foil
must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 1012Ω, which is nor-
mally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of an input. This
would cause a 100 times degradation from the LMC662’s ac-
tual performance. However, if a guard ring is held within
5 mV of the inputs, then even a resistance of 1011Ω would
cause only 0.05 pA of leakage current, or perhaps a minor
(2:1) degradation of the amplifier’s performance. See Fig-
FIGURE 7. Guard Ring Connections: Non-Inverting
Amplifier
DS009763-19
FIGURE 8. Guard Ring Connections: Follower
7
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BIAS CURRENT TESTING
Application Hints (Continued)
The test method of Figure 11 is appropriate for bench-testing
bias current with reasonable accuracy. To understand its op-
eration, first close switch S2 momentarily. When S2 is
opened, then
DS009763-20
FIGURE 9. Guard Ring Connections: Howland Current
Pump
The designer should be aware that when it is inappropriate
to lay out a PC board for the sake of just a few circuits, there
is another technique which is even better than a guard ring
on a PC board: Don’t insert the amplifier’s input pin into the
board at all, but bend it up in the air and use only air as an in-
sulator. Air is an excellent insulator. In this case you may
have to forego some of the advantages of PC board con-
struction, but the advantages are sometimes well worth the
effort of using point-to-point up-in-the-air wiring. See Figure
10.
DS009763-22
FIGURE 11. Simple Input Bias Current Test Circuit
A suitable capacitor for C2 would be a 5 pF or 10 pF silver
mica, NPO ceramic, or air-dielectric. When determining the
magnitude of Ib−, the leakage of the capacitor and socket
must be taken into account. Switch S2 should be left shorted
most of the time, or else the dielectric absorption of the ca-
pacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2
shorted)
where Cx is the stray capacitance at the + input.
DS009763-21
(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board.)
FIGURE 10. Air Wiring
www.national.com
8
Typical Single-Supply Applications (V+ 5.0 VDC
)
=
Additional single-supply applications ideas can be found in
the LM358 datasheet. The LMC662 is pin-for-pin compatible
with the LM358 and offers greater bandwidth and input resis-
tance over the LM358. These features will improve the per-
formance of many existing single-supply applications. Note,
however, that the supply voltage range of the LM662 is
smaller than that of the LM358.
Sine-Wave Oscillator
Low-Leakage Sample-and-Hold
DS009763-15
DS009763-8
Instrumentation Amplifier
Oscillator frequency is determined by R1, R2, C1, and C2:
=
fOSC 1/2πRC
=
=
=
=
where R R1 R2 and C C1 C2.
This circuit, as shown, oscillates at 2.0 kHz with
peak-to-peak output swing of 4.5V
a
1 Hz Square-Wave Oscillator
DS009763-7
DS009763-9
Power Amplifier
For good CMRR over temperature, low drift resistors should
be used. Matching of R3 to R6 and R4 to R7 affects CMRR.
Gain may be adjusted through R2. CMRR may be adjusted
through R7.
DS009763-10
9
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Typical Single-Supply Applications (V+ 5.0 VDC) (Continued)
=
10 Hz Bandpass Filter
10 Hz High-Pass Filter
DS009763-12
=
=
f
d
10 Hz
0.895
c
DS009763-11
=
=
f
Q
10 Hz
2.1
=
Gain
1
O
2 dB passband ripple
=
Gain −8.8
1 Hz Low-Pass Filter
(Maximally Flat, Dual Supply Only)
High Gain Amplifier with
Offset Voltage Reduction
DS009763-13
DS009763-14
=
Gain −46.8
Output offset voltage reduced to the level of the input offset voltage of the
bottom amplifier (typically 1 mV).
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10
Physical Dimensions inches (millimeters) unless otherwise noted
Hermatic Dual-In-Line Pkg. (D)
Order Number LMC662AMD
NS Package Number D08C
Ceramic Dual-In-Line Pkg. (J)
Order Number LMC662AMJ/883
NS Package Number J08A
11
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Small Outline Dual-In-Line Pkg. (M)
Order Number LMC662AIM, LMC662CM or LMC662EM
NS Package Number M08A
Molded Dual-In-Line Pkg. (N)
Order Number LMC662AIN, LMC662CN or LMC662EN
NS Package Number N08E
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12
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
LMC662EM 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| LMC662EMX | TI | DUAL OP-AMP, 6500uV OFFSET-MAX, 1.4MHz BAND WIDTH, PDSO8, SO-8 | 获取价格 |
|
| LMC662EN | NSC | CMOS Dual Operational Amplifier | 获取价格 |
|
| LMC662EN | TI | DUAL OP-AMP, 6500uV OFFSET-MAX, 1.4MHz BAND WIDTH, PDIP8, DIP-8 | 获取价格 |
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|
| LMC6681AIMX | NSC | Low Voltage, Rail-To-Rail Input and Output CMOS | 获取价格 |
|
| LMC6681AIN | NSC | Low Voltage, Rail-To-Rail Input and Output CMOS | 获取价格 |
|
| LMC6681B1MX | NSC | Low Voltage, Rail-To-Rail Input and Output CMOS | 获取价格 |
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| LMC6681BIM | NSC | Low Voltage, Rail-To-Rail Input and Output CMOS | 获取价格 |
|
| LMC6681BIMX | NSC | IC OP-AMP, 3000 uV OFFSET-MAX, 1.2 MHz BAND WIDTH, PDSO8, 0.150 INCH, PLASTIC, SOP-8, Operational Amplifier | 获取价格 |
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