LMC6684AIMX [NSC]
Low Voltage, Rail-To-Rail Input and Output CMOS; 低电压，轨至轨输入和输出CMOS
| 型号： | LMC6684AIMX |
| 厂家： | 
National Semiconductor |
| 描述： | Low Voltage, Rail-To-Rail Input and Output CMOS |
| 文件： | 总24页 (文件大小：752K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1995
LMC6681 Single/LMC6682 Dual/LMC6684 Quad
Low Voltage, Rail-To-Rail Input and Output CMOS
Amplifier with Powerdown
General Description
Features
The LMC6681/2/4 is a high performance operational ampli-
fier which can operate over a wide range of supply voltages,
with guaranteed specifications at 1.8V, 2.2V, 3V, 5V, and
10V.
(Typical unless otherwise noted)
n Guaranteed Specs at 1.8V, 2.2V, 3V, 5V, 10V
n Rail-to-Rail Input Common-Mode Voltage Range
n Rail-to-Rail Output Swing
The LMC6681/2/4 provides an input common-mode voltage
range that exceeds both supplies. The rail-to-rail output
swing of the amplifier assures maximum dynamic signal
range. This rail-to-rail performance of the amplifier, com-
bined with its high open-loop voltage gain makes it unique
among CMOS rail-to-rail amplifiers. The LMC6681/2/4 is an
excellent choice for circuits where the common-mode volt-
age range is a concern.
=
=
@
(within 10 mV of supply rail, VS 3V and RL 10 kΩ)
n Powerdown Mode IS OFF ≤ 1.5 µA/Amplifier
(Guaranteed at VS 1.8V, 2.2V, 3V, and 5V)
=
n Ultra Low Input Current 80 fA
=
=
n High Voltage Gain (VS 3V, RL 10 kΩ): 120 dB
n Unity Gain Bandwidth 1.2 MHz
Applications
n Battery Operated Circuits
n Sensor Amplifiers
The LMC6681/2/4 has a powerdown mode which can be
controlled externally. In this powerdown mode, the supply
current decreases from 700 µA per amplifier to less than 1
µA per amplifier. The LMC6684 has two powerdown options.
Each of the powerdown pins disables two amplifiers.
n Portable Communication Devices
n Medical Instrumentation
The LMC6681/2/4 has been designed specifically to improve
system performance in low voltage applications. The ampli-
fier’s 80 fA input current, 0.5 mV offset voltage, and 82 dB
CMRR maintain accuracy in battery-powered systems.
n Battery Monitoring Circuits
n Level Detectors, Sample-and-Hold Circuits
Connection Diagrams
8-Pin DIP/SO
14-Pin DIP/SO
DS012042-1
Top View
DS012042-2
Top View
16-Pin DIP/SO
DS012042-3
Top View
© 1999 National Semiconductor Corporation
DS012042
www.national.com
Ordering Information
Package
Temperature Range
Industrial, −40˚C to +85˚C
LMC6681AIN, LMC6681BIN
LMC6681AIM, LMC6681BIM
LMC6681AIMX, LMC6681B1MX
LMC6682AIN, LMC6682BIN
LMC6682AIM, LMC6682BIM
LMC6682AIMX, LMC6682BIMX
LMC6684AIN, LMC6684BIN
LMC6684AIM, LMC6684BIM
LMC6684AIMX, LMC6684BIMX
NSC
Drawing
N08E
M08A
M08A
N14A
M14A
M14A
N16A
M16A
M16A
Transport
Media
8-Pin Molded DIP
8-Pin Small Outline
Rails
Rails
Tape and Reel
Rails
14-Pin Molded DIP
14-Pin Small Outline
Rails
Tape and Reel
Rails
16-Pin Molded DIP
16-Pin Small Outline
Rails
Tape and Reel
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2
Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
1.8V ≤ VS ≤ 10V
Junction Temperature Range
LMC6681AI, LMC6681BI
LMC6682AI, LMC6682BI
LMC6684AI, LMC6684BI
−40˚C ≤ TJ ≤ +85˚C
−40˚C ≤ TJ ≤ +85˚C
−40˚C ≤ TJ ≤ +85˚C
ESD Tolerance (Note 2)
2 kV
±
Differential Input Voltage
Supply Voltage
Voltage at Input/Output Pin
Supply Voltage (V+ − V−)
(V+) +0.3V, (V−) −0.3V
Thermal Resistance (θJA
)
12V
N Package, 8-pin Molded DIP
M Package, 8-pin Surface Mount
N Package, 14-pin Molded DIP
M Package, 14-pin Surface Mount
N Package, 16-pin Molded DIP
M Package, 16-pin Surface Mount
108˚C/W
172˚C/W
88˚C/W
±
Current at Input Pin (Note 11)
Current at Output Pin (Note 3)
Current at Power Supply Pin
Lead Temp. (soldering, 10 sec.)
Storage Temperature Range
Junction Temperature (Note 4)
5 mA
±
30 mA
35 mA
126˚C/W
83˚C/W
260˚C
−65˚C to +150˚C
150˚C
114˚C/W
3V DC Electrical Characteristics
+
+
=
=
=
=
=
=
>
Unless otherwise specified, all limits guaranteed for TJ 25˚C, V
1 MΩ. Boldface limits apply at the temperature extremes (Note 16).
3.0V, V− 0V, VCM VO V /2, VPD 0.6V and RL
LMC6681AI
LMC6682AI
LMC6684AI
Limit
LMC6681BI
LMC6682BI
LMC6684BI
Limit
Typ
(Note 5)
Symbol
Parameter
Conditions
Units
(Note 6)
1
(Note 6)
3
VOS
Input Offset Voltage
0.5
1.5
mV
max
2.5
4.5
TCVOS
Input Offset Voltage
Average Drift
µV/˚C
IB
Input Current
(Note 12)
(Note 12)
0.08
0.04
20
10
20
10
pA max
pA max
Tera Ω
pF
IOS
Input Offset Current
Input Resistance
Input Capacitance
Common Mode
Rejection Ratio
Power Supply
>
RIN
CIN
CMRR
1
3
(Note 13)
82
82
70
65
65
62
dB
min
dB
±
±
2.5V
PSRR
VCM
1.5V ≤ VS
≤
70
65
+
=
=
Rejection Ratio
Input Common Mode
Voltage Range
VO V /2 VCM
65
62
min
V
>
CMRR 50 dB
3.23
−0.3
3.18
3.00
−0.18
0.00
10
3.18
3.00
−0.18
0.00
10
min
V
max
V/mV
V/mV
V
=
AV
VO
Large Signal
Voltage Gain
RL 600Ω (Notes 7, 12)
70
=
RL 10 kΩ (Notes 7, 12)
1000
2.87
12
12
+
=
Output Swing
RL 600Ω to V /2
2.70
2.58
0.3
2.70
2.58
0.3
min
V
0.15
2.95
0.05
2.99
0.01
0.42
2.85
2.79
0.15
0.21
2.94
2.91
0.04
0.05
0.42
2.85
2.79
0.15
0.21
2.94
2.91
0.04
0.05
max
V
+
=
RL 2 kΩ to V /2
min
V
max
V
+
=
RL 10 kΩ to V /2
min
V
max
3
www.national.com
3V DC Electrical Characteristics (Continued)
+
+
=
=
= = = =
3.0V, V− 0V, VCM VO V /2, VPD 0.6V and RL
>
Unless otherwise specified, all limits guaranteed for TJ 25˚C, V
1 MΩ. Boldface limits apply at the temperature extremes (Note 16).
LMC6681AI
LMC6682AI
LMC6684AI
Limit
(Note 6)
9.0
LMC6681BI
LMC6682BI
LMC6684BI
Limit
(Note 6)
9.0
Typ
(Note 5)
Symbol
Parameter
Conditions
Units
=
ISC
Output Short
Sourcing, VO 0V
20
12
mA
min
mA
min
mA
max
mA
max
mA
max
µA
Circuit Current
6.7
6.7
=
Sinking, VO 3V
6.0
6.0
4.5
4.5
IS ON
Supply Current
Single, LMC6681
0.7
1.4
2.8
0.5
0.5
1.0
1.13
1.13
=
when Powered ON
VCM 1.5V
1.36
1.36
Dual, LMC6682
2.26
2.26
=
VCM 1.5V
2.75
2.75
Quad, LMC6684
4.52
4.52
=
VCM 1.5V
5.42
5.42
IS OFF
Supply Current
Single, LMC6681
1.5
1.5
=
when Powered OFF
VPD 2.3V
2.1
2.1
max
µA
Dual, LMC6682
1.5
1.5
=
VPD 2.3V
2.1
2.1
max
µA
Quad, LMC6684
3.0.
3.0
=
VPD 2.3V
4.2
4.2
max
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4
1.8V and 2.2V DC Electrical Characteristics
+
=
=
=
=
=
=
Unless otherwise specified, all limits guaranteed for TJ 25˚C, V+ 1.8V and 2.2V, V− 0V, VCM VO V /2, VPD 0.4V
=
>
@
2.2V), VPD 0.3V ( 1.8V) and RL 1 MΩ. Boldface limits apply at the temperature extremes (Note 16).
@
(
LMC6681AI
LMC6681BI
Typ
LMC6682AI
LMC6682BI
Symbol
VOS
Parameter
Conditions
(Note 5)
LMC6684AI
LMC6684BI
Units
Limit
Limit
(Note 6)
10
(Note 6)
V+ 1.8V, VCM 1.5V
0.5
0.5
3
2
mV max
mV
=
=
Input Offset Voltage
V+ 2.2V, VCM 1.5V
6
=
=
3.8
7.8
max
TCVOS
Input Offset Voltage
Average Drift
V+ 2.2V
=
1.5
µV/˚C
IB
Input Current
V+ 2.2V (Note 12)
=
0.08
0.04
82
20
10
20
10
pA max
pA max
dB min
dB min
dB
V+ 2.2V (Note 12)
=
IOS
Input Offset Current
Common Mode
Rejection Ratio
Power Supply
CMRR
V+ 2.2V (Note 13)
=
60
60
V+ 1.8V (Note 13)
82
50
50
=
±
±
5V,
PSRR
VCM
1.1V ≤ VS
≤
82
70
65
+
=
=
Rejection Ratio
Input Common Mode
Voltage Range
VO V /2 VCM
65
62
min
V+ 2.2V
2.38
−0.15
1.98
2.2
0.0
1.8
0.0
2.0
1.88
0.2
0.32
1.6
1.44
0.2
0.32
1.1
1.32
2.2
2.7
4.4
5.3
1.5
2.7
1.5
2.7
3.0
5.4
2.2
0.0
1.8
0.0
2.0
1.88
0.2
0.32
1.6
1.44
0.2
0.32
1.1
1.32
2.2
2.7
4.4
5.3
1.5
2.7
1.5
2.7
3.0
5.4
V min
V max
V min
V max
V
=
>
CMRR 40 dB
V+ 1.8V
=
>
CMRR 40 dB
−0.10
2.15
V+ 2.2V
=
VO
Output Swing
+
=
RL 2 kΩ to V /2
min
0.05
1.75
0.05
0.7
V
max
V
V+ 1.8V
=
+
=
RL 2 kΩ to V /2
min
V
max
mA
IS ON
Supply Current
Single, LMC6681
=
when Powered ON
VCM 1.5V
max
mA
Dual, LMC6682
1.4
=
VCM 1.5V
max
mA
Quad, LMC6684
2.8
=
VCM 1.5V
max
µA
IS OFF
Supply Current
Single, LMC6681
0.5
=
when Powered OFF
VPD 1.5V
max
µA
Dual, LMC6682
0.5
=
VPD 1.5V
max
µA
Quad, LMC6684
1.0
=
VPD 1.5V
max
5
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5V DC Electrical Characteristics
+
+
=
=
= = = =
5.0V, V− 0V, VCM VO V /2, VPD 0.9V and RL
>
Unless otherwise specified, all limits guaranteed for TJ 25˚C, V
1 MΩ. Boldface limits apply at the temperature extremes (Note 16).
LMC6681AI
LMC6682AI
LMC6684AI
Limit
LMC6681BI
LMC6682BI
LMC6684BI
Limit
Typ
(Note 5)
Symbol
Parameter
Conditions
Units
(Note 6)
1
(Note 6)
3
=
VOS
Input Offset Voltage
VCM 1.5V
0.5
1.5
mV
max
2.5
4.5
TCVOS
Input Offset Voltage
Average Drift
µV/˚C
IB
Input Current
(Note 12)
(Note 12)
0.08
0.04
20
10
20
10
pA max
pA max
Tera Ω
pF
IOS
Input Offset Current
Input Resistance
Input Capacitance
Common Mode
Rejection Ratio
Power Supply Rejection
Ratio
>
RIN
CIN
CMRR
1
3
(Note 13)
82
82
70
65
65
62
dB
min
dB
±
±
2.5V
PSRR
VCM
1.5V ≤ VS
≤
70
65
+
=
=
VO V /2 VCM
65
62
min
V
>
Input Common Mode
Voltage Range
CMRR 50 dB
5.3
−0.3
4.9
0.05
0.8
1.5
3.0
0.5
0.5
1.0
5.18
5.00
−0.18
0.00
4.85
4.58
0.2
5.18
5.00
−0.18
0.00
4.85
4.58
0.2
min
V
max
V
+
=
VO
Output Swing
RL 2 kΩ to V /2
min
V
0.28
1.24
1.49
2.48
3.00
4.96
6.00
1.5
0.28
1.24
1.49
2.48
3.00
4.96
6.00
1.5
max
mA
max
mA
max
mA
max
µA
IS ON
Supply Current
Single, LMC6681
=
when Powered ON
VCM 1.5V
Dual, LMC6682
=
VCM 1.5V
Quad, LMC6684
=
VCM 1.5V
IS OFF
Supply Current
Single, LMC6681
=
when Powered OFF
VPD 4.3V
2.1
2.1
max
µA
Dual, LMC6682
1.5
1.5
=
VPD 4.3V
2.1
2.1
max
µA
Quad, LMC6684
3.0
3.0
=
VPD 4.3V
4.2
4.2
max
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6
10V DC Electrical Characteristics
+
+
=
=
=
=
=
=
Unless otherwise specified, all limits guaranteed for TJ 25˚C, V
10.0V, V− 0V, VCM VO V /2, VPD 1.2V and RL
>
1 MΩ. Boldface limits apply at the temperature extremes (Note 16).
LMC6681AI LMC6681BI
LMC6682AI LMC6682BI
Typ
(Note 5)
Symbol
Parameter
Conditions
LMC6684AI LMC6684BI
Units
Limit
(Note 6)
1.5
Limit
(Note 6)
3.5
=
VOS
Input Offset Voltage
VCM 1.5V
0.5
1.5
mV
max
3.0
5.0
TCVOS
Input Offset Voltage
Average Drift
µV/˚C
IB
Input Current
(Note 12)
(Note 12)
0.08
0.04
20
10
20
10
pA max
pA max
Tera Ω
pF
IOS
Input Offset Current
Input Resistance
Input Capacitance
Common Mode
>
RIN
CIN
CMRR
1
3
(Note 13)
82
82
65
62
65
62
dB
Rejection Ratio
min
dB
±
±
5V
PSRR
VCM
Positive Power Supply
Rejection Ratio
1.1V ≤ VS
≤
70
65
+
=
VO V /2
65
62
min
V
>
Input Common Mode
Voltage Range
CMRR 50 dB
10.30
−0.30
9.93
0.08
10.18
10.00
−0.18
0.00
9.7
9.58
0.3
0.42
25
10.18
10.00
−0.18
0.00
9.7
9.58
0.3
0.42
25
min
V
max
V
+
=
VO
Output Swing
RL 2 kΩ to V /2
min
V
max
V/mV
V/mV
mA
+
=
AV
Large Signal
Voltage Gain
Output Short Circuit
Current
RL 2 kΩ to V /2
Sourcing
Sinking
89
224
65
(Note 12)
25
25
=
ISC
Sourcing, VO 0V
30
30
(Note 14)
22
22
min
mA
=
Sinking, VO 10V
70
0.9
1.6
3.2
0.5
0.5
1.0
30
30
(Note 14)
22
22
min
mA
IS ON
Supply Current
Single, LMC6681
1.50
1.8
3.00
3.6
6.00
7.2
5
1.50
1.8
3.00
3.6
6.00
7.2
5
=
when Powered ON
VCM 1.5V
max
mA
Dual, LMC6682
=
VCM 1.5V
max
mA
Quad, LMC6684
=
VCM 1.5V
max
µA
IS OFF
Supply Current
Single, LMC6681
=
when Powered OFF
VPD 9.3V
7
7
max
µA
Dual, LMC6682
5
5
=
VPD 9.3V
7
7
max
µA
Quad, LMC6684
10
10
=
VPD 9.3V
14
14
max
7
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Powerdown DC Threshold Characteristics
Boldface limits apply at the temperature extremes (Note 16).
LMC6681AI, LMC6681BI
LMC6682AI, LMC6682BI
LMC6684AI, LMC6684BI
Symbol
Parameter
Conditions
Units
Min
Typ
Max
VPD, IL
Powerdown Voltage Input Low (Device
Powered ON; Amplifier meets all
specs in the datasheet tables)
V+ 2.2V
=
0.4
0.25
0.6
V
V
V
V
V
V
V
V
V− 0V
=
V+ 3V
=
V− 0V
0.45
0.9
=
V+ 5V
=
V− 0V
0.75
1.2
=
V+ 10V
=
V− 0V
1.05
=
VPD, IH
Powerdown Voltage Input High (Device
Powered OFF; Refer to DC Electrical
Characteristics for IS OFF specs)
V+ 2.2V
=
1.5
1.65
2.3
V− 0V
=
V+ 3V
=
V− 0V
2.45
4.3
=
V+ 5V
=
V− 0V
4.45
9.3
=
V+ 10V
=
V− 0V
9.45
=
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8
AC Electrical Characteristics
+
+
=
=
=
=
=
=
>
1
Unless otherwise specified, all limits guaranteed for TJ 25˚C, V
MΩ. Boldface limits apply at the temperature extremes (Note 16).
3V, V− 0V, VCM VO V /2, VPD 0.6V and RL
LMC6681AI
LMC6682AI
LMC6684AI
Limit
LMC6681BI
LMC6682BI
LMC6684BI
Limit
Typ
(Note 5)
Symbol
Parameter
Conditions
Units
(Note 6)
200
(Note 6)
200
tON
tOFF
SR
Time Delay for
(Note 15)
50
0.5
1.2
1.2
µs
µs
Device to Power ON
Time Delay for
(Note 15)
(Note 8)
2
2
Device to Power OFF
Slew Rate
0.7
0.55
0.7
0.7
0.55
0.7
V/µs
min
V+ 10V, (Note 10)
=
0.55
0.55
GBW
φm
Gain-Bandwidth Product
Phase Margin
1.2
50
MHz
Deg
dB
Gm
Gain Margin
12
Amp-to-Amp Isolation
Input-Referred
V+ 10V (Note 9)
=
130
32
dB
=
1 kHz
en
f
=
VCM 0.5V
Voltage Noise
=
in
Input-Referred
f
1 kHz
0.5
Current Noise
=
=
T.H.D.
Total Harmonic Distortion
f
1 kHz, AV +1
0.01
%
=
=
RL 10 kΩ, VO 2 VPP
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is in-
tended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the electrical characteristics.
Note 2: Human body model, 1.5 kΩ in series with 100 pF.
Note 3: Applies to both single-supply and split-supply operation. Continous short circuit operation at elevated ambient temperature can result in exceeding the maxi-
±
mum allowed junction temperature of 150˚C. Output current in excess of 30 mA over long term may adversely affect reliability.
=
Note 4: The maximum power dissipation is a function of T , θ , and T . The maximum allowable power dissipation at any ambient temperature is P
(T
J(max)
J (max) JA
A
D
− T )/θ . All numbers apply for packages soldered directly into a PC board.
A
JA
Note 5: Typical Values represent the most likely parametric norm.
Note 6: All limits are guaranteed by testing or statistical analysis.
+
=
=
0.5V. For sourcing and sinking, 0.5V ≤ V ≤ 2.5V.
Note 7:
Note 8:
V
3V, V
CM
O
+
=
V
3V. Connected as Voltage Follower with 2V step input, and the output is measured from 15%–85%. Number specified is the slower of the positive or
negative slew rates.
+
=
=
=
2 V
O PP
Note 9: Input referred, V
10V, and R
100 kΩ connected to 5V. Each amp excited in turn with 1 kHz to produce V
.
L
+
=
10V. Connected as voltage follower with 8V step Input, and output is measured from 15%–85%. Number specified is the slower of the positive or nega-
Note 10:
V
tive slew rates.
Note 11: Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
Note 12: Guaranteed limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
+
−
+
+
+
<
<
V
Note 13: CMRR and CMRR are tested, and the number indicated is the lower of the two values. For CMRR , V /2
V
CM
for 1.8V, 2.2V, 3V, 5V, and 10V.
−
+
+
<
<
<
<
V V
CM
For CMRR , 0
V
V /2 for 3V, 5V and 10V. For 1.8V and 2.2V, 0.25 − 0.3.
=
0.5V. For Sourcing tests, 1V ≤ V ≤ 5V. For Sinking tests, 5V ≤ V ≤ 9V.
CM
10V, V
+
=
Note 14:
V
CM
O
O
=
Note 15: The propogation delays are measured using an input waveform of f 5 Hz, and magnitude of 2.4V. Refer to Section 6.3 and Figures 14, 15 for a detailed
explanation.
Note 16: The V (threshold low and threshold high) limits are guaranteed at room temperature and at temperature extremes. Room temperature limits are produc-
PD
tion tested. Limits at temperature extremes are guaranteed via correlation using temperature regression analysis methods. Refer to Section 6.2 for an overview of
the threshold voltages.
9
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=
=
Typical Performance Characteristics VS+ 3V, Single Supply, TA 25˚C unless otherwise specified
Supply Current per Amplifier
vs Supply Voltage
Sourcing Current
vs Output Voltage
Sinking Current
vs Output Voltage
DS012042-40
DS012042-41
DS012042-42
Input Voltage Noise
∆VOS vs VCM
∆VOS vs VCM
vs Common-Mode Voltage
DS012042-44
DS012042-45
DS012042-43
Frequency Response
vs Temperature
Frequency Response
vs RL
Input Voltage Noise
vs Frequency
DS012042-46
DS012042-47
DS012042-48
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10
=
=
Typical Performance Characteristics VS+ 3V, Single Supply, TA 25˚C unless otherwise
specified (Continued)
CMRR
vs Frequency
Positive PSRR
vs Frequency
Negative PSRR
vs Frequency
DS012042-49
DS012042-50
DS012042-51
Crosstalk Rejection
vs Frequency
Slew Rate vs
Supply Voltage
Non-Inverting Large
Signal Pulse Response
DS012042-54
DS012042-52
DS012042-53
Inverting Large
Signal Pulse Response
Non-Inverting Small
Signal Pulse Response
Inverting Small
Signal Pulse Response
DS012042-55
DS012042-56
DS012042-57
11
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=
=
Typical Performance Characteristics VS+ 3V, Single Supply, TA 25˚C unless otherwise
specified (Continued)
Stability vs
Stability vs
Stability vs
Capacitive Load
Capacitive Load
Capacitive Load
DS012042-60
DS012042-58
DS012042-59
tON Delay till Active-On
after tPD OFF in
=
Powerdown Mode, VS 3V
DS012042-39
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12
Application Information
2.0 Rail-to-Rail Output
The approximated output resistance of the LMC6681/2/4 is
=
50Ω sourcing, and 50Ω sinking at VS 3V. The maximum
1.0 Input Common-Mode Voltage
Range
output swing can be estimated as a function of load using the
calculated output resistance.
The LMC6681/2/4 has a rail-to-rail input common-mode volt-
age range. Figure 1 shows an input voltage exceeding both
supplies with no resulting phase inversion on the output.
3.0 Low Voltage Operation
The LMC6682 operates at supply voltages of 2.2V and 1.8V.
These voltages represent the End of Discharge voltages of
several popular batteries. The amplifier can operate from 1
Lead-Acid or Lithium Ion battery, or 2NiMH, NiCd, or
Carbon-Zinc batteries. Nominal and End of Discharge of
Voltage of several batteries are listed below.
Battery Type
Nominal Voltage End of Discharge
Voltage
NiMH
1.2V
1V
1V
NiCd
1.2V
Lead-Acid
Silver Oxide
Carbon-Zinc
Lithium
2V
1.8V
1.6V
1.5V
1.3V
DS012042-5
1.1V
FIGURE 1. An Input Signal Exceeds the LMC6681/2/4
Power Supply Voltages with No Output Phase
Inversion
2.6V–3.6V
1.7V–2.4V
=
At VS
2.2V, the LMC6681/2/4 has a rail-to-rail input
common-mode voltage range. Figure 4 shows an input volt-
age extending to both supplies and the resulting output.
The absolute maximum input voltage at V+ 3V is 300 mV
=
beyond either supply rail at room temperature. Voltages
greatly exceeding this absolute maximum rating, as in Figure
2, can cause excessive current to flow in or out of the input
pins, possibly affecting reliability. The input current can be
±
externally limited to 5 mA, with an input resistor, as shown
in Figure 3.
DS012042-8
FIGURE 4. The Input Common-Mode Voltage
=
Range Extends to Both Supplies at VS 2.2V
=
The amplifier is operational at VS 1.8V, with guaranteed in-
put common-mode voltage range, output swing, and CMRR
specs. Figure 5 shows the response of the LMC6681/2/4 at
DS012042-6
=
VS 1.8V.
±
FIGURE 2. A 7.5V Input Signal Greatly
Exceeds the 3V Supply in Figure 3,
Causing No Phase Inversion Due to RI
DS012042-7
FIGURE 3. Input Current Protection for
Voltages Exceeding the Supply Voltage
DS012042-9
FIGURE 5. Response of the LMC6681/2/4
=
at VS 1.8V
13
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3.0 Low Voltage Operation (Continued)
Figure 6 shows an input voltage exceeding both supplies
with no resulting phase inversion on the output.
DS012042-11
FIGURE 7. Resistive Isolation
of a 350 pF Capacitive Load
Figure 8 displays the pulse response of the LMC6681 circuit
in Figure 7.
DS012042-10
FIGURE 6. An Input Voltage Signal Exceeds
LMC6681/2/4 Power Supply Voltages of
=
VS 1.8V with No Output Phase Inversion
4.0 Capacitive Load Tolerance
The LMC6681/2/4 can typically drive a 100 pF load with VS
=
10V at unity gain without oscillating. The unity gain fol-
lower is the most sensitive configuration to capacitive load.
Direct capacitive loading reduces the phase margin of
op-amps. The combination of the op-amp’s output imped-
ance and the capacitive load induces phase lag. This results
in either an underdamped pulse response or oscillation.
DS012042-12
FIGURE 8. Pulse Response of the
LMC6681 Circuit in Figure 7
Capacitive load compensation can be accomplished using
resistive isolation as shown in Figure 7. If there is a resistive
component of the load in parallel to the capacitive compo-
nent, the isolation resistor and the resistive load create a
voltage divider at the output. This introduces a DC error at
the output.
Another circuit, shown in Figure 9, is also used to indirectly
drive capacitive loads. This circuit is an improvement to the
circuit shown Figure 7 because it provides DC accuracy as
well as AC stability. R1 and C1 serve to counteract the loss
of phase margin by feeding the high frequency component of
the output signal back to the amplifiers inverting input,
thereby preserving phase margin in the overall feedback
loop. The values of R1 and C1 should be experimentally de-
termined by the system designer for the desired pulse re-
sponse. Increased capacitive drive is possible by increasing
the value of the capacitor in the feedback loop.
DS012042-13
FIGURE 9. The LMC6682 Compensated
to Ensure DC Accuracy and AC Stability
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14
4.0 Capacitive Load Tolerance (Continued)
The pulse response of the circuit shown in Figure 9 is shown in Figure 10.
DS012042-14
FIGURE 10. Pulse Response of the
LMC6682 Circuit Shown in Figure 9
Application Hints
5.0 Printed-Circuit-Board Layout for High-Impedance Work
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low input current of the LMC6681/2/4, typically
less than 80 fA, it is essential to have an excellent layout.
Fortunately, the techniques of obtaining low leakages are
quite simple. First, the user must not ignore the surface leak-
age of the PC board, even though it may sometimes appear
acceptably low, because under conditions of high humidity or
dust or contamination, the surface leakage will be appre-
ciable.
would cause only 0.05 pA of leakage current. See Figure 12
for typical connections of guard rings for standard op-amp
configurations.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6681/2/4’s inputs and
the terminals of capacitors, diodes, conductors, resistors, re-
lay terminals, etc. connected to the op-amp’s inputs, as in
Figure 11. To have a significant effect, guard rings should be
placed in both the top and bottom of the PC board. This PC
foil must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 1012Ω, which is nor-
mally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of the input. This
would cause a 60 times degradation from the LMC6681/2/
4’s actual performance. However, if a guard ring is held
within 5 mV of the inputs, then even a resistance of 1011Ω
DS012042-18
FIGURE 11. Example of Guard Ring in PC Board
Layout
15
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5.0 Printed-Circuit-Board Layout
for High-Impedance Work (Continued)
DS012042-22
(Input pins are lifted out of PC board and soldered directly to components.
All other pins are connected to PC board.)
FIGURE 13. Air Wiring
DS012042-19
Inverting Amplifier
6.0 Powerdown
6.1 PINOUT FOR THE LMC6681/LMC6682/LMC6684
For the LMC6681/2/4, the input, output, and power pins are
the same as those used in the standard configuration. One
of the other pins, pin 5 in the case of the LMC6681, is used
to enable the powerdown mode. The connection diagrams
for the LMC6681/2/4 are on the front page of the datasheet.
DS012042-20
The LMC6684 has 2 powerdown options. Each of the power-
down pins disables two amplifiers. If both the powerdown
pins are pulled high, all four amplifiers will be disabled. Re-
ferring to the connection diagrams on the front page of the
datasheet, Pin 5 disables amplifiers B and C and Pin 13 dis-
ables amplifiers A and D.
Non-Inverting Amplifier
6.2 EXPLANATION OF DATASHEET PARAMETERS
The LMC6681/2/4 is ON (meets all the datasheet specs)
when the voltage applied to the powerdown pin, VPD is a
logic low. The device is OFF when VPD is a logic high. These
logic levels are indicated in the test conditions in the
datasheet tables. Summarizing these numbers:
DS012042-21
Follower
FIGURE 12. Typical Connections of Guard Rings
The designer should be aware that when it is inappropriate
to lay out a PC board for the sake of just a few circuits, there
is another technique which is even better than a guard ring
on a PC board: Don’t insert the amplifier’s input pin into the
board at all, but bend it up in the air and use only air as an in-
sulator. Air is an excellent insulator. In this case you may
have to forego some of the advantages of PC board con-
struction, but the advantages are sometimes well worth the
effort of using point-to-point up-in-the-air wiring. See Figure
13.
Supply
Voltage
2.2V
3V
Logic High [V]
Logic Low [V]
at room
over temp
VPD ≥ 1.65
VPD ≥ 2.45
VPD ≥ 4.45
VPD ≥ 9.45
at room
over temp
VPD ≤ 0.25
VPD ≤ 0.45
VPD ≤ 0.75
VPD ≤ 1.05
VPD ≥ 1.5
VPD ≥ 2.3
VPD ≥ 4.3
VPD ≥ 9.3
VPD ≤ 0.4
VPD ≤ 0.6
VPD ≤ 0.9
VPD ≤ 1.2
5V
10V
In applications where the powerdown pin is not connected
externally, it is pulled to a logic low internally through a cur-
rent source. The tON and tOFF specs will essentially be the
same for a VPD in the specified range. This means that the
LMC6681/2/4 will typically be fully operational 50 µs after a
logic low has been applied to the powerdown pin. Please
note that the frequency of VPD in the test circuit below is
5 Hz.
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16
powerdown pin is pulled high, the amplifier shuts down, and
draws less than 1 µA/Amplifier. In this powerdown mode, the
output pin has high impedance, and the output of the circuit
is pulled to 0V. tON is specified as the time between the 50%
points of the trailing edges of the input waveform at the pow-
erdown pin, and the waveform at the output pin. Similarly,
the tOFF is specified as the time between the 50% points of
the leading edges of the input waveform at the powerdown
pin, and the waveform at the output pin.
6.0 Powerdown (Continued)
6.3 TEST CIRCUIT TO MEASURE tON AND tOFF
The circuit used to measure the tON, and tOFF during the
powerdown operation is a voltage follower with a load of
2 kΩ as shown in Figure 14.
When the input to the powerdown pin is low, the LMC6681/
2/4 is on. Since the amplifier is connected in the voltage fol-
lower configuation, the output of the circuit is −1V. When the
DS012042-16
FIGURE 14. Test Circuit for tON and tOFF Measurements
DS012042-17
DS012042-29
(a) tOFF Measurement
(b) tON Measurement
FIGURE 15.
6.4 tON and tOFF
The tON (time delay for device to power on) the tOFF (time de-
lay for device to power off) specs are guaranteed at a supply
voltage of 3V. The tON and tOFF spec are independent of the
VPD applied in the specified range. Refer to the Powerdown
DC Threshold Characteristics table for the values for a logic
low and a logic high.
The guaranteed spec for tON is 200 µs. This does not mean
that the signal to the VPD pin can be as high as 5 kHz (1/200
µs). Note that the VPD frequency for the tON and tOFF mea-
surements is 5 Hz. The LMC6681/2/4 is ideal for DC type ap-
plications where the powerdown pin is controlled by low fre-
quency signals.
When the LMC6681/2/4 is powered off, internal bias currents
are shutoff. There is a inherent latency in the circuit, and the
device has to power off for a certain period of time for the tON
spec to apply. Refer to the figure below. tPD OFF refers to the
time interval for which the device is in the powerdown mode.
Consider the case when the device has been powered off for
5 ms, and then the powerdown pin is pulled to a logic low.
From Figure 16, at room temperature, the device powers on
after 500 µs.
DS012042-39
FIGURE 16. tON Delay Till Active-On after
=
tPDOFF in Powerdown Mode, VS 3V
17
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7.0 Compensating for Input
Capacitance
It is quite common to use large values of feedback resis-
tance with amplifiers that have ultra-low input current, like
the LMC6681/2/4. Large feedback resistors can react with
small values of input capacitance due to transducers, photo-
diodes, and circuits board parasitics to reduce phase
margins.
Applications
Transducer Interface Circuits
A. PIEZOELECTRIC TRANSDUCERS
DS012042-24
FIGURE 18. Transducer Interface Application
The LMC6681 can be used for processing of transducer sig-
nals as shown in the circuit below. The two 11 MΩ resistors
provide a path for the DC currents to ground. Since the resis-
tors are bootstrapped to the output, the AC input resistance
of the LMC6681 is much higher.
DS012042-15
FIGURE 17. Canceling the Effect of Input Capacitance
The effect of input capacitance can be compensated for by
adding a feedback capacitor. The feedback capacitor (as in
Figure 17), CF, is first estimated by:
or
DS012042-36
R1CIN ≤ R2CF
FIGURE 19. LMC6681 Used for Signal Processing
which typically provides significant overcompensation.
Printed circuit board stray capacitance may be larger or
smaller than that of a breadboard, so the actual optimum
value for CF may be different. The values of CF should be
checked on the actual circuit. (Refer to the LMC660 quad
CMOS amplifier data sheet for a more detailed discussion.)
An input current of 80 fA and a CMRR of 82 dB causes an in-
significant error offset voltage at the output. The rail-to-rail
performance of the amplifier also provides the maximum dy-
namic range for the transducer signals.
B. PHOTODIODE AMPLIFIERS
8.0 Spice Macromodel
A Spice Macromodel is available for the LMC6681/2/4. The
model includes a simulation of:
•
•
•
•
•
Input common-mode voltage range
Frequency and transient response
GBW dependence on loading conditions
Quiescent and dynamic supply current
Output swing dependence on loading conditions
and many more characteristics as listed on the macromodel
disk.
Contact the National Semiconductor Customer Response
Center at 1-800-272-9959 to obtain an operational amplifier
spice macromodel library disk.
DS012042-26
FIGURE 20. Photodiode Amplifier
Photocells can be used in light measuring instruments. An
error offset voltage is produced at the output due to the input
current and the offset voltage of the amplifier. The LMC6682,
which can be operated off a single battery is an excellent
choice for this application with its 80 fA input current and 0.5
mV offset voltage.
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18
Low Voltage Peak Detector
→
=
t2 0.74 seconds
Then,
DS012042-23
FIGURE 21. Low Voltage Peak Detector
The accuracy of the peak detector is dependent on the leak-
age currents of the diodes and the capacitors, and the
non-idealities of the amplifier. The parameters of the ampli-
fier which can limit the performance of this circuit are (a) Fi-
nite slew rate, (b) Input current, and (c) Maximum output cur-
rent of the amplifier.
LMC6681/2/4 as a Comparator
The input current of the amplifier causes a slow discharge of
the capacitor. This phenomenon is called “drooping”. The
LMC6682 has a typical input current of 80 fA. This would
=
=
cause the capacitor to droop at a rate of dV/dt
IB/C
=
80 fA/100 pF
0.8 mV/s. Accuracy in the amplitude mea-
DS012042-31
surement is also maintained by an offset voltage of 0.5 mV,
and an open-loop gain of 120 dB.
FIGURE 23. Comparator with Hysteresis
Figure 23 shows the application of the LMC6681/2/4 as a
comparator. The hysteresis is determined by the ratio of the
two resistors. Since the supply current of the LMC6681/2/4 is
less than 1 mA, it can be used as a low power comparator, in
applications where the quiescent current is an important pa-
Oscillators
=
rameter. At VS 3V, typical propagation delays would be on
=
=
the order of tPHL 6 µs, and tPLH 5 µs.
Filters
DS012042-30
FIGURE 22. 1 Hz Square — Wave Oscillator
For single supply 5V operation, the output of the circuit will
swing from 0V to 5V. The voltage divider set up R2, R3 and
R4 will cause the non-inverting input of the LMC6681/2/4 to
move from 1.67V (1⁄
3
of 5V) to 3.33V (2⁄
of 5V). This voltage
3
behaves as the threshold voltage.
R1 and C1 determine the time constant for the circuit. The
frequency of oscillation, fOSC is
DS012042-32
FIGURE 24. Wide-Band Band-Pass Filter
The filter shown in Figure 24 is used to process “voice-band”
signals. The bandpass filter has a gain of 40 dB. The two
corner frequencies, f1 and f2 are calculated as
where ∆t is the time the amplifier input takes to move from
1.67V to 3.33V. The calculations are shown below.
=
=
where τ RC 0.68 seconds
→
=
t1 0.27 seconds.
and
19
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Filters (Continued)
Battery Monitoring Circuit
The LMC6681/2/4, with its rail-to-rail input common-mode
=
voltage range and high gain (120 dB typical, RL 10 kΩ) is
extremely well suited for such filter applications. The
rail-to-rail input range allows for large input signals to be pro-
cessed without distortion. The high gain means that the cir-
cuit can provide filtering and gain in one stage, instead of the
typical two stage filter. This implies a reduction in cost, and
savings of space and power.
This is an illustration of the conceptual use of the LMC6681/
2/4. The selectivity of the filter can be improved by increas-
ing the order (number of poles) of the design.
Sample-and-Hold Circuits
DS012042-37
FIGURE 26. Circuit Used to Sense Charging
DS012042-34
FIGURE 25. Sample-and-Hold Application
DS012042-38
When the “Switch” is closed during the Sample Interval,
CHOLD charges up to the value of the input signal when the
“Switch” is open, CHOLD retains this value as it is buffered by
the high input impedance of the LMC6681.
FIGURE 27. Circuit Used to Sense Discharging
The LMC6681/2/4 has been optimized for performance at
3V, and also has guaranteed specs at 1.8V and 2.2V. In por-
table applications, the RLOAD represents the laptop/
notebook, or any other computer which the battery is power-
Errors in the “hold” voltage are caused by the input current of
the amplifier, the leakage current of the CD4066, and the
leakage current of the capacitor. While an input current of 80
fA minimizes the accumulation rate for error in this circuit, the
LMC6681’s CMRR of 82 dB allows excellent accuracy
throughout the amplifier’s rail-to-rail dynamic capture range.
ing.
A desired output voltage can be achieved by
manipulating the ratios of the feedback resistors. During the
charging cycle, the current flows out of the battery as shown.
While during discharge, the current is in the reverse direc-
tion. Since the current can range from a few milliamperes to
amperes, the amplifier will have to sense a signal below
ground during the discharge cycle. At 3V, the LMC6681/2/4
can accept a signal up to 300 mV below ground. The
common-mode voltage range of the LMC6681/2/4, which ex-
tends beyond both rails, is thus a very useful feature in this
application.
A typical offset voltage of 0.5 mV, and CMRR of 82 dB main-
tain accuracy in the circuit output, while the rail-to-rail output
performance allows for a maximum signal range.
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20
Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin Small Outline Package
Order Number LMC6681AIM or LMC6681BIM
NS Package Number M08A
14-Pin Small Outline Package
Order Number LMC6682AIM or LMC6682BIM
NS Package Number M14A
21
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Pin Small Outline Package
Order Number LMC6684AIM or LMC6684BIM
NS Package Number M16A
8-Pin Molded Dual-In-Line Package
Order Number LMC6681AIN or LMC6681BIN
NS Package Number N08E
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22
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Pin Molded Dual-In-Line Package
Order Number LMC6682AIN or LMC6682BIN
NS Package Number N14A
16-Pin Molded Dual-In-Line Package
Order Number LMC6684AIN or LMC6684BIN
NS Package Number N16A
23
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Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
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Tel: 81-3-5639-7560
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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