LMF40CIN-100 [NSC]
IC SWITCHED CAPACITOR FILTER, BUTTERWORTH, LOWPASS, PDIP8, 0.300 INCH, MINI, PLASTIC, DIP-8, Active Filter;
| 型号： | LMF40CIN-100 |
| 厂家： | 
National Semiconductor |
| 描述： | IC SWITCHED CAPACITOR FILTER, BUTTERWORTH, LOWPASS, PDIP8, 0.300 INCH, MINI, PLASTIC, DIP-8, Active Filter LTE 信息通信管理 光电二极管 有源滤波器 |
| 文件： | 总16页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1994
LMF40 High Performance 4th-Order
Switched-Capacitor Butterworth Low-Pass Filter
General Description
Features
Y
Cutoff frequency range of 0.1 Hz to 40 kHz
The LMF40 is a versatile, easy to use, precision 4th-order
Butterworth low-pass filter fabricated using National’s high
performance LMCMOS process. Switched-capacitor tech-
niques eliminate external component requirements and al-
low a clock-tunable cutoff frequency. The ratio of the clock
frequency to the low-pass cutoff frequency is internally set
to 50-to-1 (LMF40-50) or 100-to-1 (LMF40-100). A Schmitt
trigger clock input stage allows two clocking options, either
self-clocking (via an external resistor and capacitor) for
stand-alone applications, or for tighter cutoff frequency con-
trol, an external TTL or CMOS logic compatible clock can
be applied. The maximally flat passband frequency re-
sponse together with a DC gain of 1 V/V allows cascading
LMF40 sections together for higher-order filtering.
Y
Y
Y
Y
Y
Y
g
Cutoff frequency accuracy of 1.0%, maximum
Low offset voltage, 100 mV, maximum, 5V supply
g
g
Low clock feedthrough of 5 mV , typical
P-P
Dynamic range of 88 dB, typical
No external components required
8-pin mini-DIP or 14-pin wide-body small-outline pack-
ages
Y
Y
Y
4V to 14V single/dual supply operation
Cutoff frequency set by external or internal clock
Pin-compatible with MF4
Applications
Y
Communication systems
Y
Instrumentation
Y
Automated control systems
Block and Connection Diagrams
Dual-In-Line Package
TL/H/10557–2
Top View
Small-Outline-Wide-Body Package
TL/H/10557–1
*Pin numbers in parentheses are for the 14-pin package
Ordering Information
s
a
TL/H/10557–3
s
b
Industrial ( 40 C
T
A
85 C)
§
Package
N08E
§
Top View
LMF40CIN-50, LMF40CIN-100
LMF40CIWM-50
M14B
LMF40CIWM-100
M14B
s
s
a
b
Military ( 55 C
T
125 C)
§
§
LMF40CMJ-50, LMF40CMJ-100
A
J08A
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/H/10557
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Lead Temperature
a
a
a
a
N Package, Soldering (10 sec.)
J Package, Soldering (10 sec.)
WM Package, Vapor Phase (60 sec.) (Note 16)
WM Package, Infrared (15 sec.)
260 C
§
300 C
§
Supply Voltage (Va –Vb
)
15V
0.2V
5 mA
215 C
§
220 C
§
a
0.2V to V
b
a
Voltage at Any Pin
Vb
ESD Susceptibility (Note 12)
Pin 1 CLK IN
2000V
1700V
Input Current at Any Pin (Note 13)
Package Input Current (Note 13)
Power Dissipation (Note 14)
Storage Temperature
20 mA
500 mW
Operating Ratings (Notes 1 & 2)
Temperature Range
LMF40CIN-50, LMF40CIN-100
LMF40CIWM-50,
LMF40CIWM-100
LMF40CMJ-50, LMF40CMJ-100 55 C
Supply Voltage Range (Va
b
a
65 C to 150 C
§
§
s
s
T
T
T
A
MIN
A
MAX
s
s
b
b
a
85 C
40 C
T
§
§
s
s
a
T
A
125 C
§
§
4V to 14V
b
b
V
)
Filter Electrical Characteristics
The following specifications apply for f
e
e
e
T T
J
500 kHz. Boldface limits apply for T
to T
: All other limits T
MAX A
CLK
A
MIN
e
e
25 C.
T
J
§
Typical
Conditions
(Note 10)
Limits
Units
Symbol
e a
Parameter
5V
(Note 11)
(Limit)
b
5V, V
Va
e b
f
Clock Frequency Range
(Note 17)
CLK
5
Hz (min)
2
MHz (max)
I
Supply Current
DC Gain
CMJ
3.5 / 7.0
3.5 / 5.0
mA (max)
mA (max)
S
CIN, CIJ, CIWM
s
a
b
a
H
R
Source
2 kX
0.05 / 0.05
dB (max)
dB (min)
O
b
0.15 / 0.20
f
/f
Clock to Cutoff
Frequency Ratio
(Note 3)
CLK
c
g
g
LMF40-50
49.80 0.8% / 49.80 1.0%
(max)
(max)
g
g
99.00 0.8% / 99.00 1.0%
LMF40-100
Df
/f /DT
CLK
Clock to Cutoff Frequency
Ratio Temperature
Coefficient
c
LMF40-50
5
5
ppm/ C
§
ppm/ C
§
LMF40-100
A
MIN
Stopband Attenuation
At 2 f
24.0
dB (min)
c
2
Filter Electrical Characteristics (Continued)
e
e
e
T T
J
The following specifications apply for f
e
500 kHz. Boldface limits apply for T
to T
: All other limits T
MAX A
CLK
A
MIN
e
T
J
25 C.
§
Typical
Limits
(Note 11)
Units
Symbol
e a
Parameter
e b
5V (Continued)
Conditions
(Note 10)
(Limit)
b
Va
5V, V
V
OS
Unadjusted DC
Offset Voltage
g
g
g
LMF40-50
LMF40-100
80 / 100
mV (max)
mV (max)
g
80 / 100
e
R
L
a
b
a
V
O
Output Swing
5 kX
3.9 / 3.7
V (min)
V (max)
b
4.2 / 4.0
I
Output Short Circuit
Current (Note 8)
Source
Sink
90
mA
mA
SC
2.2
Dynamic Range
(Note 4)
88
dB
Additional Magnitude
Response Test Points
(Note 6)
e
e
b
b
b
g
g
LMF40-50
f
f
12 kHz
9 kHz
7.50 0.26 / 7.50 0.30
dB (max)
dB (max)
IN
IN
b
1.46 0.12 / 1.46 0.16
g
g
e
e
b
b
b
g
g
LMF40-100
f
f
6 kHz
7.15 0.26 / 7.15 0.30
dB (max)
dB (max)
IN
b
1.42 0.12 / 1.42 0.16
g
g
4.5 kHz
IN
Clock Feedthrough
Filter Output
e
5
mV
P–P
V
0V
IN
e
Filter Electrical Characteristics The following specifications apply for f
250 kHz. Boldface limits
CLK
e
e
e
e
T
J
apply for T
T
T
to T
: All other limits T
25 C.
§
A
J
MIN
MAX
A
Typical
Limits
Units
Symbol
Parameter
Conditions
(Note 10)
(Note 11)
(Limit)
b
Va
2.5V, V
e a
e b
2.5V
f
Clock Frequency Range
(Note 17)
CLK
5
Hz (min)
1.0
MHz (max)
I
Supply Current
DC Gain
CMJ
2.1 / 4.0
2.1 / 3.0
mA (max)
mA (max)
S
CIN, CIJ, CIWM
s
a
b
a
H
R
S
2 kX
0.05 / 0.05
dB (max)
dB (min)
O
e
b
0.15 / 0.20
f
250 kHz
CLK
e
b
0.1
f
500 kHz
dB
CLK
f
/f
Clock to Cutoff
Frequency Ratio
LMF40-50
CLK
c
e
e
g
49.80 0.8%
f
f
250 kHz
500 kHz
(max)
CLK
49.80
CLK
g
0.6%
e
e
g
g
99.00 1.0% / 99.00 1.2%
LMF40-100
(Note 3)
f
f
250 kHz
500 kHz
(max)
CLK
99.00
CLK
g
1.2%
3
Filter Electrical Characteristics (Continued)
e
e
e
The following specifications apply for f
e
250 kHz. Boldface limits apply for T
T
T
MIN
to T
: All other limits T
MAX A
CLK
A
J
e
T
J
25 C.
§
Typical
Conditions
(Note 10)
Limits
(Note 11)
Units
Symbol
Parameter
e b
2.5V (Continued)
(Limit)
Va
2.5V, V
b
e a
Df
/f /DT
Clock to Cutoff
CLK
c
Frequency Ratio
Temperature Coefficient
LMF40-50
5
5
ppm/ C
§
ppm/ C
§
LMF40-100
b
A
V
Stopband Attenuation
At 2 f
24.0
dB (min)
MIN
c
Unadjusted DC
Offset Voltage
OS
g
g
g
LMF40-50
80 / 100
mV (max)
mV (max)
g
80 / 100
LMF40-100
e
R
L
a
b
a
V
O
Output Swing
5 kX
1.4 / 1.2
V (min)
V (max)
b
2.0 / 1.8
I
Output Short Circuit
Current (Note 8)
Source
Sink
42
mA
mA
SC
0.9
Dynamic Range
(Note 4)
81
dB
Additional Magnitude Response
Test Points (Note 6)
LMF40-50
e
e
b
b
b
g
g
f
f
6 kHz
7.50 0.26 / 7.50 0.30
dB (max)
dB (max)
IN
b
g g
1.46 0.12 / 1.46 0.16
4.5 kHz
IN
e
e
b
b
b
g
g
LMF40-100
f
f
3 kHz
7.15 0.26 / 7.15 0.30
dB (max)
dB (max)
IN
IN
b
1.42 0.12 / 1.42 0.16
g
g
2.25 kHz
Clock Feedthrough
Filter Output
e
5
mV
P–P
V
0V
IN
Logic Input-Output Characteristics The following specifications apply for Vb 0V unless otherwise
e
e
e
e
e
T 25 C.
J
specified. Boldface limits apply for T
T
J
T
MIN
to T
: all other limits T
§
A
MAX
A
Typical
Limits
Units
Symbol
Parameter
Conditions
(Note 10)
(Note 11)
(Limit)
TTL CLOCK INPUT, CLK R PIN (Note 9)
Va
Vb
e a
5V
e b
5V
TTL CLK R Pin Input Voltage
Logic ‘‘1’’
Logic ‘‘0’’
2.0 / 2.1
0.8 / 0.8
V (min)
V (max)
Va
Vb
e a
2.5V
e b
2.5V
CLK R Input Voltage
Logic ‘‘1’’
Logic ‘‘0’’
2.0 / 2.0
0.6 / 0.4
V (min)
V (max)
Maximum Leakage Current
at CLK R Pin
2.0
mA
SCHMITT TRIGGER
a
e a
e a
V
T
Positive Going Input
Threshold Voltage
CLK IN Pin
Va
10V
5V
6.1 / 6.0
8.8 / 8.9
V (min)
V (max)
Va
3.0 / 2.9
4.3 / 4.4
V (min)
V (max)
4
Logic Input-Output Characteristics (Continued) The following specifications apply for Vb 0V unless
e
e
e
e
e
T 25 C.
J
otherwise specified. Boldface limits apply for T
T
T
MIN
to T
: all other limits T
§
A
J
MAX
A
Typical
Limits
Units
Symbol
Parameter
Conditions
(Note 10)
(Note 11)
(Limit)
SCHMITT TRIGGER (Continued)
b
e a
e a
e a
e a
V
Negative Going Input
Threshold Voltage
CLK IN Pin
Va
10V
5V
1.4 / 1.3
3.8 / 3.9
V (min)
V (max)
T
Va
Va
Va
0.7 / 0.6
1.9 / 2.0
V (min)
V (max)
a b
b
V
T
V
T
Hysteresis CLK IN Pin
10V
5V
2.3 / 2.1
7.4 / 7.6
V (min)
V (max)
1.1 / 0.9
3.6 / 3.8
V (min)
V (max)
e b
10 mA
Logical ‘‘1’’ Output
Voltage CLK R
Pin
I
O
Va
Va
10V
5V
9.1 / 9.0
4.6 / 4.5
V (min)
V (min)
e a
e a
e b
10 mA
Logical ‘‘0’’ Output
Voltage CLK R
Pin
I
O
Va
Va
10V
5V
0.9 / 1.0
0.4 / 0.5
V (max)
V (max)
e a
e a
Output Source Current
CLK R Pin
CLK R to Vb
Va
Va
10V
5V
4.9 / 3.7
1.6 / 1.2
mA (min)
mA (min)
e a
e a
Output Sink Current
CLK R Pin
CLK R to Va
Va
Va
10V
5V
4.9 / 3.7
1.6 / 1.2
mA (min)
mA (min)
e a
e a
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating range.
Note 2: All voltages are specified with respect to ground.
Note 3: The filter’s cutoff frequency is defined as the frequency where the magnitude response is 3.01 dB less than the DC gain of the filter.
g
Note 4: For 5V supplies the dynamic range is referenced to 2.62 V
(3.7V peak) where the wideband noise over a 20 kHz bandwidth is typically 100 mV
for
rms
the LMF40. For 2.5V supplies the dynamic range is referenced to 0.849 V
rms
(1.2V peak) where the wideband noise over a 20 kHz bandwidth is typically
g
for the LMF40.
rms
75 mV
rms
g
g
Note 5: The specifications for the LMF40 have been given for a clock frequency (f
g
) of 500 kHz at 5V and 250 kHz at 2.5V. Above this clock frequency the
CLK
cutoff frequency begins to deviate from the specified error band of 0.8% over the temperature range, but the filter still maintains its magnitude characteristics.
See Application Information, Section 1.4.
e
Note 6: The filter’s magnitude response is tested at the cutoff frequency, f , f
c
2 f , and at these other two additional frequencies.
c
S
Note 7: For simplicity all logic levels have been referenced to Vb
e
g
0V (except for the TTL input logic levels). The logic levels will scale accordingly for 5V and
g
2.5V supplies.
Note 8: The short circuit source current is measured by forcing the output that is being tested to its maximum positive swing and then shorting that output to the
negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage and then shorting that output
to the positive supply. These are worst case conditions.
Note 9: The LMF40 is operated with symmetrical supplies and L. Sh. is tied to ground.
e
Note 10: Typicals are at T
25 C and represent the most likely parametric norm.
§
J
Note 11: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Human body model; 100 pF discharged through a 1.5 kX resistor.
b
a) the absolute value of the current at that pin should
k
l
V
Note 13: When the input voltage (V ) at any pin exceeds the power supply voltages (V
V
or V
IN
be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply voltages with 5 mA current limit to four.
IN
IN
Note 14: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by T , i , and the ambient temperature T . The
JMAX
JA
A
e
b
T
maximum allowable power dissipation is PD
e
(T
)/i or the number given in the Absolute Maximum Ratings, whichever is lower. For the LMF40,
A JA
JMAX
125 C, and the typical junction-to-ambient thermal resistance, when board mounted, is 67 C/W for the LMF40CIN, 62 C/W for the LMF40CIJ and
T
§
§
§
JMAX
LMF40CMJ, and 78 C/W for the LMC40CIWM.
§
Note 15: In popular usage the term cutoff frequency defines that frequency at which a filter’s gain drops 3.01 dB below its DC value. Equations (2) and (3) and
design example 2.1, however, use the term cutoff frequency (f ) to define that frequency at which a filter’s gain drops by a variable amount as determined from the
b
given design specifications.
Note 16: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering surface mount devices or see the section
titled ‘‘Surface Mount’’ in the Linear Data Book.
Note 17: The nominal ratio of the clock frequency to the low-pass cutoff frequency is internally set to 50-to-1 (LMF40-50) or 100-to-1 (LMF40-100).
5
Typical Performance Characteristics
f
vs Power Supply Voltage
/f Deviation
CLK
f
CLK
vs Temperature
/f Deviation
f
CLK
vs Clock Frequency
/f Deviation
c
c
c
TL/H/10557–5
6
Typical Performance Characteristics (Continued)
Power Supply Current
vs Power Supply Voltage
Power Supply Current
vs Temperature
Positive Voltage Swing
vs Power Supply Voltage
TL/H/10557–6
7
Pin Descriptions
(Numbers in ( ) are for 14-pin package).
Pin
Ý
Pin
Pin
Ý
Pin
Function
Function
Name
Va, Vb
Name
CLK IN
7, 4
The positive and negative
supply pins. The total power
supply range is 4V, to 14V.
Decoupling these pins with
0.1 mF capacitors is highly
recommended.
1
A CMOS Schmitt-trigger input
to be used with an external
CMOS logic level clock. Also
used for self clocking Schmitt-
trigger oscillator (see Section
1.1).
(7, 12)
(1)
8
FILTER
IN
The input to the low-pass filter.
To minimize gain errors the
source impedance that drives
this input should be less than
2k (see Section 3). For single
supply operation the input
signal must be biased to mid-
supply or AC coupled through
a capacitor.
2
CLK R
A TTL logic level clock input
when in split supply operation
(14)
(3)
g
g
2.0V to 7V) with L. Sh
(
tied to system ground. This pin
becomes a low impedance
output when L. Sh is tied to
V
b. Also used in conjunction
with the CLK IN pin for a self
clocking Schmitt-trigger
oscillator (see Section 1.1).
The TTL input signal must not
exceed the supply voltages by
more than 0.2V.
1.0 LMF40 Application Information
The LMF40 is a non-inverting unity gain low-pass fourth-or-
der Butterworth switched-capacitor filter. The switched-ca-
pacitor topology makes the cutoff frequency (where the gain
drops 3.01 dB below the DC gain) a direct ratio (100:1 or
50:1) of the clock frequency supplied to the filter. Internal
integrator time constants set the filter’s cutoff frequency.
The resistive element of these integrators is actually a ca-
pacitor which is ‘‘switched’’ at the clock frequency (for a
detailed discussion see Input Impedance section). Varying
the clock frequency changes the value of this resistive ele-
ment and thus the time constant of the integrators. The
3
L. Sh
Level shift pin; selects the
logic threshold levels for the
clock. When tied to Vb it
enables an internal TRI-
(5)
STATE buffer stage between
É
the Schmitt trigger and the
internal clock level shift stage
thus enabling the CLK IN
Schmitt-trigger input and
making the CLK R pin a low
impedance output. When the
clock-to-cutoff-frequency ratio (f
/f ) is set by the ratio of
CLK c
the input and feedback capacitors in the integrators. The
higher the clock-to-cutoff-frequency ratio the closer this ap-
proximation is to the theoretical Butterworth response.
voltage level at this input
b
exceeds 25% (Va
V
)
b
a
1.1 CLOCK INPUTS
Vb the internal TRI-STATE
buffer is disabled allowing the
CLK R pin to become the
clock input for the internal
clock level-shift stage. The
CLK R threshold level is now
2V above the voltage on the L.
Sh pin. The CLK R pin will be
compatible with TTL logic
levels when the LMF40 is
operated on split supplies with
the L. Sh pin connected to
system ground.
The LMF40 has a Schmitt-trigger inverting buffer which can
be used to construct a simple R/C oscillator. Pin 3 is con-
nected to Vb, making Pin 2 a low impedance output. The
oscillator’s frequency is nominally
1
e
f
CLK
b
b
b
a
a
b
V
V
V
V
V
t
CC
t
RC In
V
(1)
Ð#
J #
J(
CC
t
t
which is typically
1
j
f
CLK
1.37 RC
(1a)
e
for V
CC
Note that f
10V.
5
(8)
6
FILTER
OUT
The output of the low-pass
filter.
is dependent on the buffer’s threshold levels
CLK
as well as the resistor/capacitor tolerance (see Figure 1 ).
Schmitt-trigger threshold voltage levels can change signifi-
cantly causing the R/C oscillator’s frequency to vary greatly
from part to part.
AGND
The analog ground pin. This
pin sets the DC bias level for
the filter section and must be
tied to the system ground for
split supply operation or to
mid-supply for single supply
operation (see Section 1.2).
When tied to mid-supply this
pin should be well bypassed.
(10)
Where accurate cutoff frequency is required, an external
clock can be used to drive the CLK R input of the LMF40.
This input is TTL logic level compatible and also presents a
E
very light load to the external clock source ( 2 mA). With
split supplies and the level shift (L. Sh) tied to system
ground, the logic level is about 2V. (See the Pin Description
for L. Sh).
8
1.0 LMF40 Application Information (Continued)
1.2 POWER SUPPLY
As an example, with a source impedance of 10 kX the over-
all gain would be:
The LMF40 can be powered from a single supply or split
supplies. The split supply mode shown in Figure 2 is the
most flexible and easiest to implement. Supply voltages of
1 MX
e
e
b
0.99009 or 0.086 dB
A
V
a
10 kX
1 MX
g
g
5V to 7V enable the use of TTL or CMOS clock logic
Since the maximum overall gain error for the LMF40 is
s
2 kX the actual gain
levels. Figure 3 shows AGND resistor-biased to Va/2 for
single supply operation. In this mode only CMOS clock logic
levels can be used, and input signals should be capacitor-
coupled or biased near mid-supply.
@
a
error for this case would be 0.04 dB to 0.24 dB.
b
0.05, 0.15 dB
25 C with R
b
§
S
b
1.4 CUTOFF FREQUENCY RANGE
The filter’s cutoff frequency (f ) has a lower limit due to
c
1.3 INPUT IMPEDANCE
leakage currents through the internal switches draining the
charge stored on the capacitors. At lower clock frequencies
these leakage currents can cause millivolts of error. For ex-
ample:
The LMF40 low-pass filter input (FILTER IN) is not a high
impedance buffer input. This input is a switched-capacitor
resistor equivalent, and its effective impedance is inversely
proportional to the clock frequency. The equivalent circuit of
the filter’s input can be seen in Figure 4. The input capacitor
e
e
e
1 pA, C 1 pF
f
100 Hz, I
CLK
Leakage
charges to V during the first half of the clock period; dur-
IN
ing the second half the charge is transferred to the feed-
back capacitor. The total transfer of charge in one clock
1 pA
e
e
10 mV
V
1 pF (100 Hz)
The propagation delay in the logic and the settling time re-
quired to acquire a new voltage level on the capacitors limit
the filter’s accuracy at high clock frequencies. The ampli-
e
cycle is therefore Q
C
V
, and since current is defined
IN IN
as the flow of charge per unit time, the average input current
becomes
g
tude characteristic on 5V supplies will typically stay flat
until f exceeds 1.5 MHz and then peak at about 0.1 dB
e
I
Q/T
IN
CLK
at the corner frequency with a 2 MHz clock. As supply volt-
(where T equals one clock period) or
g
age drops to 2.5V, a shift in the f
/f ratio occurs which
c
CLK
C
V
IN IN
e
e
C
I
V f
IN IN CLK
will become noticeable when the clock frequency exceeds
500 kHz. The response of the LMF40 is still a good approxi-
mation of the ideal Butterworth low-pass characteristic
shown in Figure 5.
IN AVE
T
The equivalent input resistor (R ) then can be expressed
IN
as
V
1
IN
e
e
R
IN
2.0 Designing with the LMF40
I
C
f
IN CLK
IN
Given any low-pass filter specification, two equations will
come in handy in trying to determine whether the LMF40 will
do the job. The first equation determines the order of the
low-pass filter required to meet a given response specifica-
tion:
The input capacitor is 2 pF for the LMF40-50 and 1 pF for
the LMF40-100, so for the LMF40-100
12
12
10
c
c
c
1
10
1
10
1
10
c
e
e
e
R
IN
c
c
f
f
100
f
CLK
0.1A
0.1A
min
max
b
b
1)
[
log (10
]
and
1)/(10
e
n
11
11
10
c
c
c
(2)
5
10
5
10
1
10
2 log (f /f )
b
s
e
e
e
R
IN
c
f
f
50
f
c
where n is the order of the filter, A
min
band attenuation (in dB) desired at frequency f , and A
is the minimum stop-
CLK
c
is
s
max
for the LMF40-50. The above equation shows that for a
given cutoff frequency (f ), the input resistance of the
c
the passband ripple or attenuation (in dB) at cutoff frequen-
cy f (Note 15). If the result of this equation is greater than
b
4, more than one LMF40 will be required.
LMF40-50 is the same as that of the LMF40-100. The high-
er the clock-to-cutoff-frequency ratio, the greater equivalent
input resistance for a given clock frequency.
The attenuation at any frequency can be found by the fol-
lowing equation:
0.1A
This input resistance will form a voltage divider with the
). Since R is inversely propor-
Source IN
max
2n
b
1)(f/f ) dB
e
a
[
]
source impedance (R
Attn (f)
10 log
1
(10
(3)
b
tional to the cutoff frequency, operation at higher cutoff fre-
quencies will be more likely to attenuate the input signal
which would appear as an overall decrease in gain to the
output of the filter. Since the filter’s ideal gain is unity, the
overall gain is given by:
e
where n
4 for the LMF40.
2.1 A LOW-PASS DESIGN EXAMPLE
Suppose the amplitude response specification in Figure 6 is
given. Can the LMF40 be used? The order of the Butter-
worth approximation will have to be determined using (1):
R
IN
e
A
V
a
e
e
e
e
1 kHz
R
R
Source
A
18 dB, A
max
1.0 dB, f
2 kHz, and f
IN
min
s
b
If the LMF40-50 or the LMF40-100 were set up for a cutoff
frequency of 10 kHz the input impedance would be:
1.8
0.1
b
b
1)
[
log (10
]
1)/(10
e
e
3.95
n
2 log(2)
10
10
c
1
e
Since n can only take on integer values, n
4. Therefore
e
e
1 MX
R
IN
10 kHz
the LMF40 can be used. In general, if n is 4 or less a single
LMF40 can be utilized.
9
2.0 Designing with the LMF40 (Continued)
Likewise, the attenuation at f can be found using (3) with
e
Equation (4) will determine whether the order of the filter is
s
s
the above values and n
4:
adequate (n 4) while equation (5) can determine the actu-
al stopband attenuation and cutoff frequency (f ) necessary
c
0.1
8
e
a
b
1) (2 kHz/1 kHz)
[
10 log 1
]
Attn (2 kHz)
10
to obtain the desired frequency response. The design pro-
cedure would be identical to the one shown in Section 2.0.
e
18.28 dB
This result also meets the design specification given in Fig-
ure 6 again verifying that a single LMF40 section will be
adequate.
2.3 CHANGING CLOCK FREQUENCY
INSTANTANEOUSLY
The LMF40 responds well to an instantaneous change in
clock frequency. If the control signal in Figure 9 is low the
Since the LMF40’s cutoff frequency (f ), which corresponds
c
to a gain attenuation of 3.01 dB, was not specified in this
b
example, it needs to be calculated. Solving equation (3)
e
this signal goes high the clock frequency changes to 50 kHz
LMF40-50 has a 100 kHz clock making f
2 kHz; when
c
e
where f
f
c
as follows:
e
yielding f
1 kHz. As Figure 9 illustrates, the output signal
c
0.1(3.01 dB)
b
10
1
1/(2n)
changes quickly and smoothly in response to a sudden
change in clock frequency.
e
f
c
f
b
0.1A
max
b
(10
1)
Ð
(
0.301
0.1
b
The step response of the LMF40 in Figure 10 is dependent
10
1
1/8
e
e
1 kHz
on f . The LMF40 responds as a classical fourth-order But-
c
terworth low-pass filter.
b
10
1
Ð
(
1.184 kHz
2.4 ALIASING CONSIDERATIONS
e
ple for the LMF40-50 the clock frequency will have to be set
where f
f
/50 or f
/100. To implement this exam-
CLK
c
CLK
Aliasing effects have to be considered when input signal
frequencies exceed half the sampling rate. For the LMF40
e
e
e
to f
CLK
e
f
50(1.184 kHz)
100 (1.184 kHz)
59.2 kHz, or for the LMF40-100,
118.4 kHz.
this equals half the clock frequency (f
). When the input
CLK
CLK
signal contains a component at a frequency higher than half
the clock frequency f /2, as in Figure 11a, that compo-
2.2 CASCADING LMF40s
CLK
nent will be ‘‘reflected’’ about f
When a steeper stopband attenuation rate is required, two
LMF40s can be cascaded (Figure 7) yielding an 8th order
slope of 48 dB per octave. Because the LMF40 is a Butter-
worth filter and therefore has no ripple in its passband,
when LMF40s are cascaded the resulting filter also has no
ripple in its passband. Likewise the DC and passband gains
will remain at 1V/V. The resulting response is shown in Fig-
ure 8a.
/2 into the frequency
CLK
/2, as in Figure 11b. If this component is
range below f
CLK
within the passband of the filter and of large enough ampli-
tude it can cause problems. Therefore, if frequency compo-
nents in the input signal exceed f
/2 they must be attenu-
CLK
ated before being applied to the LMF40 input. The neces-
sary amount of attenuation will vary depending on system
requirements. In critical applications the signal components
above f
/2 will have to be attenuated at least to the fil-
In determining whether the cascaded LMF40s will yield a
filter that will meet a particular amplitude response specifi-
CLK
ter’s residual noise level.
cation, as above, equations (4) and (5) can be used, shown
below.
0.05A
min
0.05Amax
2
]
1) (f/f ) dB
b
b
b
1)
[
log (10,
]
1)/(10
e
n
2 log(f /f )
(4)
(5)
s
b
0.05A
max
e
a
b
[
Attn (f)
10 log
1
(10
e
where n
4 (the order of each filter).
1
e
f
b
b
a
a
b
V
V
V
V
t
CC
t
RC In
b
V
V
t
Ð#
J#
J(
CC
t
1
j
f
1.37 RC
e
(V
CC
10V)
TL/H/10557–7
FIGURE 1. Schmitt Trigger R/C Oscillator
10
2.0 Designing with the LMF40 (Continued)
V
V
V
I
I
C
TL/H/10557–8
TL/H/10557–9
(a)
(b)
FIGURE 2. Split Supply Operation with CMOS Level Clock (a), and TTL Level Clock (b)
TL/H/10557–10
FIGURE 3. Single Supply Operation. AGND Resistor Biased to Va/2
TL/H/10557–11
TL/H/10557–12
a) Equivalent Circuit for LMF40 Filter Input
b) Actual Circuit for LMF40 Filter Input
FIGURE 4. LMF40 Filter Input
11
2.0 Designing with the LMF40 (Continued)
TL/H/10557–13
TL/H/10557–14
TL/H/10557–15
FIGURE 5a. LMF40-100 Amplitude
g
Response with 5V Supplies
FIGURE 5b. LMF40-50 Amplitude
g
Response with 5V Supplies
FIGURE 5c. LMF40-100 Amplitude
g
Response with 2.5V Supplies
TL/H/10557–16
FIGURE 5d. LMF40-50 Amplitude
g
Response with 2.5V Supplies
TL/H/10557–17
FIGURE 6. Design Example Magnitude Response
Specification. The response of the filter design
must fall within the shaded area of the specification.
12
2.0 Designing with the LMF40 (Continued)
TL/H/10557–18
FIGURE 7. Cascading Two LMF40s
TL/H/10557–19
FIGURE 8a. One LMF40-50
vs Two LMF40-50s Cascaded
FIGURE 8b. Phase Response
of Two Cascaded LMF40-50s
TL/H/10557–21
TL/H/10557–20
FIGURE 10. LMF40-50 Input Step Response
FIGURE 9. LMF40-50 Abrupt Clock Frequency Change
13
2.0 Designing with the LMF40 (Continued)
TL/H/10557–22
TL/H/10557–23
(a) Input Signal Spectrum
(b)Output Signal Spectrum. Note that the input signal at
a
b
f causes an output signal to appear at f /2 f.
s
f /2
s
FIGURE 11. The phenomenon of aliasing in sampled-data systems. An input signal whose
frequency is greater than one-half the sampling frequency will cause an output to appear
e
at a frequency lower than one-half the sampling frequency. In the LMF40, f
f
.
s
CLK
14
Physical Dimensions inches (millimeters)
Order Number LMF40CMJ-50 or LMF40CMJ-100
NS Package Number J08A
Order Number LMF40CIWM-50 or LMF40CIWM-100
NS Package Number M14B
15
Physical Dimensions inches (millimeters) (Continued)
Order Number LMF40CIN-50, or LMF40CIN-100
NS Package Number N08E
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
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Fax:
(
49) 0-180-530 85 86
@
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Tel: (852) 2737-1600
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a
a
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(
(
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