概述
数据手册LMH6559_06 概述
High-Speed, Closed-Loop Buffer 高速，闭环缓冲
LMH6559_06 数据手册
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PDF下载July 2006
LMH6559
High-Speed, Closed-Loop Buffer
General Description
Features
n Closed-loop buffer
The LMH6559 is a high-speed, closed-loop buffer designed
for applications requiring the processing of very high fre-
quency signals. While offering a small signal bandwidth of
1750MHz, and an ultra high slew rate of 4580V/µs the
LMH6559 consumes only 10mA of quiescent current. Total
harmonic distortion into a load of 100Ω at 20MHz is −52dBc.
The LMH6559 is configured internally for a loop gain of one.
Input resistance is 200kΩ and output resistance is but 1.2Ω.
These characteristics make the LMH6559 an ideal choice for
the distribution of high frequency signals on printed circuit
boards. Differential gain and phase specifications of 0.06%
and 0.02˚ respectively at 3.58MHz make the LMH6559 well
suited for the buffering of video signals.
n 1750MHz small signal bandwidth
n 4580V/µs slew rate
n 0.06% / 0.02˚ differential gain/phase
n −52dBc THD at 20MHz
n Single supply operation (3V min.)
n 75mA output current
Applications
n Video switching and routing
n Test point drivers
n High frequency active filters
n Wideband DC clamping buffers
n High-speed peak detector circuits
n Transmission systems
The device is fabricated on National’s high-speed VIP10
process using National’s proven high performance circuit
architectures.
n Telecommunications
n Test equipment and instrumentation
Typical Schematic
20064133
© 2006 National Semiconductor Corporation
DS200641
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Wave Soldering (10 sec.)
Storage Temperature Range
Junction Temperature
260˚C
−65˚C to +150˚C
+150˚C
ESD Tolerance (Note 2)
Operating Ratings (Note 1)
Supply Voltage (V+ - V−)
Human Body Model
2000V
200V
3 - 10V
Machine Model
Temperature Range (Notes 5, 6)
−40˚C to +85˚C
Output Short Circuit Duration
Supply Voltage (V+ – V−)
Voltage at Input/Output Pins
Soldering Information
(Note 3), (Note 4)
13V
V+ +0.8V, V− −0.8V
Package Thermal Resistance (Notes 5, 6)
8-Pin SOIC
172˚C/W
235˚C/W
5-Pin SOT23
Infrared or Convection (20 sec.)
235˚C
5V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = +5V, V− = −5V, VO = VCM = 0V and RL = 100Ω to 0V.
Boldface limits apply at the temperature extremes.
Min
Typ
Max
Symbol
Parameter
Conditions
VO 0.5VPP
(Note 8)
(Note 7)
(Note 8)
Units
Frequency Domain Response
<
SSBW
GFN
Small Signal Bandwidth
1750
200
MHz
MHz
MHZ
%
<
<
Gain Flatness 0.1dB
VO 0.5VPP
FPBW
DG
Full Power Bandwidth (−3dB)
Differential Gain
VO = 2VPP (+10dBm)
RL = 150Ω to 0V,
f = 3.58 MHz
1050
0.06
DP
Differential Phase
RL = 150Ω to 0V,
f = 3.58 MHz
0.02
deg
Time Domain Response
tr
Rise Time
3.3V Step (20-80%)
0.4
0.5
9
ns
ns
tf
Fall Time
ts
Settling Time to 0.1%
Overshoot
3.3V Step
1V Step
ns
OS
SR
4
%
Slew Rate
(Note 10)
4580
V/µs
Distortion And Noise Performance
HD2
HD3
THD
en
2nd Harmonic Distortion
3rd Harmonic Distortion
Total Harmonic Distortion
Input-Referred Voltage Noise
1dB Compression point
Signal to Noise Ratio
VO = 2VPP, f = 20MHz
VO = 2VPP, f = 20MHz
VO = 2VPP, f = 20MHz
f = 1MHz
−58
−53
−52
5.7
dBc
dBc
dBc
nV/
CP
f = 10MHz
+23
89
dBm
dB
>
100kHz, BW = 5MHz,
SNR
f
VO = 350mVrms
Static, DC Performance
ACL
Small Signal Voltage Gain
VO = 100mVPP
RL = 100Ω to 0V
VO = 100mVPP
RL = 2kΩ to 0V
.97
.99
.996
.998
3
V/V
VOS
Input Offset Voltage
20
mV
µV/˚C
µA
25
TC VOS
IB
Temperature Coefficient Input
Offset Voltage
(Note 11)
(Note 9)
23
Input Bias Current
−10
−3
−14
TC IB
Temperature Coefficient Input
Bias Current
(Note 11)
−3.6
nA/˚C
www.national.com
2
5V Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = +5V, V− = −5V, VO = VCM = 0V and RL = 100Ω to 0V.
Boldface limits apply at the temperature extremes.
Min
(Note 8)
Typ
(Note 7)
1.2
Max
(Note 8)
Symbol
Parameter
Output Resistance
Conditions
Units
Ω
ROUT
RL = 100Ω to 0V, f = 100kHz
RL = 100Ω to 0V, f = 10MHz
1.3
PSRR
IS
Power Supply Rejection Ratio
Supply Current
VS
=
5V to VS
=
5.25V
48
63
dB
44
No Load
10
14
mA
17
Miscellaneous Performance
RIN
CIN
VO
Input Resistance
200
1.7
kΩ
Input Capacitance
Output Swing Positive
pF
RL = 100Ω to 0V
RL = 2kΩ to 0V
RL = 100Ω to 0V
RL = 2kΩ to 0V
3.20
3.18
3.55
3.54
3.45
V
3.65
−3.45
−3.65
Output Swing Negative
−3.20
−3.18
−3.55
−3.54
V
ISC
IO
Output Short Circuit Current
Linear Output Current
Sourcing: VIN = +VS, VO = 0V
Sinking: VIN = −VS, VO = 0V
Sourcing: VIN - VO = 0.5V
(Note 9)
−83
83
mA
mA
−50
−43
50
−74
Sinking: VIN - VO = −0.5V
(Note 9)
74
43
5V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2.
Boldface limits apply at the temperature extremes.
Min
Typ
Max
Symbol
Parameter
Conditions
VO 0.5VPP
(Note 8)
(Note 7)
(Note 8)
Units
Frequency Domain Response
<
SSBW
GFN
Small Signal Bandwidth
745
90
MHz
MHz
MHZ
%
<
<
Gain Flatness 0.1dB
VO 0.5VPP
FPBW
DG
Full Power Bandwidth (−3dB)
Differential Gain
VO = 2VPP (+10dBm)
RL = 150Ω to V+/2,
f = 3.58 MHz
485
0.29
DP
Differential Phase
RL = 150Ω to V+/2,
0.06
deg
f = 3.58 MHz
Time Domain Response
tr
Rise Time
2.3VPP Step (20-80%)
0.6
0.9
9.6
3
ns
ns
tf
Fall Time
ts
Settling Time to 0.1%
Overshoot
2.3V Step
1V Step
ns
OS
SR
%
Slew Rate
(Note 10)
2070
V/µs
Distortion And Noise Performance
HD2
HD3
THD
en
2nd Harmonic Distortion
3rd Harmonic Distortion
Total Harmonic Distortion
Input-Referred Voltage Noise
VO = 2VPP, f = 20MHz
VO = 2VPP, f = 20MHz
VO = 2VPP, f = 20MHz
f = 1MHz
−53
−56
−52
4.0
dBc
dBc
dBc
nV/
3
www.national.com
5V Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 5V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2.
Boldface limits apply at the temperature extremes.
Min
(Note 8)
Typ
(Note 7)
+7
Max
(Note 8)
Symbol
CP
SNR
Parameter
1dB Compression point
Signal to Noise Ratio
Conditions
Units
dBm
dB
f = 10MHz
>
f
100kHz, BW = 5MHz,
92
VO = 350mVrms
Static, DC Performance
ACL
Small Signal Voltage Gain
VO = 100mVPP
RL = 100Ω to V+/2
VO = 100mVPP
RL = 2kΩ to V+/2
.97
.99
.996
.998
1.52
23
V/V
VOS
Input Offset Voltage
12
mV
µV/˚C
µA
16
TC VOS
IB
Temperature Coefficient Input
Offset Voltage
(Note 11)
(Note 9)
Input Bias Current
−5
−2.7
1.6
−8
TC IB
ROUT
PSRR
IS
Temperature Coefficient Input
Bias Current
(Note 11)
nA/˚C
Output Resistance
RL = 100Ω to V+/2, f = 100kHz
RL = 100Ω to V+/2, f = 10MHz
VS = +5V to VS = +5.5V,
VIN = VS/2
1.4
1.6
68
Ω
Power Supply Rejection Ratio
Supply Current
48
dB
44
No Load
4.7
7
mA
8.5
Miscellaneous Performance
RIN
CIN
VO
Input Resistance
22
2.0
kΩ
Input Capacitance
Output Swing Positive
pF
RL = 100Ω to V+/2
RL = 2kΩ to V+/2
RL = 100Ω to V+/2
RL = 2kΩ to V+/2
3.80
3.75
3.94
3.92
3.88
V
3.98
1.12
1.03
Output Swing Negative
1.20
1.25
1.06
1.09
V
ISC
IO
Output short circuit Current
Linear Output Current
Sourcing: VIN = +VS, VO = V+/2
Sinking: VIN = −VS, VO = V+/2
Sourcing: VIN - VO = 0.5V
(Note 9)
−57
26
mA
mA
−50
−43
30
−64
Sinking: VIN - VO = −0.5V
(Note 9)
42
23
3V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 3V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2.
Boldface limits apply at the temperature extremes.
Min
Typ
Max
Symbol
Parameter
Conditions
VO 0.5VPP
(Note 8)
(Note 7)
(Note 8)
Units
Frequency Domain Response
<
SSBW
GFN
Small Signal Bandwidth
315
44
MHz
MHz
<
<
VO 0.5VPP
Gain Flatness 0.1dB
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4
3V Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 3V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2.
Boldface limits apply at the temperature extremes.
Min
(Note 8)
Typ
(Note 7)
265
Max
(Note 8)
Symbol
Parameter
Conditions
Units
FPBW
Full Power Bandwidth (−3dB)
VO = 1VPP (+4.5dBm)
MHZ
Time Domain Response
tr
Rise Time
1.0V Step (20-80%)
0.8
1.2
10
ns
ns
tf
Fall Time
ts
Settling Time to 0.1%
Overshoot
1V Step
ns
OS
SR
0.5V Step
(Note 10)
0
%
Slew Rate
770
V/µs
Distortion And Noise Performance
HD2
HD3
THD
en
2nd Harmonic Distortion
3rd Harmonic Distortion
Total Harmonic Distortion
Input-Referred Voltage Noise
1dB Compression point
Signal to Noise Ratio
VO = 2VPP, f = 20MHz
VO = 2VPP, f = 20MHz
VO = 2VPP, f = 20MHz
f = 1MHz
−74
−57
−56
3.9
+4
dBc
dBc
dBc
nV/
CP
f = 10MHz
dBm
dB
>
SNR
f
100kHz, BW = 5MHz,
92
VO = 350mVrms
Static, DC Performance
ACL
Small Signal Voltage Gain
VO = 100mVPP
RL = 100Ω to V+/2
VO = 100mVPP
RL = 2kΩ to V+/2
.97
.99
.995
.998
1
V/V
VOS
Input Offset Voltage
7
mV
µV/˚C
µA
9
TC VOS
IB
Temperature Coefficient Input
Offset Voltage
(Note 11)
(Note 9)
3.5
Input Bias Current
−3
−1.5
0.46
−3.5
TC IB
ROUT
PSRR
IS
Temperature Coefficient Input
Bias Current
(Note 11)
nA/˚C
Output Resistance
RL = 100Ω to V+/2, f = 100kHz
RL = 100Ω to V+/2, f = 10MHz
VS = +3V to VS = +3.5V,
VIN = V+/2
1.8
2.3
68
Ω
Power Supply Rejection Ratio
Supply Current
48
dB
46
No Load
2.4
3.5
mA
4.5
Miscellaneous Performance
RIN
CIN
VO
Input Resistance
23
2.3
kΩ
Input Capacitance
Output Swing Positive
pF
RL = 100Ω to V+/2
RL = 2kΩ to V+/2
RL = 100Ω to V+/2
RL = 2kΩ to V+/2
2.02
1.95
2.12
2.02
2.07
V
2.17
.930
.830
Output Swing Negative
.970
1.050
.880
V
.980
ISC
Output Short Circuit Current
Sourcing: VIN = +VS, VO = V+/2
Sinking: VIN = −VS, VO = V+/2
−32
15
mA
5
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3V Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 3V, V− = 0V, VO = VCM = V+/2 and RL = 100Ω to V+/2.
Boldface limits apply at the temperature extremes.
Min
(Note 8)
−20
Typ
(Note 7)
−28
Max
(Note 8)
Symbol
IO
Parameter
Conditions
Sourcing: VIN - VO = 0.5V
(Note 9)
Units
Linear Output Current
−13
mA
Sinking: VIN - VO = −0.5V
(Note 9)
12
17
8
Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150˚C.
Note 4: Short circuit test is a momentary test. See next note.
Note 5: The maximum power dissipation is a function of T
, θ , and T . The maximum allowable power dissipation at any ambient temperature is P =
A D
J(MAX) JA
(T
– T ) / θ . All numbers apply for packages soldered directly onto a PC board.
J(MAX)
A JA
Note 6: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of
the device such that T = T . There is no guarantee of parametric performance as indicated in the electrical tables under conditions of internal self-heating where
J
A
>
T
T . See Applications section for information on temperature de-rating of this device.
J
A
Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 8: All limits are guaranteed by testing or statistical analysis.
Note 9: Positive current corresponds to current flowing into the device.
Note 10: Slew rate is the average of the positive and negative slew rate.
Note 11: Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature change.
Connection Diagrams
8-Pin SOIC
5-Pin SOT23
20064134
20064135
Top View
Top View
Ordering Information
Package
Part Number
LMH6559MA
LMH6559MAX
LMH6559MF
LMH6559MFX
Package Marking
Transport Media
NSC Drawing
8-Pin SOIC
LMH6559MA
95 Units/Rail
M08A
2.5k Units Tape and Reel
1k Units Tape and Reel
3k Units Tape and Reel
5-Pin SOT23
B05A
MF05A
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6
Typical Performance Characteristics At TJ = 25˚C; V+ = +5V; V− = −5V; Unless otherwise speci-
fied.
Frequency Response
Frequency Response Over Temperature
20064101
20064132
Gain Flatness
Differential Gain and Phase
20064103
20064102
Differential Gain and Phase
Transient Response Positive
20064104
20064107
7
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Typical Performance Characteristics At TJ = 25˚C; V+ = +5V; V− = −5V; Unless otherwise
specified. (Continued)
Transient Response Negative
Transient Response Positive for Various VSUPPLY
20064108
20064106
@
Harmonic Distortion vs. VOUT 5MHz
Transient Response Negative for Various VSUPPLY
20064105
20064109
@
@
Harmonic Distortion vs. VOUT 20MHz
Harmonic Distortion vs. VOUT 10MHz
20064114
20064110
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8
Typical Performance Characteristics At TJ = 25˚C; V+ = +5V; V− = −5V; Unless otherwise
specified. (Continued)
THD vs. VOUT for Various Frequencies
Voltage Noise
20064113
20064111
Linearity VOUT vs. VIN
VOS vs. VSUPPLY for 3 Units
20064112
20064122
VOS vs. VSUPPLY for Unit 1
VOS vs. VSUPPLY for Unit 2
20064123
20064124
9
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Typical Performance Characteristics At TJ = 25˚C; V+ = +5V; V− = −5V; Unless otherwise
specified. (Continued)
VOS vs. VSUPPLY for Unit 3
IB vs. VSUPPLY (Note 9)
20064126
20064125
ROUT vs. Frequency
PSRR vs. Frequency
20064115
20064116
ISUPPLY vs. VSUPPLY
ISUPPLY vs. VIN
20064127
20064121
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10
Typical Performance Characteristics At TJ = 25˚C; V+ = +5V; V− = −5V; Unless otherwise
specified. (Continued)
VOUT vs. IOUT Sinking
VOUT vs. IOUT Sourcing
20064129
20064128
IO Sinking vs. VSUPPLY
IO Sourcing vs. VSUPPLY
20064131
20064130
@
Large Signal Pulse Response VS = 3V
Small Signal Pulse Response
20064117
20064118
11
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Typical Performance Characteristics At TJ = 25˚C; V+ = +5V; V− = −5V; Unless otherwise
specified. (Continued)
@
@
Large Signal Pulse Response VS = 10V
Large Signal Pulse Response VS = 5V
20064120
20064119
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12
Application Notes
USING BUFFERS
A buffer is an electronic device delivering current gain but no
voltage gain. It is used in cases where low impedances need
to be driven and more drive current is required. Buffers need
a flat frequency response and small propagation delay. Fur-
thermore, the buffer needs to be stable under resistive,
capacitive and inductive loads. High frequency buffer appli-
cations require that the buffer be able to drive transmission
lines and cables directly.
20064138
FIGURE 3.
In these three options it is seen that there is more than one
preferred method to reach an (end) point on a transmission
line. Until a certain point the designer can make his own
choice but the designer should keep in mind never to break
the rules about high frequency transport of signals. An ex-
planation follows in the text below.
IN WHAT SITUATION WILL WE USE A BUFFER?
In case of a signal source not having a low output impedance
one can increase the output drive capability by using a
buffer. For example, an oscillator might stop working or have
frequency shift which is unacceptably high when loaded
heavily. A buffer should be used in that situation. Also in the
case of feeding a signal to an A/D converter it is recom-
mended that the signal source be isolated from the A/D
converter. Using a buffer assures a low output impedance,
the delivery of a stable signal to the converter, and accom-
modation of the complex and varying capacitive loads that
the A/D converter presents to the OpAmp. Optimum value is
often found by experimentation for the particular application.
TRANSMISSION LINES
Introduction to transmission lines. The following is an over-
view of transmission line theory. Transmission lines can be
used to send signals from DC to very high frequencies. At all
points across the transmission line, Ohm’s law must apply.
For very high frequencies, parasitic behavior of the PCB or
cables comes into play. The type of cable used must match
the application. For example an audio cable looks like a coax
cable but is unusable for radar frequencies at 10GHz. In this
case one have to use special coax cables with lower attenu-
ation and radiation characteristics.
The use of buffers is strongly recommended for the handling
of high frequency signals, for the distribution of signals
through transmission lines or on pcb’s, or for the driving of
external equipment. There are several driving options:
•
•
•
Use one buffer to drive one transmission line (see Figure
1)
Normally a pcb trace is used to connect components on a
pcb board together. An important considerations is the
amount of current carried by these pcb traces. Wider pcb
traces are required for higher current densities and for ap-
plications where very low series resistance is needed. When
routed over a ground plane, pcb traces have a defined
Characteristic Impedance. In many design situations char-
acteristic impedance is not utilized. In the case of high
frequency transmission, however it is necessary to match
the load impedance to the line characteristic impedance
(more on this later). Each trace is associated with a certain
amount of series resistance and series inductance plus each
trace exhibits parallel capacitance to the ground plane. The
combination of these parameters defines the line’s charac-
teristic impedance. The formula with which we calculate this
impedance is as follows:
Use one buffer to drive to multiple points on one trans-
mission line (see Figure 2)
Use one buffer to drive several transmission lines each
driving a different receiver. (see Figure 3)
20064136
FIGURE 1.
√
= (L/C)
Z0
In this formula L and C are the value/unit length, and R is
assumed to be zero. C and L are unknown in many cases so
we have to follow other steps to calculate the Z0. The char-
acteristic impedance is a function of the geometry of the
cross section of the line. In (Figure 4) we see three cross
sections of commonly used transmission lines.
20064137
FIGURE 2.
13
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Application Notes (Continued)
20064139
FIGURE 4.
Z0 can be calculated by knowing some of the physical di-
mensions of the pcb line, such as pcb thickness, width of the
trace and er, relative dielectric constant. The formula given in
transmission line theory for calculating Z0 is as follows:
20064142
FIGURE 5.
Next, there will be a discussion of some issues associated
with the interaction of the transmission line at the source and
at the load.
(1)
er relative dielectric constant
Connecting A Load Using A Transmission Line
h
pcb height
In most cases, it is unrealistic to think that we can place a
driver or buffer so close to the load that we don’t need a
transmission line to transport the signal. The pcb trace
length between a driver and the load may affect operation
depending upon the operating frequency. Sometimes it is
possible to do measurements by connecting the DUT directly
to the analyzer. As frequencies become higher the short
lines from the DUT to the analyzer become long lines. When
this happens there is a need to use transmission lines. The
next point to examine is what happens when the load is
connected to the transmission line. When driving a load, it is
important to match the line and load impedance, otherwise
reflections will occur and this phenomena will distort the
signal. If a transient is applied at T = 0 (Figure 6, trace A) the
resultant waveform may be observed at the start point of the
transmission line. At this point (begin) on the transmission
line the voltage increases to (V) and the wave front travels
along the transmission line and arrives at the load at T = 10.
At any point across along the line I = V/Z0, where Z0 is the
impedance of the transmission line. For an applied transient
of 2V with Z0 = 50Ω the current from the buffer output stage
is 40mA. Many vintage opamps cannot deliver this level of
current because of an output current limitation of about
20mA or even less. At T = 10 the wave front arrives at the
load. Since the load is perfectly matched to the transmission
line all of the current traveling across the line will be ab-
sorbed and there will be no reflections. In this case source
and load voltages are exactly the same. When the load and
the transmission line have unequal values of impedance a
different situation results. Remember there is another basic
which says that energy cannot be lost. The power in the
transmission line is P = V2/R. In our example the total power
is 22/50 = 80mW. Assume a load of 75Ω. In that case a
power of 80mW arrives at the 75Ω load and causes a
voltage of the proper amplitude to maintain the incoming
power.
W trace width
th thickness of the copper
If we ignore the thickness of the copper in comparison to the
width of the trace then we have the following equation:
(2)
With this formula it is possible to calculate the line imped-
ance vs. the trace width. Figure 5 shows the impedance
associated with a given line width. Using the same formula it
is also possible to calculate what happens when er varies
over a certain range of values. Varying the er over a range of
1 to 10 gives a variation for the Characteristic Impedance of
about 40Ω from 80Ω to 38Ω. Most transmission lines are
designed to have 50Ω or 75Ω impedance. The reason for
that is that in many cases the pcb trace has to connect to a
cable whose impedance is either 50Ω or 75Ω. As shown er
and the line width influence this value.
www.national.com
14
cations, amplifier gain is set to 2 in order to realize an overall
gain of 1. Many operational amplifiers have a relatively flat
frequency response when set to a gain of two compared to
unity gain. In trace B it is seen that, if the voltage reaches the
end of the transmission line, the line is perfectly matched
and no reflections will occur. The end point voltage stays at
half the output voltage of the opamp or buffer.
Application Notes (Continued)
(3)
The voltage wavefront of 2.45V will now set about traveling
back over the transmission line towards the source, thereby
resulting in a reflection caused by the mismatch. On the
other hand if the load is less then 50Ω the backwards
traveling wavefront is subtracted from the incoming voltage
of 2V. Assume the load is 40Ω. Then the voltage across the
load is:
Driving More Than One Input
Another transmission line possibility is to route the trace via
several points along a transmission line (Figure 2) This is
only possible if care is taken to observe certain restrictions.
Failure to do so will result in impedance discontinuities that
will cause distortion of the signal. In the configuration of
Figure 2 there is a transmission line connected to the buffer
output and the end of the line is terminated with Z0. We have
seen in the section ’Connecting a load using a transmission
line’ that for the condition above, the signal throughout the
entire transmission line has the same value, that the value is
the nominal value initiated by the opamp output, and no
reflections occur at the end point. Because of the lack of
reflections no interferences will occur. Consequently the sig-
nal has every where on the line the same amplitude. This
allows the possibility of feeding this signal to the input port of
any device which has high ohmic impedance and low input
capacitance. In doing so keep in mind that the transient
arrives at different times at the connected points in the
transmission line. The speed of light in vacuum, which is
about 3 * 108 m/sec, reduces through a transmission line or
a cable down to a value of about 2 * 108 m/sec. The distance
the signal will travel in 1ns is calculated by solving the
following formula:
(4)
This voltage is now traveling backwards through the line
toward the start point. In the case of a sinewave interfer-
ences develop between the incoming waveform and the
backwards-going reflections, thus distorting the signal. If
there is no load at all at the end point the complete transient
of 2V is reflected and travels backwards to the beginning of
the line. In this case the current at the endpoint is zero and
the maximum voltage is reflected. In the case of a short at
the end of the line the current is at maximum and the voltage
is zero.
S = V*t
Where
S = distance
V = speed in the cable
t = time
This calculation gives the following result: s = 2*108 * 1*10−9
= 0.2m
That is for each nanosecond the wave front shifts 20cm over
the length of the transmission line. Keep in mind that in a
distance of just 2cm the time displacement is already 100ps.
Using Serial Termination To More Than One
Transmission Line
Another way to reach several points via a transmission line is
to start several lines from one buffer output (see Figure 3).
This is possible only if the output can deliver the needed
current into the sum of all transmission lines. As can be seen
in this figure there is a series termination used at the begin-
ning of the transmission line and the end of the line has no
termination. This means that only the signal at the endpoint
is usable because at all other points the reflected signal will
cause distortion over the line. Only at the endpoint will the
measured signal be the same as at the startpoint. Referring
to Figure 6 trace C, the signal at the beginning of the line has
a value of V/2 and at T = 0 this voltage starts traveling
towards the end of the transmission line. Once at the end-
point the line has no termination and 100% reflection will
occur. At T = 10 the reflection causes the signal to jump to 2V
and to start traveling back along the line to the buffer (see
Figure 6 trace D). Once the wavefront reaches the series
termination resistor, provided the termination value is Z0, the
wavefront undergoes total absorption by the termination.
This is only true if the output impedance of the buffer/driver
is low in comparison to the characteristic impedance Z0. At
20064145
FIGURE 6.
Using Serial And Parallel Termination
Many applications, such as video, use a series resistance
between the driver and the transmission line (see Figure 1).
In this case the transmission line is terminated with the
characteristic impedance at both ends of the line. See Figure
6 trace B. The voltage traveling through the transmission line
is half the voltage seen at the output of the buffer, because
the series resistor in combination with Z0 forms a two-to-one
voltage divider. The result is a loss of 6dB. For video appli-
15
www.national.com
As calculated before in the section ’Driving more than one
input’ the signal travels 20cm/ns so in 5ns this distance
indicated distance is 1m. So this example is easily verified.
Application Notes (Continued)
this moment the voltage in the whole transmission line has
the nominal value of 2V (see Figure 6 trace E). If the three
transmission lines each have a different length the particular
point in time at which the voltage at the series termination
resistor jumps to 2V is different for each case. However, this
transient is not transferred to the other lines because the
output of the buffer is low and this transient is highly attenu-
ated by the combination of the termination resistor and the
output impedance of the buffer. A simple calculation illus-
trates the point. Assume that the output impedance is 5Ω.
For the frequency of interest the attenuation is VB/VA = 55/5
= 11, where A and B are the points in Figure 3. In this case
the voltage caused by the reflection is 2/11 = 0.18V. This
voltage is transferred to the remaining transmission lines in
sequence and following the same rules as before this volt-
age is seen at the end points of those lines. The lower the
output resistance the higher the decoupling between the
different lines. Furthermore one can see that at the endpoint
of these transmission lines there is a normal transient equal
to the original transient at the beginning point. However at all
other points of the transmission line there is a step voltage at
different distances from the startpoint depending at what
point this is measured (see trace D).
APPLYING A CAPACITIVE LOAD
The assumption of pure resistance for the purpose of con-
necting the output stage of a buffer or opamp to a load is
appropriate as a first approximation. Unfortunately that is
only a part of the truth. Associated with this resistor is a
capacitor in parallel and an inductor in series. Any capaci-
tance such as CL-1 which is connected directly to the output
stage is active in the loop gain as seen in Figure 8. Output
capacitance, present also at the minus input in the case of a
buffer, causes an increasing phase shift leading to instability
or even oscillation in the circuit.
Measuring The Length Of A Transmission Line
20064148
An open transmission line can be used to measure the
length of a particular transmission line. As can be seen in
Figure 7 the line of interest has a certain length. A transient
is applied at T = 0 and at that point in time the wavefront
starts traveling with an amplitude of V/2 towards the end of
the line where it is reflected back to the startpoint.
FIGURE 8.
Unfortunately the leads of the output capacitor also contain
series inductors which become more and more important at
high frequencies. At a certain frequency this series capacitor
and inductor forms an LC combination which becomes se-
ries resonant. At the resonant frequency the reactive com-
ponent vanishes leaving only the ohmic resistance (R-1 or
R-2) of the series L/C combination. (see Figure 9).
20064146
FIGURE 7.
20064149
To calculate the length of the line it is necessary to measure
immediately after the series termination resistor. The voltage
at that point remains at half nominal voltage, thus V/2, until
the reflection returns and the voltage jumps to V. During an
interval of 5ns the signal travels to the end of the line where
the wave front is reflected and returns to the measurement
point. During the time interval when the wavefront is travel-
ing to the end of the transmission line and back the voltage
has a value of V/2. This interval is 10ns. The length can be
calculated with the following formula: S = (V*T)/2
FIGURE 9.
Consider a frequency sweep over the entire spectrum for
which the LMH6559 high frequency buffer is active. In the
first instance peaking occurs due to the parasitic capaci-
tance connected at the load whereas at higher frequencies
the effects of the series combination of L and C become
noticeable. This causes a distinctive dip in the output fre-
quency sweep and this dip varies depending upon the par-
ticular capacitor as seen in Figure 10.
(5)
www.national.com
16
USING GROUND PLANES
Application Notes (Continued)
The use of ground planes is recommended both for provid-
ing a low impedance path to ground (or to one of the other
supply voltages) and also for forming effective controlled
impedance transmission lines for the high frequency signal
flow on the board. Multilayer boards often make use of inner
conductive layers for routing supply voltages. These supply
voltage layers form a complete plane rather than using dis-
crete traces to connect the different points together for the
specified supply. Signal traces on the other hand are routed
on outside layers both top and bottom. This allows for easy
access for measurement purposes. Fortunately, only very
high density boards have signal layers in the middle of the
board. In an earlier section, the formula for Z0 was derived
as:
(6)
The width of a trace is determined by the thickness of the
board. In the case of a multilayer board the thickness is the
space between the trace and the first supply plane under this
trace layer. By common practice, layers do not have to be
evenly divided in the construction of a pcb. Refer to Figure
12. The design of a transmission line design over a pcb is
based upon the thickness of the different internal layers and
the er of the board material. The pcb manufacturer can
supply information about important specifications. For ex-
ample, a nominal 1.6mm thick pcb produces a 50Ω trace for
a calculated width of 2.9mm. If this layer has a thickness of
0.35mm and for the same er, the trace width for 50Ω should
be of 0.63mm, as calculated from Equation 7, a derivation
from Equation 6.
20064150
FIGURE 10.
To minimize peaking due to CL a series resistor for the
purpose of isolation from the output stage should be used. A
low valued resistor will minimize the influence of such a load
capacitor. In a 50Ω system as is common in high frequency
circuits a 50Ω series resistor is often used. Usage of the
series resistor, as seen in Figure 11 eliminates the peaking
but not the dip. The dip will vary with the particular capacitor.
Using a resistor in series with a capacitor creates in a single
pole situation a 6dB/oct rolloff. However, at high frequencies
the internal inductance is appreciable and forms a series LC
combination with the capacitor. Choice of a higher valued
resistor, for example 500 to 1kΩ, and a capacitor of hun-
dreds of pF’s provides the expected response at lower fre-
quencies.
(7)
20064154
FIGURE 12.
Using a trace over a ground plane has big advantages over
the use of a standard single or double sided board. The main
advantage is that the electric field generated by the signal
transported over this trace is fixed between the trace and the
ground plane e.g. there is almost no possibility of radiation
(seeFigure 13).
20064151
FIGURE 11.
17
www.national.com
Careful attention to power line distribution leads to improved
overall circuit performance. This is especially valid for analog
circuits which are more sensitive to spurious noise and other
unwanted signals.
Application Notes (Continued)
20064155
FIGURE 13.
This effect works to both sides because the circuit will not
generate radiation but the circuit is also not sensible if ex-
posed to a certain radiation level. The same is also notice-
able when placing components flat on the printed circuit
board. Standard through hole components when placed up-
right can act as an antenna causing an electric field which
could be picked up by a nearby upright component. If placed
directly at the surface of the pcb this influence is much lower.
20064157
FIGURE 15.
The Effect Of Variation For er
As demonstrated in Figure 15 the power lines are routed
from both sides on the pcb. In this case a current loop is
created as indicated by the dotted line. This loop can act as
an antenna for high frequency signals which makes the
circuit sensitive to RF radiation. A better way to route the
power traces can be seen in the following setup. (see Figure
16)
When using pcb material the er has a certain shift over the
used frequency spectrum, so if necessary to work with very
accurate trace impedances one must taken into account for
which frequency region the design has to be functional.
Figure 14 (http://www.isola.de) gives an example what the
drift in er will be when using the pcb material produced by
Isola. If working at frequencies of 100MHz then a 50Ω trace
has a width of 3.04mm for standard 1.6mm FR4 pcb mate-
rial, and the same trace needs a width of 3.14mm. for
frequencies around 10GHz.
20064158
FIGURE 16.
20064156
In this arrangement the power lines have been routed in
order to avoid ground loops and to minimize sensitivity to
noise etc. The same technique is valid when routing a high
frequent signal over a board which has no ground plane. In
that case is it good practice to route the high frequency
signal alongside a ground trace. A still better way to create a
pcb carrying high frequency signals is to use a pcb with a
ground plane or planes.
FIGURE 14.
Routing Power Traces
Power line traces routed over a pcb should be kept together
for best practice. If not a ground loop will occur which may
cause more sensitivity to radiation. Also additional ground
trace length may lead to more ringing on digital signals.
www.national.com
18
If the overall density becomes too high it is better to make a
design which contains additional metal layers such that the
ground planes actually function as ground planes. The costs
for such a pcb are increased but the payoff is in overall
effectiveness and ease of design.
Application Notes (Continued)
Discontinuities In A Ground Plane
A ground plane with traces routed over this plane results in
the build up of an electric field between the trace and the
ground plane as seen in Figure 13. This field is build up over
the entire routing of the trace. For the highest performance
the ground plane should not be interrupted because to do so
will cause the field lines to follow a roundabout path. In
Figure 17 it was necessary to interrupt the ground plane with
a crossing trace. This interruption causes the return current
to follow a longer route than the signal path follows to
overcome the discontinuity.
Ground Planes At Top And Bottom Layer Of A PCB
In addition to the bottom layer ground plane another useful
practice is to leave as much copper as possible at the top
layer. This is done to reduce the amount of copper to be
removed from the top layer in the chemical process. This
causes less pollution of the chemical baths allowing the
manufacturer to make more pcb’s with a certain amount of
chemicals. Connecting this upper copper to ground provides
additional shielding and signal performance is enhanced.
For lower frequencies this is specifically true. However, at
higher frequencies other effects become more and more
important such that unwanted coupling may result in a re-
duction in the bandwidth of a circuit. In the design of a test
circuit for the LMH6559 this effect was clearly noticeable and
the useful bandwidth was reduced from 1500MHz to around
850MHz.
20064159
FIGURE 17.
If needed it is possible to bypass the interruption with traces
that are parallel to the signal trace in order to reduce the
negative effects of the discontinuity in the ground plane. In
doing so, the current in the ground plane closely follows the
signal trace on the return path as can be seen in Figure 18.
Care must be taken not to place too many traces in the
ground plane or the ground plane effectively vanishes such
that even bypasses are unsuccessful in reducing negative
effects.
20064161
FIGURE 19.
As can be seen in Figure 19 the presence of a copper field
close to the transmission line to and from the buffer causes
unwanted coupling effects which can be seen in the dip at
about 850MHz. This dip has a depth of about 5dB for the
case when all of the unused space is filled with copper. In
case of only one area being filled with copper this dip is
about 9dB.
PCB Board Layout And Component Selection
Sound practice in the area of high frequency design requires
that both active and passive components be used for the
purposes for which they were designed. It is possible to
amplify signals at frequencies of several hundreds of MHz
using standard through hole resistors. Surface mount de-
vices, however, are better suited for this purpose. Surface
mount resistors and capacitors are smaller and therefore
parasitics are of lower value and therefore have less influ-
ence on the properties of the amplifier. Another important
issue is the pcb itself, which is no longer a simple carrier for
all the parts and a medium to interconnect them. The pcb
board becomes a real component itself and consequently
contributes its own high frequency properties to the overall
performance of the circuit. Sound practice dictates that a
20064160
FIGURE 18.
19
www.national.com
Application Notes (Continued)
Device
Package
Evaluation Board
Part Number
CLC730245
design have at least one ground plane on a pcb which
provides a low impedance path for all decoupling capacitors
and other ground connections. Care should be taken espe-
cially that on- board transmission lines have the same im-
pedance as the cables to which they are connected - 50Ω for
most applications and 75Ω in case of video and cable TV
applications. Such transmission lines usually require much
wider traces on a standard double sided PCB board than
needed for a ’normal’ trace. Another important issue is that
inputs and outputs must not ’see’ each other. This occurs if
inputs and outputs are routed together over the pcb with only
a small amount of physical separation, particularly when
there is a high differential in signal level between them.
Furthermore components should be placed as flat and low
as possible on the surface of the PCB. For higher frequen-
cies a long lead can act as a coil, a capacitor or an antenna.
A pair of leads can even form a transformer. Careful design
of the pcb avoids oscillations or other unwanted behaviors.
For ultra high frequency designs only surface mount compo-
nents will give acceptable results. (for more information see
OA-15).
LMH6559MA
LMH6559MAX
LMH6559MF
LMH6559MFX
SOIC-8
SOIC-8
CLC730245
SOT23-5
SOT23-5
CLC730136
CLC730136
These free evaluation boards are shipped when a device
sample request is placed with National Semiconductor.
POWER SEQUENCING OF THE LMH6559
Caution should be exercised in applying power to the
LMH6559. When the negative power supply pin is left float-
ing it is recommended that other pins, such as positive
supply and signal input should also be left unconnected. If
the ground is floating while other pins are connected the
input circuitry is effectively biased to ground, with a mostly
low ohmic resistor, while the positive power supply is ca-
pable of delivering significant current through the circuit. This
causes a high input bias current to flow which degrades the
input junction. The result is an input bias current which is out
of specification. When using inductive relays in an applica-
tion care should be taken to connect first both power con-
nections before connecting the bias resistor to the input.
NSC suggests the following evaluation boards as a guide for
high frequency layout and as an aid in device testing and
characterization.
www.national.com
20
Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin SOIC
NS Package Number M08A
5-Pin SOT23
NS Package Number MF05A
21
www.national.com
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances
and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at:
www.national.com/quality/green.
Lead free products are RoHS compliant.
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Support Center
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Fax: +49 (0) 180-530 85 86
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LMH6559_06 相关器件
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| LMH6560 | NSC | Quad, High-Speed, Closed-Loop Buffer | 获取价格 |
|
| LMH6560MA | NSC | Quad, High-Speed, Closed-Loop Buffer | 获取价格 |
|
| LMH6560MA/NOPB | TI | 暂无描述 | 获取价格 |
|
| LMH6560MAX | NSC | Quad, High-Speed, Closed-Loop Buffer | 获取价格 |
|
| LMH6560MAX/NOPB | TI | BUFFER AMPLIFIER, PDSO14, SOIC-14 | 获取价格 |
|
| LMH6560MT | NSC | Quad, High-Speed, Closed-Loop Buffer | 获取价格 |
|
| LMH6560MT/NOPB | TI | BUFFER AMPLIFIER, PDSO14, TSSOP-14 | 获取价格 |
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| LMH6560MTX | NSC | Quad, High-Speed, Closed-Loop Buffer | 获取价格 |
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| LMH6560_04 | NSC | Quad, High-Speed, Closed-Loop Buffer | 获取价格 |
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