LMH6618 [NSC]
130 MHz, 1.25 mA Rail-to-Rail Input and Output Operational Amplifier with Shutdown; 130兆赫， 1.25毫安轨至轨输入和输出运算放大器，带有关断
| 型号： | LMH6618 |
| 厂家： | 
National Semiconductor |
| 描述： | 130 MHz, 1.25 mA Rail-to-Rail Input and Output Operational Amplifier with Shutdown |
| 文件： | 总26页 (文件大小：1126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2007
LMH6618
130 MHz, 1.25 mA Rail-to-Rail Input and Output Operational
Amplifier with Shutdown
General Description
Features
The LMH6618 is a 130 MHz rail-to-rail input and output am-
plifier designed for ease of use in a wide range of applications
requiring high speed, low supply current, low noise, and the
ability to drive complex ADC and video loads. The operating
voltage range extends from 2.7V to 11V and the supply cur-
rent is typically 1.25 mA at 5V.
VS = 5V, RL = 1 kΩ, TA = 25°C and AV = +1, unless otherwise
specified.
Operating voltage range
Supply current
2.7V to 11V
1.25 mA
130 MHz
55 V/µs
90 ns
■
■
■
■
■
■
■
■
■
■
■
Small signal bandwidth
Slew rate
The amplifier’s voltage feedback design topology provides
balanced inputs and high open loop gain for ease of use and
accuracy in applications such as active filter design. Offset
voltage is typically 0.1 mV and settling time to 0.01% is 120
ns which combined with an 80 dBc SFDR at 1 MHz makes
the part suitable for use as an input buffer for popular 10-bit
and 12-bit mega-sample ADCs.
Settling time to 0.1%
Settling time to 0.01%
SFDR (f = 1 MHz, AV = +1, VOUT = 2 VPP
0.1 dB bandwidth (AV = +2)
Low voltage noise
120 ns
80 dBc
15 MHz
10 nV/√Hz
)
Industrial temperature grade
Rail-to-Rail input and output
−40°C to +125°C
The input common mode range extends 200 mV beyond the
supply rails. The output swings to within 270 mV of the supply
rails for a 150Ω load and 83 mV of the supply rail for a 1 kΩ Applications
load providing true single supply operation and maximum sig-
nal dynamic range on low power rails. The amplifier output
will source and sink 35 mA and drive up to 15 pF loads without
the need for external compensation.
ADC driver
■
DAC buffer
■
■
■
■
■
■
Active filters
High speed sensor amplifier
Current sense amplifier
Portable video
The LMH6618 has an active low disable pin which reduces
the supply current to 72 µA and is offered in the space saving
6-Pin TSOT23 package. The LMH6618 is available with a
−40°C to +125°C extended industrial temperature grade.
STB, TV video amplifier
Typical Application
20195829
WEBENCH® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation
201958
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Supply Voltage (VS = V+ – V−)
Junction Temperature (Note 3)
12V
150°C max
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings (Note 1)
Supply Voltage (VS = V+ – V−)
2.7V to 11V
−40°C to +125°C
ESD Tolerance (Note 2)
Human Body Model
Ambient Temperature Range (Note 3)
For input pins only
For all other pins
Machine Model
2000V
2000V
200V
Package Thermal Resistance (θJA
6-Pin TSOT23
)
231°C/W
+3V Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = +25°C,
V+ = 3V, V− = 0V, DISABLE = 3V, VCM = VO = V+/2, AV = +1 (RF = 0Ω), otherwise RF = 2 kΩ for AV ≠ +1, RL = 1 kΩ || 5 pF.
Boldface Limits apply at temperature extremes. (Note 4)
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Frequency Domain Response
SSBW
–3 dB Bandwidth Small Signal
120
56
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
MHz
MHz
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
GBW
Gain Bandwidth
55
71
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
LSBW
−3 dB Bandwidth Large Signal
13
13
1.5
15
AV = 1, RL = 1 kΩ, VOUT = 2 VPP
AV = 2, RL = 150Ω, VOUT = 2 VPP
AV = 1, CL = 5 pF
MHz
Peak
Peaking
dB
0.1
0.1 dB Bandwidth
AV = 2, VOUT = 0.5 VPP
,
MHz
dBBW
RF = RG = 825Ω
DG
Differential Gain
AV = +2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
0.1
0.1
%
DP
Differential Phase
AV = +2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
deg
Time Domain Response
tr/tf
Rise & Fall Time
Slew Rate
2V Step, AV = 1
2V Step, AV = 1
2V Step, AV = −1
2V Step, AV = −1
36
46
ns
SR
36
V/μs
ts_0.1
ts_0.01
0.1% Settling Time
0.01% Settling Time
90
ns
120
Noise and Distortion Performance
SFDR
Spurious Free Dynamic Range
100
80
58
10
1
fC = 100 kHz, VOUT= 2 VPP, RL = 1 kΩ
fC = 1 MHz, VOUT = 2 VPP, RL = 1 kΩ
fC = 5 MHz, VOUT = 2 VPP, RL = 1 kΩ
f = 100 kHz
dBc
en
in
Input Voltage Noise
Input Current Noise
nV/
pA/
f = 100 kHz
Input, DC Performance
VOS
Input Offset Voltage
VCM = 0.5V (pnp active)
VCM = 2.5V (npn active)
0.1
0.8
±0.6
±1.0
mV
TCVOS
IB
Input Offset Voltage Average
Drift
(Note 5)
μV/°C
Input Bias Current
VCM = 0.5V (pnp active)
VCM = 2.5V (npn active)
−1.4
+1.0
0.01
1.5
−2.6
+1.8
μA
IO
Input Offset Current
Input Capacitance
Input Resistance
±0.27
μA
pF
CIN
RIN
8
MΩ
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2
Symbol
Parameter
Condition
DC, CMRR ≥ 65 dB
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
CMVR
CMRR
Input Voltage Range
−0.2
78
3.2
V
Common Mode Rejection Ratio VCM Stepped from −0.1V to 1.4V
96
107
98
dB
VCM Stepped from 2.0V to 3.1V
81
RL = 1 kΩ to V+/2
RL = 150Ω to V+/2
AOL
Open Loop Gain
dB
82
Output DC Characteristics
RL = 1 kΩ to V+/2
RL =150Ω to V+/2
RL = 1 kΩ to V+/2
RL =150Ω to V+/2
RL = 150Ω to V−
VO
Output Swing High
(Voltage from V+ Supply Rail)
56
62
50
160
60
172
198
Output Swing Low
(Voltage from V− Supply Rail)
66
74
mV
170
29
184
217
39
43
IOUT
RO
Linear Output Current
Output Resistance
VOUT = V+/2 (Note 6)
f = 1 MHz
±25
2.0
±35
mA
0.17
Ω
Enable Pin Operation
Enable High Voltage Threshold Enabled
Enable Pin High Current VDISABLE = 3V
Enable Low Voltage Threshold Disabled
V
µA
V
0.04
1.0
Enable Pin Low Current
Turn-On Time
VDISABLE = 0V
1
µA
ns
ns
Ton
Toff
25
90
Turn-Off Time
Power Supply Performance
PSRR
IS
Power Supply Rejection Ratio DC, VCM = 0.5V, VS = 2.7V to 11V
84
104
1.2
dB
mA
μA
Supply Current
1.5
1.7
RL = ∞
ISD
Disable Shutdown Current
DISABLE = 0V
59
85
+5V Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = +25°C,
V+ = 5V, V− = 0V, DISABLE = 5V, VCM = VO = V+/2, AV = +1 (RF = 0Ω), otherwise RF = 2 kΩ for AV ≠ +1, RL = 1 kΩ || 5 pF.
Boldface Limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Frequency Domain Response
SSBW
–3 dB Bandwidth Small Signal
130
53
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
MHz
MHz
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
GBW
Gain Bandwidth
54
64
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
LSBW
−3 dB Bandwidth Large Signal
15
15
0.5
15
AV = 1, RL = 1 kΩ, VOUT = 2 VPP
AV = 2, RL = 150Ω, VOUT = 2 VPP
AV = 1, CL = 5 pF
MHz
Peak
Peaking
dB
0.1
0.1 dB Bandwidth
AV = 2, VOUT = 0.5 VPP
,
MHz
dBBW
RF = RG = 1 kΩ
DG
Differential Gain
AV = +2, 4.43 MHz, 0.6V < VOUT < 2V,
0.1
%
RL = 150Ω to V+/2
3
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Symbol
Parameter
Differential Phase
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
DP
AV = +2, 4.43 MHz, 0.6V < VOUT < 2V,
0.1
deg
RL = 150Ω to V+/2
Time Domain Response
tr/tf
Rise & Fall Time
Slew Rate
2V Step, AV = 1
2V Step, AV = 1
2V Step, AV = −1
2V Step, AV = −1
30
ns
SR
44
55
90
V/μs
ts_0.1
ts_0.01
0.1% Settling Time
0.01% Settling Time
ns
120
Distortion and Noise Performance
SFDR
Spurious Free Dynamic Range
100
80
58
10
1
fC = 100 kHz, VOUT = 2 VPP, RL = 1 kΩ
fC = 1 MHz, VOUT = 2 VPP, RL = 1 kΩ
fC = 5 MHz, VO = 2 VPP, RL = 1 kΩ
f = 100 kHz
dBc
en
in
Input Voltage Noise
Input Current Noise
nV/
pA/
f = 100 kHz
Input, DC Performance
VOS
Input Offset Voltage
VCM = 0.5V (pnp active)
VCM = 4.5V (npn active)
0.1
0.8
±0.6
±1.0
mV
TCVOS
IB
Input Offset Voltage Average
Drift
(Note 5)
µV/°C
Input Bias Current
VCM = 0.5V (pnp active)
VCM = 4.5V (npn active)
−1.5
+1.0
0.01
1.5
−2.4
+1.9
μA
IO
Input Offset Current
Input Capacitance
Input Resistance
±0.26
μA
pF
CIN
RIN
8
MΩ
CMVR
CMRR
Input Voltage Range
−0.2
81
5.2
V
DC, CMRR ≥ 65 dB
Common Mode Rejection Ratio VCM Stepped from −0.1V to 3.4V
98
108
100
83
dB
dB
VCM Stepped from 4.0V to 5.1V
84
RL = 1 kΩ to V+/2
RL = 150Ω to V+/2
AOL
Open Loop Gain
Output DC Characteristics
RL = 1 kΩ to V+/2
RL =150Ω to V+/2
RL = 1 kΩ to V+/2
RL =150Ω to V+/2
RL = 150Ω to V−
VO
Output Swing High
(Voltage from V+ Supply Rail)
73
82
60
230
75
255
295
Output Swing Low
(Voltage from V− Supply Rail)
83
96
mV
250
32
270
321
43
45
IOUT
RO
Linear Output Current
Output Resistance
VOUT = V+/2 (Note 6)
f = 1 MHz
±25
3.0
±35
mA
0.17
Ω
Enable Pin Operation
Enable High Voltage Threshold Enabled
Enable Pin High Current VDISABLE = 5V
Enable Low Voltage Threshold Disabled
V
µA
V
1.2
2.0
Enable Pin Low Current
Turn-On Time
VDISABLE = 0V
2.5
25
90
µA
ns
ns
Ton
Toff
Turn-Off Time
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4
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Power Supply Performance
PSRR
IS
Power Supply Rejection Ratio
DC, VCM = 0.5V, VS = 2.7V to 11V
84
104
dB
mA
μA
Supply Current
1.25
1.5
1.7
RL = ∞
ISD
Disable Shutdown Current
DISABLE = 0V
72
105
±5V Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TJ = +25°C,
V+ = 5V, V− = −5V, DISABLE = 5V, VCM = VO = 0V, AV = +1 (RF = 0Ω), otherwise RF = 2 kΩ for AV ≠ +1, RL = 1 kΩ || 5 pF.
Boldface Limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Frequency Domain Response
SSBW
–3 dB Bandwidth Small Signal
140
53
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
MHz
MHz
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
GBW
Gain Bandwidth
54
65
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
LSBW
−3 dB Bandwidth Large Signal
16
15
AV = 1, RL = 1 kΩ, VOUT = 2 VPP
AV = 2, RL = 150Ω, VOUT = 2 VPP
AV = 1, CL = 5 pF
MHz
Peak
Peaking
0.05
15
dB
0.1
0.1 dB Bandwidth
AV = 2, VOUT = 0.5 VPP
,
MHz
dBBW
RF = RG = 1.21 kΩ
DG
Differential Gain
AV = +2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
0.1
0.1
%
DP
Differential Phase
AV = +2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
deg
Time Domain Response
tr/tf
Rise & Fall Time
Slew Rate
2V Step, AV = 1
2V Step, AV = 1
2V Step, AV = −1
2V Step, AV = −1
30
57
ns
SR
45
V/μs
ts_0.1
ts_0.01
0.1% Settling Time
0.01% Settling Time
90
ns
120
Noise and Distortion Performance
SFDR
Spurious Free Dynamic Range
100
80
58
10
1
fC = 100 kHz, VOUT = 2 VPP, RL = 1 kΩ
fC = 1 MHz, VOUT = 2 VPP, RL = 1 kΩ
fC = 5 MHz, VOUT = 2 VPP, RL = 1 kΩ
f = 100 kHz
dBc
en
in
Input Voltage Noise
Input Current Noise
nV/
pA/
f = 100 kHz
Input DC Performance
VOS
Input Offset Voltage
VCM = −4.5V (pnp active)
VCM = 4.5V (npn active)
0.1
0.9
±0.6
±1.0
mV
TCVOS
IB
Input Offset Voltage Average
Drift
(Note 5)
µV/°C
Input Bias Current
VCM = −4.5V (pnp active)
VCM = 4.5V (npn active)
−1.5
+1.0
0.01
1.5
−2.4
+1.9
μA
IO
Input Offset Current
Input Capacitance
Input Resistance
±0.26
μA
pF
CIN
RIN
8
MΩ
CMVR
Input Voltage Range
−5.2
5.2
V
DC, CMRR ≥ 65 dB
5
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Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
CMRR
Common Mode Rejection Ratio VCM Stepped from −5.1V to 3.4V
VCM Stepped from 4.0V to 5.1V
84
83
100
108
95
dB
dB
RL = 1 kΩ to V+/2
AOL
Open Loop Gain
RL = 150Ω to V+/2
84
Output DC Characteristics
VO
Output Swing High
(Voltage from V+ Supply Rail)
111
126
100
430
110
440
35
RL = 1 kΩ to GND
RL =150Ω to GND
RL = 1 kΩ to GND
RL =150Ω to GND
RL = 150Ω to V−
457
526
Output Swing Low
(Voltage from V− Supply Rail)
121
136
mV
474
559
51
52
IOUT
RO
Linear Output Current
Output Resistance
VOUT = V+/2 (Note 6)
f = 1 MHz
±25
5.5
±35
mA
0.17
Ω
Enable Pin Operation
Enable High Voltage Threshold Enabled
Enable Pin High Current VDISABLE = +5V
Enable Low Voltage Threshold Disabled
V
µA
V
16
4.5
Enable Pin Low Current
Turn-On Time
VDISABLE = −5V
17
25
90
µA
ns
ns
Ton
Toff
Turn-Off Time
Power Supply Performance
PSRR
IS
Power Supply Rejection Ratio
DC, VCM = −4.5V, VS = 2.7V to 11V
84
104
dB
mA
μA
Supply Current
1.35
1.6
1.9
RL = ∞
ISD
Disable Shutdown Current
DISABLE = −5V
103
140
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 4: Boldface limits apply to temperature range of −40°C to 125°C
Note 5: Voltage average drift is determined by dividing the change in VOS by temperature change.
Note 6: Do not short circuit the output. Continuous source or sink currents larger than the IOUT typical are not recommended as it may damage the part.
Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 8: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using the Statistical Quality
Control (SQC) method.
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6
Connection Diagram
6-Pin TSOT23
20195801
Top View
Ordering Information
Package
Part Number
Package Marking
AE4A
Transport Media
1k Units Tape and Reel
3k Units Tape and Reel
NSC Drawing
LMH6618MK
6-Pin TSOT23
MK06A
LMH6618MKX
7
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Typical Performance Characteristics At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 2 kΩ for AV ≠ +1,
unless otherwise specified.
Closed Loop Frequency Response for
Various Supplies
Closed Loop Frequency Response for
Various Supplies
20195831
20195816
Closed Loop Frequency Response for
Various Supplies
Closed Loop Frequency Response for
Various Supplies
20195815
20195817
Closed Loop Frequency Response for
Various Temperatures
Closed Loop Frequency Response for
Various Temperatures
20195819
20195820
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8
Closed Loop Gain vs. Frequency for
Various Gains
Large Signal Frequency Response
20195818
20195830
±0.1 dB Gain Flatness for Various Supplies
Small Signal Frequency Response with
Various Capacitive Load
20195832
20195826
Small Signal Frequency Response with
Capacitive Load and Various RISO
HD2 vs. Frequency and Supply Voltage
20195835
20195827
9
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HD3 vs. Frequency and Supply Voltage
HD2 and HD3 vs. Frequency and Load
20195871
20195836
HD2 and HD3 vs. Common Mode Voltage
HD2 and HD3 vs. Common Mode Voltage
20195873
20195872
HD2 vs. Frequency and Gain
HD3 vs. Frequency and Gain
20195875
20195874
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10
Open Loop Gain/Phase
HD3 vs. Output Swing
HD2 vs. Output Swing
HD2 vs. Output Swing
HD2 vs. Output Swing
HD3 vs. Output Swing
20195833
20195843
20195844
20195845
20195869
20195846
11
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HD3 vs. Output Swing
THD vs. Output Swing
20195847
20195870
Settling Time vs. Input Step Amplitude
(Output Slew and Settle Time)
Input Noise vs. Frequency
20195876
20195821
VOS vs. VOUT
VOS vs. VOUT
20195849
20195850
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12
VOS vs. VCM
VOS vs. VS (pnp)
20195852
20195851
VOS vs. VS (npn)
VOS vs. IOUT
20195853
20195854
VOS Distribution (pnp and npn)
IB vs. VS (pnp)
20195855
20195877
13
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IB vs. VS (npn)
VOUT vs. VS
VOUT vs. VS
IS vs. VS
20195857
20195856
VOUT vs. VS
20195858
20195859
Closed Loop Output Impedance vs. Frequency AV = +1
20195860
20195822
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PSRR vs. Frequency
PSRR vs. Frequency
20195838
20195837
CMRR vs. Frequency
Small Signal Step Response
20195805
20195823
Small Signal Step Response
Small Signal Step Response
20195806
20195804
15
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Small Signal Step Response
Small Signal Step Response
Small Signal Step Response
Small Signal Step Response
Small Signal Step Response
Small Signal Step Response
20195808
20195807
20195812
20195809
20195811
20195810
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Large Signal Step Response
Large Signal Step Response
20195813
20195814
Overload Recovery Waveform
IS vs. VDISABLE
20195824
20195861
17
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which will reduce the supply current to typically less than 100
µA. The DISABLE pin is “active low” and should be connected
through a resistor to V+ for normal operation. Shutdown is
guaranteed when the DISABLE pin is 0.5V below the supply
midpoint at any operating supply voltage and temperature.
Application Information
The LMH6618 is based on National Semiconductor’s propri-
etary VIP10 dielectrically isolated bipolar process. This de-
vice family architecture features the following:
•
•
•
•
Complimentary bipolar devices with exceptionally high ft
(∼8GHz) even under low supply voltage (2.7V) and low
bias current.
Common emitter push-push output stage. This
architecture allows the output to reach within millivolts of
either supply rail.
Consistent performance from any supply voltage (2.7V -
11V) with little variation with supply voltage for the most
important specifications (e.g. BW, SR, IOUT.)
Significant power saving compared to competitive devices
on the market with similar performance.
In the shutdown mode, essentially all internal device biasing
is turned off in order to minimize supply current flow and the
output goes into high impedance mode. During shutdown, the
input stage has an equivalent circuit as shown in Figure 2.
With 3V supplies and a common mode input voltage range
that extends beyond either supply rail, the LMH6618 is well
suited to many low voltage/low power applications. Even with
3V supplies, the −3 dB BW (at AV = +1) is typically 120 MHz.
The LMH6618 is designed to avoid output phase reversal.
With input over-drive, the output is kept near the supply rail
(or as close to it as mandated by the closed loop gain setting
and the input voltage). Figure 1 shows the input and output
voltage when the input voltage significantly exceeds the sup-
ply voltages.
20195839
FIGURE 2. Input Equivalent Circuit During Shutdown
When the LMH6618 is shutdown, there may be current flow
through the internal diodes shown, caused by input potential,
if present. This current may flow through the external feed-
back resistor and result in an apparent output signal. In most
shutdown applications the presence of this output is incon-
sequential. However, if the output is “forced” by another de-
vice, the other device will need to conduct the current
described in order to maintain the output potential.
To keep the output at or near ground during shutdown when
there is no other device to hold the output low, a switch using
a transistor can be used to shunt the output to ground.
SINGLE CHANNEL ADC DRIVER
The low noise and wide bandwidth make the LMH6618 an
excellent choice for driving a 12-bit ADC. Figure 3 shows the
schematic of the LMH6618 driving an ADC121S101. The AD-
C121S101 is a single channel 12-bit ADC. The LMH6618 is
set up in a 2nd order multiple-feedback configuration with a
gain of −1. The −3 db point is at 500 kHz and the −0.01 dB
point is at 100 kHz. Table 1 shows the performance data of
the LMH6618 and the ADC121S101.
20195825
FIGURE 1. Input and Output Shown with CMVR Exceeded
If the input voltage range is exceeded by more than a diode
drop beyond either rail, the internal ESD protection diodes will
start to conduct. The current flow in these ESD diodes should
be externally limited.
The LMH6618 can be shutdown by connecting the
DISABLE pin to a voltage 0.5V below the supply midpoint
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18
20195829
FIGURE 3. LMH6618 Driving an ADC121S101
TABLE 1. Performance Data for the LMH6618 Driving an ADC121S101
Parameter
Signal Frequency
Signal Amplitude
SINAD
Measured Value
100 kHz
4.5V
71.5 dB
SNR
71.87 dB
−82.4 dB
90.97 dB
11.6 bits
THD
SFDR
ENOB
When the op amp and the ADC are using the same supply, it
is important that both devices are well bypassed. A 0.1 µF
ceramic capacitor and a 10 µF tantalum capacitor should be
located as close as possible to each supply pin. A sample
layout is shown in Figure 4. The 0.1 µF capacitors (C13 and
C6) and the 10 µF capacitors (C11 and C5) are located very
close to the supply pins of the LMH6618 and the AD-
C121S101.
19
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20195840
FIGURE 4. LMH6618 and ADC121S101 Layout
DIFFERENTIAL ADC DRIVER
C121S705. The ADC121S705 is a fully differential 12-bit
ADC. Performance with this circuit is similar to the circuit in
Figure 3.
The circuit in Figure 3 can be used to drive both inputs of a
differential ADC. Figure 5 shows the LMH6618 driving an AD-
20195842
FIGURE 5. LMH6618 Driving an ADC121S705
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20
DC LEVEL SHIFTING
7. For the example the supply voltage will be +5V.
8. Noise gain = 2 + 2/5V = 2.4.
9. RF = 2 kΩ
10. R1 = 2 kΩ/2 = 1 kΩ
11. R2 = 2 kΩ/(2.4-2) = 5 kΩ.
12. RG = 2 kΩ/(2.4 – 1) = 1.43 kΩ.
Often a signal must be both amplified and level shifted while
using a single supply for the op amp. The circuit in Figure 6
can do both of these tasks. The procedure for specifying the
resistor values is as follows.
1. Determine the input voltage.
2. Calculate the input voltage midpoint, VINMID = VINMIN
(VINMAX – VINMIN)/2.
+
3. Determine the output voltage needed.
4. Calculate the output voltage midpoint, VOUTMID
VOUTMIN + (VOUTMAX – VOUTMIN)/2.
=
5. Calculate the gain needed, gain = (VOUTMAX – VOUTMIN)/
(VINMAX – VINMIN
)
6. Calculate the amount the voltage needs to be shifted
from input to output, ΔVOUT = VOUTMID – gain x VINMID
.
7. Set the supply voltage to be used.
8. Calculate the noise gain, noise gain = gain + ΔVOUT/VS.
9. Set RF.
10. Calculate R1, R1 = RF/gain.
11. Calculate R2, R2 = RF/(noise gain-gain).
12. Calculate RG, RG= RF/(noise gain – 1).
20195848
Check that both the VIN and VOUT are within the voltage
ranges of the LMH6618.
FIGURE 6. DC Level Shifting
The following example is for a VIN of 0V to 1V with a VOUT of
2V to 4V.
4th ORDER MULTIPLE FEEDBACK LOW-PASS FILTER
Figure 7 shows the LMH6618 used as the amplifier in a mul-
tiple feedback low-pass filter. This filter is set up to have a
gain of +1 and a −3 dB point of 1 MHz. Values can be deter-
mined by using the WEBENCH® Active Filter Designer found
at amplifiers.national.com.
1. VIN = 0V to 1V.
2. VINMID = 0V + (1V – 0V)/2 = 0.5V.
3. VOUT = 2V to 4V.
4. VOUTMID = 2V + (4V – 2V)/2 = 3V.
5. Gain = (4V – 2V)/(1V – 0V) = 2
6.
ΔVOUT = 3V – 2 x 0.5V = 2.
20195828
FIGURE 7. 4th Order Multiple Feedback Low-Pass Filter
21
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CURRENT SENSE AMPLIFIER
With it’s rail-to-rail input and output capability, low VOS, and
low IB the LMH6618 is an ideal choice for a current sense
amplifier application. Figure 8 shows the schematic of the
LMH6618 set up in a low-side sense configuration which pro-
vides a conversion gain of 2V/A. Voltage error due to VOS can
(1)
(2)
be calculated to be VOS
x
(1
+
RF/RG) or
0.6 mV x 21 = 12.6 mV. Voltage error due to IO is IO x RF or
0.26 µA x 1 kΩ = 0.26 mV. Hence total voltage error is
12.6 mV + 0.26 mV or 12.86 mV which translates into a cur-
rent error of 12.86 mV/(2 V/A) = 6.43 mA.
20195841
FIGURE 8. Current Sense Amplifier
20195865
TRANSIMPEDANCE AMPLIFIER
FIGURE 10. Bode Plot of Noise Gain Intersecting with Op
Amp Open-Loop Gain
By definition, a photodiode produces either a current or volt-
age output from exposure to a light source. A Tran-
simpedance Amplifier (TIA) is utilized to convert this low-level
current to a usable voltage signal. The TIA often will need to
be compensated to insure proper operation.
Figure 10 shows the bode plot of the noise gain intersecting
the op amp open loop gain. With larger values of gain, CT and
RF create a zero in the transfer function. At higher frequencies
the circuit can become unstable due to excess phase shift
around the loop.
A pole at fP in the noise gain function is created by placing a
feedback capacitor (CF) across RF. The noise gain slope is
flattened by choosing an appropriate value of CF for optimum
performance.
Theoretical expressions for calculating the optimum value of
CF and the expected −3 dB bandwidth are:
(3)
(4)
20195862
FIGURE 9. Photodiode Modeled with Capacitance
Elements
Equation 4 indicates that the −3 dB bandwidth of the TIA is
inversely proportional to the feedback resistor. Therefore, if
the bandwidth is important then the best approach would be
to have a moderate transimpedance gain stage followed by a
broadband voltage gain stage.
Figure 9 shows the LMH6618 modeled with photodiode and
the internal op amp capacitances. The LMH6618 allows cir-
cuit operation of a low intensity light due to its low input bias
current by using larger values of gain (RF). The total capaci-
tance (CT) on the inverting terminal of the op amp includes
the photodiode capacitance (CPD) and the input capacitance
of the op amp (CIN). This total capacitance (CT) plays an im-
portant role in the stability of the circuit. The noise gain of this
circuit determines the stability and is defined by:
Table 2 shows the measurement results of the LMH6618 with
different photodiodes having various capacitances (CPD) and
a feedback resistance (RF) of 1 kΩ.
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22
TABLE 2. TIA (Figure 1) Compensation and Performance Results
CPD
(pF)
22
CT
(pF)
24
CF CAL
(pF)
7.7
CF USED
(pF)
5.6
f −3 dB CAL
(MHz)
23.7
f −3 dB MEAS
(MHz)
20
Peaking
(dB)
0.9
47
49
10.9
15.8
23.4
10
16.6
15.2
0.8
100
222
102
224
15
11.5
10.8
0.9
18
7.81
8
2.9
Note:
GBWP = 65 MHz
CT = CPD + CIN
CIN = 2 pF
VS = ±2.5V
Figure 11 shows the frequency response for the various pho-
todiodes in Table 2.
When analyzing the noise at the output of the TIA, it is im-
portant to note that the various noise sources (i.e. op amp
noise voltage, feedback resistor thermal noise, input noise
current, photodiode noise current) do not all operate over the
same frequency band. Therefore, when the noise at the out-
put is calculated, this should be taken into account. The op
amp noise voltage will be gained up in the region between the
noise gain’s zero and pole (fZ and fP in Figure 10). The higher
the values of RF and CT, the sooner the noise gain peaking
starts and therefore its contribution to the total output noise
will be larger. It is obvious to note that it is advantageous to
minimize CIN by proper choice of op amp or by applying a
reverse bias across the diode at the expense of excess dark
current and noise.
20195868
FIGURE 11. Frequency Response for Various Photodiode
and Feedback Capacitors
23
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Physical Dimensions inches (millimeters) unless otherwise noted
6-Pin TSOT23
NS Package Number MK06A
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24
Notes
25
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Notes
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