LMK3001 [NSC]
Precision Clock Conditioner with Integrated VCO Evaluation Board Operating Instructions; 精密时钟调节器集成VCO的评估板使用说明书
| 型号： | LMK3001 |
| 厂家： | 
National Semiconductor |
| 描述： | Precision Clock Conditioner with Integrated VCO Evaluation Board Operating Instructions |
| 文件： | 总23页 (文件大小：3220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMK3001
Precision Clock Conditioner with Integrated VCO
Evaluation Board Operating Instructions
11-10-2006
National Semiconductor Corporation
Interface
2900 Semiconductor Dr.
MS A2-600
Santa Clara, CA, 95052-8090
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
TABLE OF
C
ONTENTS
G
ENERAL
D
ESCRIPTION ............................................................................................................................... 3
ILTER................................................................................................................................................ 3
PERATION................................................................................................................... 4
NFORMATION.................................................................................................................................. 8
L
R
B
OOP
F
EAD FIRST, BASIC
OARD
O
I
OSCin ................................................................................................................................................... 8
Fin......................................................................................................................................................... 8
Fout....................................................................................................................................................... 8
Loop Filter ............................................................................................................................................ 8
Features of the board............................................................................................................................. 9
Other Important Notes .......................................................................................................................... 9
R
D
ECOMMENDED
E
QUIPMENT...................................................................................................................... 10
ELAYS...................................................................................................................................................... 11
ETTINGS............................................................................................................................ 12
PPENDIX A: SCHEMATIC .......................................................................................................................... 16
ATERIALS............................................................................................................. 19
C
A
A
A
ODELOADER S
PPENDIX B: BILL OF
PPENDIX C: BUILD
M
D
IAGRAM .................................................................................................................. 22
2
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
General Description
The LMK3001 Evaluation Board simplifies evaluation of the LMK3001 Precision Clock Conditioner with
Integrated VCO. The package consists of a characterization board, a USB <--> uWire buffer board,
and CodeLoader software. The CodeLoader software will run on a Windows 2000 or Windows XP PC.
The purpose of the CodeLoader software is to program the internal registers of the LMK3001 device
through a MICROWIRETM interface.
Loop Filter
Phase Margin
74.4º
3200 uA
10 MHz
Kφ
Loop Bandwidth
59.1 kHz
Fcomp
Crystal Frequency
Supply Voltage
10 MHz
Output Frequency
VCO Gain
1470 to 1570 MHz
10 MHz/Volt
3.3 Volts
Charge Pump
R3
100 Ω
R4
100 Ω
VCO
CPout
C3
100 pF
C4
110 pF
This loop filter is located on the bottom side of the PCB and is selected by
placing a 0 ohm resistor on pad R137.
This loop filter has been designed for optimal RMS jitter using a low noise
reference.
3
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
Read first, Basic Operation
Read the document, “Installing CodeLoader 4 & USB Driver” for instructions to prepare the computer
for usage with the characterization board before continuing with the hardware setup.
For basic operation…
1. Connect a low noise 3.3 V power supply to the Vcc connector located at the top left of the
board
2. Connect a 10 MHz reference signal to the OSCin connector located on the right side of the
board.
3. Connect the CodeLoader cable to the uWire header located in the lower left.
4
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
Read first, Basic Operation (Continued)
4. Connect the USB <--> uWire board to the PC with the USB cable.
USB Setup
The USB <--> uWire board must be connected and operating (both
LEDs solid) before CodeLoader is started.
If CodeLoader is started before the USB <--> uWire board is
connected communications with target board will not work. If this is
done, exit CodeLoader and start CodeLoader again.
5
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
Read first, Basic Operation (Continued)
5. Start CodeLoader 4.
6. Select the USB Communication Mode on the Port Setup tab.
7. Select the default mode by clicking “Mode” ꢀ “10 MHz OSC”
6
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
Read first, Basic Operation (Continued)
8. Enable output to be measured, any of CLKout(0-7) or EN_Fout from either Clock Outputs or
Bits/Pins tab.
9. Program the part by clicking “Keyboard Controls” ꢀ “Load Device” or by pressing Ctrl+L.
7
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
Board Information
Notes on the operation of the board are included here.
OSCin
The board is configured to accept a single ended OSCin source, however it is also possible to drive
OSCin with a differential signal by changing the following components.
Differential OSCin setup
0 ohm
100 ohm
0.1 uF
Open
R35, R36, R38, R39
R44
C24, C25 (C6 is a 0.1 uF 0402 cap which may be moved to C25)
C6
The single ended setup uses the following components.
Single ended OSCin setup
0 ohm
51 ohm
0.1 uF
Open
R35, R38
No pad for this. Place between R44 pad on C24 side and GND
C24, C6 (C25 is a 0.1 uF 0402 cap which may be moved to C6)
C25
Fin
Fin is placed on the board for testing other devices in the footprint compatible family.
Fout
Fout allows direct access to the internal VCO before the clock distribution section. The EN_Fout bit
must be selected to enable Fout. A 3 dB pad is placed on R103, R104, and R105.
Loop Filter
R4 and R137 form a “resistor switch” which allows either one of two different loop filters to be
selected.
Resistor
Switch
Loop Filter
Location
Loop Filter
Components
Default Loop
Bandwidth
R4 Shorted
Top of board
C1, C2, R2, C101
77 Hz
R137 Shorted Bottom of board
C97, C4, R139, C100
59.1 kHz
The following table services as a cross reference from traditional loop filter component
designators to the designators on the characterization board. Also, on the board below each loop
filter is an offset diagram illustrating the positions of each loop filter component using traditional
C1, C2, C2p, R2 designators.
Traditional
Textbook
designators
C1
Top
Loop Filter
designators
C1
Bottom
Loop Filter
designators
C97
C2
C2
C4
C2p
C101
C100
R2
R2
R139
8
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
Features of the board
•
Either one of two loop filters can be selected by shorting either R137 or R4. More info
about each loop filter can be found in the General Description and Appendix A.
Test points for each of the uWire lines are scattered in the lower left corner of the board
and include: GOE_TP, DATAuWire, CLKuWire, LEuWire, SYNC_TP, LD_TP, Pin10_TP,
Pin7_TP, Pin5_TP.
•
•
•
Ground is located on each pin GND_J1, the 10 pin header on the left side of the board.
Ground is located on the GND_tp2 in the upper left corner of the board and GND_tp1
located to the right of the Vcc SMA connector.
•
•
Ground is located on the bottom side of the board on each pad of the unstuffed 10 pin
header GND_J2.
Vcc is located on each pin of VCC_J1, the 10 pin header on the upper left side of the
board.
•
•
Vcc is located on VccPlane test point located to the right of the Vcc SMA.
Vcc is located on the bottom side of the board on each pad of the unstuffed 10 pin
header VCC_J2
Other Important Notes
•
For both loop filters on the top and bottom side of the board, a helper silkscreen is offset
from the loop filters to help identify the components by National Semiconductor’s
traditional reference designators associated with loop filters.
When changing the OSCin frequency, the OSCin frequency register needs to be changed
to match.
•
•
•
Toggle the SYNC* pin to synchronize the clock outputs
Errata: SYNC* is labeled on the PCB as SYNC, however the logic of SYNC* is still active
low!
9
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
Recommended Equipment
Power Supply
The Power Supply should be a low noise power supply. An Agilent 6623A Triple power supply with LC
filters on the output to reduce noise was used in creating these evaluation board instructions.
Phase Noise / Spectrum Analyzer
For measuring phase noise an Agilent E5052A is recommended. An Agilent E4445A PSA Spectrum
Analyzer with the Phase Noise option is also usable although the architecture of the E5052A is superior
for phase noise measurements.
Oscilloscope
For measuring delay an Agilent Infiniium DSO81204A was used.
Reference Oscillator
Either a 10 MHz crystal or the reference output of any RF test equipment will serve as a 10 MHz
output.
Note: The default loop filter has a loop bandwidth of ~60 kHz. Inside the loop bandwidth of a PLL the
noise is greatly affected by any noise on the reference oscillator (OSCin). Therefore any noise on the
oscillator less than 60 kHz will be passed through and seen on the outputs. For this reason the main
output of a Signal Generator is not recommended for driving OSCin in this setup. Instead use the 10
MHz reference output of the signal generator.
10
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
Delays
These delay measurements illustrate how skew errors due to different length traces may be tuned out.
The delay may be adjusted in steps of 150 ps.
Delays 150, 300, 450, 600, 750
CLKout0_DLY = 0 ps
CLKout1_DLY = all delays
programmed: 0, 150, 300, 450,
600, 750, 900, 1050, 1200,
1350, 1500, 1650, 1800, 1950,
2100, and 2250 ps
11
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
CodeLoader Settings
The USB <--> uWire board must be connected and operating (both
LEDs solid) before CodeLoader is started.
If CodeLoader is started before the USB <--> uWire board is
connected communications with target board will not work. If this is
done, exit CodeLoader and start CodeLoader again.
The Port Setup tab tells CodeLoader what signals are assigned to which pins. If this is wrong,
the part will not program.
Part setup can be restored to the default state by clicking Mode ꢀ “10 MHz OSC.” The default
reference oscillator used for these instructions is 10 MHz and the restored mode expects a 10
MHz OSCin signal. For the loaded mode to take affect the device must be loaded by
pressing Ctrl+L.
12
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
The Bits/Pins tab shows some of the internal registers which are not accessible from any of the
other visual tabs like “PLL” and “Clock Outputs.”
Program Bits
POWERDOWN
EN_Fout
OSCin_FREQ
Powers the part down.
Turns on the Fout pin for measuring the internal VCO.
Must be set to the OSCin frequency in MHz.
This control also exists on the Clock Outputs page, it sets the value of the
input divider.
Programmable to many different values to support Lock Detect or aid
troubleshooting.
INPUT_DIV
PLL_MUX
VCO_R3_LF
VCO_R4_LF
Internal loop filter values, also accessible from Clock Outputs tab.
VCO_C3_C4_LF
Enable CLKout bits from CLKout0 to CLKout7. Also accessible from Clock
Outputs tab.
EN_CLKout0..7
Enable all clock outs. If unselected then the EN_CLKouts are overridden
and the outputs are all disabled.
EN_CLKout_Global
Program Pins
GOE
SYNC*
Set Global Output Enable to high or low logic level
Set SYNC* pin to high or low logic level
TRIGGER
Set auxiliary trigger pin to high or low logic level.
13
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
The Registers tab shows the raw bits which will be programmed when device is loaded by
clicking Keyboard Controls ꢀ Load Device or Ctrl+L.
The Clock Outputs tab allows the user to visualize the clock distribution portions of the device.
From this tab the device’s dividers, delays, clock output muxes, and output drivers can be
programmed along with internal loop filter values. The PLL block shows the R and N divider
values however to change these values either click on the PLL tab or the blue PLL box to access
the PLL tab to make changes to the PLL.
14
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
The PLL tab shows a conventional PLL diagram along with the Input Divider. It is important to
realize that the total effective N value is PLL N Counter * Input Divider. This means that the
“channel spacing” is the Phase Detector Frequency * Input Divider. Depending on the
situation, this may require the R Counter multiplied up by the value of the Input Divider to achieve
desired VCO output frequencies.
Example: If the desired VCO output frequency was 1501 MHz, R would need to be increased to
20 before 1501 MHz could be programmed because of the Input Divider of 2 would only allow
programming of 1500, 1502, 1504, etc. with a 1 MHz phase detector frequency.
15
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
Appendix A: Schematic
1
2
3
4
5
6
D
C
B
A
D
C
B
A
Timex-Main Board
Timex-Main Board.sch
Timex-Outputs
Timex-Outputs.sch
F1
SMA_CONN
Vcc
Vcc
GND_J1
VCC_J1
1
3
5
7
9
2
4
6
8
1
3
5
7
9
2
4
6
8
10
10
HEADER_2X5
GND_J2
HEADER_2X5
VCC_J2
Vcc
Vcc
1
3
5
7
9
2
4
6
8
1
3
5
7
9
2
4
6
8
10
10
HEADER_2X5
HEADER_2X5
Title
Size
B
Number
Revision
Date:
File:
1-Sep-2006
C:\worksvn\Timex-EvalBoard\Timex.ddb
Sheet of
Drawn By:
1
2
3
4
5
6
16
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
1
2
3
4
5
6
U2
LM317
Vin
LM317_out
U3
Input
LP2989_out
Vcc
LP2989_out
R5
0
R145
Open
R146
Open
TCXO_pwr
Open
1
3
4
2
8
3
5
6
7
1
VinLDO
Vin
Vout
VinLDO
Output
Sense
TCXO_RF
SMA
OSCin
C5
Open
R99
Open
R100
Open
LM317_out
NC
C15
Open
C75
Open
/Shutdown /Error
R37
Open
R53
Open
R44_opt
51 ohm
C24
GND
Bypass
R38
C12
Open
VinLDO
C14
Open
Vcc
VccLDO
Open
R144
Open
R9
Open
C53
Open
LP2989
0 ohm
R98
Open
R35
0 ohm
Vcc
DUT_OSCin
DUT_OSCin*
TCXO
C104
Open
C13
Open
C35
Open
C56
Open
OSCin
B1
SMA
SMA
6
4
1
2
3
R44
Open
0.1 uF
C25
Pd
Sd
NC
S
R45
Open
P
D
C
B
A
D
C
B
A
R36
Open
R134
Open
Open
1
2
Y1
4
Vcont Vcc
Open
TCXO
R39
Open
Vin LM317_out LP2989_out
OSCin*
C105
Open
C6
0.1 uF
GND_tp1
GND_tp2
C94
Open
3
GND
Out
TCXO_RF
R1
0
R33
Open
R34
Open
VccPlane
Vcc
Vcc3
Vcc4
Vcc5
Vcc6
R7
0
C54
100 pF
C9
10 uF
CLK0
R6
0
C3
10 uF
VCXO_pwr
Open
Vcc
Vcc
C55
100 pF
VCO_RF
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
Fin
C10
10 uF
R151
Open
R153
Open
R8
0
R48
Open
R54
Open
R49
VCXO
C63
100 pF
Vcc1
Vcc
R21
R13
C48
Open
R46
0 ohm
Open
DUT_Fin
0
Fout
C57
100 pF
C50
Open
C69
Open
Fin
B2
Pd
C11
10 uF
R16
0
SMA
6
4
1
2
3
R55
Open
0.1 uF
Sd
NC
S
VtuneVCXO
C64
100 pF
Vcc2
C49
R141 R148
Open Open
P
R10
0
R47
Open
U4
Vtune
DUT_Fin*
R56
R135
0 ohm
TC1-1-13M+
R50
1
2
3
6
5
4
Vs
RF*
RF
VCO
C58
100 pF
Vcc11
0.1 uF
Open
R19
0
Fin*
C106
C7
Open
C99
Open
NC
VCXO_RF*
VCXO_RF
DIG_vcc_tp
R152
51 ohm 51 ohm
R154
C95
Open
Open
Open
R149
Open
R51
C65
100 pF
Vcc7
Vcc8
Vcc9
SMA
Open
R14
0
GND
R101
Open
C107 Open
Open
DIG_vcc
VCXO - C5310
C59
C108
Open
C110
Open
Vcc12
R147 R41
Open Open
VCXO_RF*
VCXO_RF
R17
100 pF DIG
0
C66
100 pF
R11
0
R102
Open
C60
100 pF
Vcc13
R20
0
OSCin
PDCP_vcc_tp
Open
R150
C67
100 pF
R15
R52
0
VtuneVCO
Open
PDCP_vcc
0
VCO
C61
100 pF
C109
0.1 uF
C111
Open
Vcc14
U5
R18
0
PDCP
Synth
R57
1
7
6
5
Vt
NC
G
Open
C68
100 pF
Vcc10
2
G
R12
C96
Open
3
Vcc
Fout
VCO_RF
0
C62
100 pF
VCO_pwr
Open
Vcc
Vcc
R136
Open
R142
Open
C36
0.1 uF
C26
1 uF
C37
C38
C27
1 uF
C39
0.1 uF
C40
0.1 uF
C28
1 uF
C41
0.1 uF
C46
0.1 uF
C17
1 uF
C18
1 uF
C19
1 uF
C22
1 uF
0.1 uF
0.1 uF
C103
Open
C102
Open
Vcc
CLKout6
CLKout6*
CLKout5*
CLKout5
Vcc
C33
0.1 uF
C23
1 uF
C34
C42
C29
1 uF
C43
0.1 uF
C44
0.1 uF
C30
1 uF
C45
0.1 uF
C31
1 uF
C47
0.1 uF
C16
1 uF
C20
1 uF
C21
1 uF
0.1 uF
0.1 uF
CLKout7
CLKout7*
CLKout4*
CLKout4
R27
0
Vcc
Vcc14
Vcc13
Vcc12
Vcc11
CLKuWire
DATAuWire
LEuWire
R61
Open
R64
Open
DATAuWire
C71
LEuWire
LD
U1
C32
1 uF
CLKuWire
R25
LD
Open
0
R26
C8
Open
R58
27 k
R22
15 k
R59
27 k
R23
15 k
C72
Open
R60
27 k
R24
15 k
R62
15 k
R63
Open
C70
Open
Open
0
1
36
35
34
Vcc10
33
GND
Bias
Fout
B3 TC1-1-13M+
C76
R105
18 ohms
R103
1
2
3
6
4
2
Vcc1
3
VtuneVCXO VtuneVCO
Sd
NC
S
Pd
P
Fout
Fin*
Fin
DUT_Fin*
DUT_Fin
SMA
47 pF
Vcc1
R104
270
R40
Open
Open
270
4
Vtune
Open
CLKuWire
DATAuWire
CLKuWire
DATAuWire
LEuWire
NC
Vcc10
CPout
Vcc9
R3
0
R4
R143
Open
Vcc
Fout*
Open
5
6
32
Vcc9
31
Vcc8
30
29
28
27
Open
Pin10_TP
C2
LEuWire
Vcc2
Open C101
10 uF
R67
Open
DS8SF18I
0
Open
R138
GOE
Open
GOE
7
R137
Vcc8
C1
uWire
HEADER_2X5
R2
820
R42
Open
820 nF
8
Vcc2
OSCin*
OSCin
SYNC
Vcc7
DUT_OSCin*
DUT_OSCin
SYNC
C73
1 uF
R66
27 k
R28
15 k
9
LDObyp1
LDObyp2
GOE
10
11
12
R30
R31
Open
GOE
Vcc7
26
1
R32
1
LD
Pin7_TP
Pin5_TP
LDObyp1
R69
25
SYNC_TP
LDObyp2
C51
Open
LD
GND
Vcc
Open
R140
Open
C77
10 uF
C52
0.1 uF
C4
C100
12 nF
R65
Open
R29
15 k
Open
SYNC
Open
C97
Open
C98
Open
R139
1.8 k
R43
Open
GOE_TP LD_TP
SYNC
Vcc3
Vcc4
Vcc5
Vcc6
C74
100 pF
R68
27 k
CLKout0
CLKout0*
CLKout3*
CLKout3
Title
CLKout1
CLKout1*
CLKout2*
CLKout2
Size
C
Number
Revision
Date:
File:
8-Sep-2006
Sheet of
C:\worksvn\Timex-EvalBoard\Timex.ddb Drawn By:
1
2
3
4
5
6
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L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
1
2
3
4
5
6
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
CLKout0
CLKout1
CLKout2
CLKout3
R72
Open
R74
Open
R78
Open
R80
Open
R84
Open
R86
Open
R90
Open
R92
Open
D
C
B
A
D
C
B
A
C78
CLKout0
C80
CLKout1
C82
CLKout2
C84
CLKout3
CLKout0
CLKout1
CLKout2
CLKout3
0.1 uF
0.1 uF
0.1 uF
0.1uF
R106
Open
R107
Open
R108
Open
R109
Open
PC0
PC0b
PC1
PC1b
PC2
PC2b
PC3
PC3b
C79
CLKout0*
C81
CLKout1*
C83
CLKout2*
C85
CLKout3*
CLKout0*
CLKout1*
CLKout2*
CLKout3*
0.1 uF
0.1 uF
0.1 uF
0.1uF
R70
Open
R71
Open
R73
Open
R75
Open
R76
Open
R77
Open
R79
Open
R81
Open
R82
Open
R83
Open
R85
Open
R87
Open
R88
Open
R89
Open
R91
Open
R93
Open
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
CLKout4
CLKout5
CLKout6
CLKout7
R118
Open
R119
Open
R120
Open
R121
Open
R122
Open
R123
Open
R124
Open
R125
Open
C86
CLKout4
C88
CLKout5
C90
CLKout6
C92
CLKout7
CLKout4
CLKout5
CLKout6
CLKout7
0.1 uF
0.1 uF
0.1 uF
0.1uF
PC4
R94
Open
R95
Open
R96
Open
R97
Open
PC4b
PC5
PC5b
PC6
PC6b
PC7
PC7b
C87
CLKout4*
C89
CLKout5*
C91
CLKout6*
C93
CLKout7*
CLKout4*
CLKout5*
CLKout6*
CLKout7*
0.1 uF
0.1 uF
0.1 uF
0.1uF
R110
125
R111
125
R126
Open
R127
Open
R112
125
R113
125
R128
Open
R129
Open
R114
125
R115
125
R130
Open
R131
Open
R116
125
R117
125
R132
Open
R133
Open
Title
Size
C
Number
Revision
Date:
File:
1-Sep-2006
C:\worksvn\Timex-EvalBoard\Timex.ddb
Sheet of
DrawnBy:
1
2
3
4
5
6
18
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
Appendix B: Bill of Materials
Part
Manufacturer
Part Number
Quant Identifier
Capacitors
47 pF
Kemet
C0603C470J5GAC
1
C76
C54, C55, C57, C58, C59, C60, C61, C62, C63, C64, C65, C66, C67,
C68
C74
100 pF
100 pF
Kemet
Kemet
C0402C101J5GAC
C0603C101J5GAC
14
1
C6, C24, C48, C49, C78, C79, C80, C81, C82, C83, C84, C85, C86,
C87, C88, C89, C90, C91, C92, C93
0.1 uF
Kemet
C0402C104J4RAC
20
C33, C34, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46,
C47, C52
C109
C100
0.1 uF
0.1 uF
12 nF
Kemet
Kemet
Kemet
Kemet
C0603C104J3RAC
C0603C104J3RAC
C0805C123K4RAC
C0603C824K4RAC
15
1
1
820 nF
1
C1
C16, C17, C18, C19, C20, C21, C22, C23, C26, C27, C28, C29, C30,
C31, C73
C32
C77, C101
C3, C9, C10, C11
1 uF
1 uF
10 uF
10 uF
Kemet
Kemet
Kemet
Kemet
C0603C105K8VAC
C0603C105K8VAC
C0805C106K9PAC
C0805C106K9PAC
15
1
2
4
Resistors
R6, R7, R8, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,
R52
R1, R3, R5, R25, R35, R38, R46, R135, R137
R27
R26
R30, R32
R105
R152, R154
R44_opt (connected from one pad of R44 to GND)
R110, R111, R112, R113, R114, R115, R116, R117
R103, R104
R2
0 ohm
0 ohm
0 ohm
0 ohm
Panasonic
Vishay
Vishay
Vishay
Vishay
Vishay
Panasonic
Vishay
Panasonic
Vishay
Vishay
ERJ-2GE0R00X
15
9
1
1
2
1
2
1
8
2
1
CRCW0603000ZRT1
CRCW0603000ZRT1
CRCW0603000ZRT1
CRCW0603010JRT1
CRCW0603180JRT1
ERJ-2GEJ510X
CRCW0603510JRT1
ERJ-2GEJ121X
CRCW0603271JRT1
CRCW0603821JRT1
1 ohm
18 ohms
51 ohms
51 ohms
120 ohms
270 ohms
820 ohms
19
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
1.8 k
15 k
27 k
Vishay
Vishay
Vishay
CRCW0603182JRT1
CRCW0603153JRT1
CRCW0603273JRT1
1
6
5
R139
R22, R23, R24, R28, R29, R62
R58, R59, R60, R66, R68
SMA Connectors
SMA_EDGE
Johnson Components 142-0701-851
1
Vcc
CLKout0, CLKout0*, CLKout3, CLKout3*, CLKout4, CLKout4*, CLKout7,
CLKout7*
Fin, Fin*, OSCin, OSCin*, Fout
SMA_EDGE
SMA_EDGE
Johnson Components 142-0701-851
Johnson Components 142-0701-851
8
5
Other
HEADER_2X5
HEADER_2X5
BALUN - TC1-1-13M+
PCB
SPCS-8
LMK3001 Device
FCI Electronics
Comm Con Connectors HTSM3203-10G2
Minicircuits
Printed Circuits Corp.
SPC Technology
National
52601-S10-8
1
2
1
1
4
1
uWire
GND_J1, VCC_J1
B2
-
Standoffs in the four corners (insert from bottom)
U1
TC1-1-13M+
LMK30xxEB_PCB
SPCS-8
LMK3001
Open
C2, C4, C5, C7, C8, C12, C13, C14, C15, C25, C35, C50, C51, C53,
C56, C69, C70, C71, C72, C75, C94, C95, C96, C97, C98, C99, C102,
C103, C104, C105, C106, C107, C108, C110, C111
Open
Capacitors
35
R4, R9, R21, R31, R33, R34, R36, R37, R39, R40, R41, R42, R43, R44,
R45, R47, R48, R49, R50, R51, R53, R54, R55, R56, R57, R61, R63,
R64, R65, R67, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78,
R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91,
R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R106,
R107, R108, R109, R118, R119, R120, R121, R122, R123, R124, R125,
R126, R127, R128, R129, R130, R131, R132, R133, R134, R136, R138,
R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150,
R151, R153
Open
Open
Resistors
90
2
Comm Con Connectors HTSM3203-10G2
GND_J2, VCC_J2
CLKout1, CLKout1*, CLKout2, CLKout2*, CLKout5, CLKout5*, CLKout6,
CLKout6*, Vtune, Fout*, LD, GOE, SYNC, VccLDO, DIG_vcc,
Open
Johnson Components 142-0701-851
19
20
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
PDCP_vcc, TCXO_pwr, VCO_pwr, VCXO_pwr
B1, B3
Open
Minicircuits
TC1-1-13M+
2
21
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
Appendix C: Build Diagram
22
L M K 3 0 0 1 E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S
Bottom Build Diagram
23
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