LMV982 [NSC]
1.8V, RRIO Operational Amplifiers with Shutdown; 1.8V ， RRIO与关断运算放大器
| 型号： | LMV982 |
| 厂家： | 
National Semiconductor |
| 描述： | 1.8V, RRIO Operational Amplifiers with Shutdown |
| 文件： | 总18页 (文件大小：581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2002
LMV981 Single / LMV982 Dual
1.8V, RRIO Operational Amplifiers with Shutdown
General Description
Features
LMV981/LMV982 are low voltage, low power operational
amplifiers. LMV981/LMV982 are guaranteed to operate from
+1.8V to +5.0V supply voltages and have rail-to-rail input
and output. LMV981/LMV982 input common mode voltage
extends 200mV beyond the supplies which enables user
enhanced functionality beyond the supply voltage range.
The output can swing rail-to-rail unloaded and within 105mV
from the rail with 600Ω load at 1.8V supply. LMV981/
LMV982 are optimized to work at 1.8V which make them
ideal for portable two-cell battery powered systems and
single cell Li-Ion systems.
(Typical 1.8V Supply Values; Unless Otherwise Noted)
n Guaranteed 1.8V, 2.7V and 5V specifications
n Output swing
— w/600Ω load
— w/2kΩ load
n VCM
n Supply current (per channel)
n Gain bandwidth product
n Maximum VOS
80mV from rail
30mV from rail
200mV beyond rails
100µA
1.4MHz
4.0mV
101dB
n Gain w/600Ω load
n Ultra tiny package micro SMD
n Turn-on time from shutdown
n Temperature range
1.0mm x 1.5mm
19µs
−40˚C to 125˚C
LMV981/LMV982 offer a shutdown pin that can be used to
disable the device and reduce the supply current. The device
is in shutdown when the SHDN-pin = low.
LMV981/LMV982 exhibit excellent speed-power ratio,
achieving 1.4MHz gain bandwidth product at 1.8V supply Applications
voltage with very low supply current. LMV981/LMV982 are
capable of driving a 600Ω load and up to 1000pF capacitive
load with minimal ringing. LMV981/LMV982 have a high DC
gain of 101dB, making them suitable for low frequency ap-
plications.
n Industrial and automotive
n Consumer communication
n Consumer computing
n PDAs
n Portable audio
n Portable/battery-powered electronic equipment
n Supply current monitoring
LMV981 is offered in space saving 6-Bump micro SMD,
SC70-6 and SOT23-6 packages. The 6-Bump micro SMD
package has only a 1.006mm x 1.514mm x 0.945mm foot-
print. LMV982 is offered in space saving MSOP-10 package.
These small packages are ideal solutions for area con-
strained PC boards and portable electronics such as cellular
phones and PDAs.
n Battery monitoring
Typical Application
200214H0
© 2002 National Semiconductor Corporation
DS200214
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Absolute Maximum Ratings (Note 1)
Mounting Temp.
Infrared or Convection (20 sec)
235˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings (Note 1)
ESD Tolerance (Note 2)
Supply Voltage Range
1.8V to 5.0V
Machine Model
200V
2000V
Temperature Range
−40˚C to 125˚C
Human Body Model
Thermal Resistance (θJA
6-Bump micro SMD
SC70-6
)
Differential Input Voltage
Supply Voltage
5.5V
286˚C/W
414˚C/W
265˚C/W
235˚C/W
−
Supply Voltage (V+–V
)
Output Short Circuit to V+ (Note 3)
Output Short Circuit to V− (Note 3)
Storage Temperature Range
SOT23-6
MSOP-10
−65˚C to 150˚C
150˚C
Junction Temperature (Note 4)
1.8V DC Electrical Characteristics
−
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 1.8V, V = 0V, VCM = V+/2, VO = V+/2,
+
>
RL 1 MΩ and SHDN tied to V . Boldface limits apply at the temperature extremes. See (Note 10).
Symbol
Parameter
Condition
LMV981 (Single)
LMV982 (Dual)
Min
(Note 6)
Typ
(Note 5)
1
Max
(Note 6)
Units
VOS
Input Offset Voltage
4
6
mV
1
5.5
5.5
7.5
TCVOS
IB
Input Offset Voltage Average
Drift
µV/˚C
nA
Input Bias Current
15
35
50
25
40
185
205
1
IOS
IS
Input Offset Current
13
nA
Supply Current (per channel)
103
0.156
0.178
78
In Shutdown
LMV981 (Single)
LMV982 (Dual)
µA
dB
2
3.5
5
CMRR
Common Mode Rejection
Ratio
LMV981, 0 ≤ VCM ≤ 0.6V
1.4V ≤ VCM ≤ 1.8V
(Note 8)
60
55
LMV982, 0 ≤ VCM ≤ 0.6V
1.4V ≤ VCM ≤ 1.8V (Note 8)
−0.2V ≤ VCM ≤ 0V
1.8V ≤ VCM ≤ 2.0V
1.8V ≤ V+ ≤ 5V
55
50
50
76
72
PSRR
CMVR
Power Supply Rejection
Ratio
75
70
V− −0.2
V−
100
dB
V
Input Common-Mode Voltage For CMRR
Range Range ≥ 50dB
TA = 25˚C
TA = −40˚C to
85˚C
−0.2 to 2.1
V+ +0.2
V+
TA = 125˚C
V− +0.2
V+ −0.2
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2
1.8V DC Electrical Characteristics (Continued)
−
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 1.8V, V = 0V, VCM = V+/2, VO = V+/2,
+
>
RL 1 MΩ and SHDN tied to V . Boldface limits apply at the temperature extremes. See (Note 10).
Symbol
Parameter
Condition
Min
(Note 6)
77
Typ
(Note 5)
101
Max
(Note 6)
Units
AV
Large Signal Voltage Gain
LMV981 (Single)
RL = 600Ω to 0.9V,
VO = 0.2V to 1.6V, VCM = 0.5V
RL = 2kΩ to 0.9V,
73
dB
80
105
90
VO = 0.2V to 1.6V, VCM = 0.5V
75
Large Signal Voltage Gain
LMV982 (Dual)
RL = 600Ω to 0.9V,
VO = 0.2V to 1.6V, VCM = 0.5V
RL = 2kΩ to 0.9V,
75
72
dB
78
100
1.72
0.077
1.77
0.024
8
VO = 0.2V to 1.6V, VCM = 0.5V
75
VO
Output Swing
RL = 600Ω to 0.9V
1.65
1.63
VIN
=
100mV
0.105
0.120
V
RL = 2kΩ to 0.9V
VIN 100mV
1.75
=
1.74
0.035
0.04
IO
Output Short Circuit Current
Sourcing, VO = 0V
VIN = 100mV
4
3.3
7
mA
Sinking, VO = 1.8V
VIN = −100mV
9
5
Ton
Turn-on Time from Shutdown
Turn-on Voltage to enable
part
19
µs
V
VSHDN
1.0
Turn-off Voltage
0.55
1.8V AC Electrical Characteristics
−
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 1.8V, V = 0V, VCM = V+/2, VO = V+/2,
+
>
RL 1 MΩ and SHDN tied to V . Boldface limits apply at the temperature extremes. See (Note 10).
Symbol
Parameter
Conditions
Min
(Note 6)
Typ
(Note 5)
0.35
1.4
Max
(Note 6)
Units
SR
Slew Rate
(Note 7)
V/µs
MHz
deg
dB
GBW
Φm
Gm
en
Gain-Bandwidth Product
Phase Margin
67
Gain Margin
7
Input-Referred Voltage Noise f = 1kHz, VCM = 0.5V
Input-Referred Current Noise f = 1kHz
60
in
0.06
THD
Total Harmonic Distortion
Amp-to-Amp Isolation
f = 1kHz, AV = +1
RL = 600Ω, VIN = 1 VPP
(Note 9)
0.023
123
%
dB
3
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2.7V DC Electrical Characteristics
−
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 2.7V, V = 0V, VCM = V+/2, VO = V+/2,
+
>
RL 1 MΩ and SHDN tied to V . Boldface limits apply at the temperature extremes. See (Note 10).
Symbol
Parameter
Condition
LMV981 (Single)
LMV982 (Dual)
Min
(Note 6)
Typ
(Note 5)
1
Max
(Note 6)
Units
mV
VOS
Input Offset Voltage
4
6
1
5.5
6
mV
7.5
TCVOS
IB
Input Offset Voltage Average
Drift
µV/˚C
nA
Input Bias Current
15
35
50
25
40
190
210
1
IOS
IS
Input Offset Current
8
nA
Supply Current (per channel)
105
In Shutdown
LMV981 (Single)
LMV982 (Dual)
0.061
0.101
81
µA
2
3.5
5
CMRR
Common Mode Rejection
Ratio
LMV981, 0 ≤ VCM ≤ 1.5V
2.3V ≤ VCM ≤ 2.7V (Note 8)
LMV982, 0 ≤ VCM ≤ 1.5V
2.3V ≤ VCM ≤ 2.7V (Note 8)
−0.2V ≤ VCM ≤ 0V
2.7V ≤ VCM ≤ 2.9V
1.8V ≤ V+ ≤ 5V
VCM = 0.5V
60
55
55
50
50
80
dB
dB
V
74
PSRR
CMVR
Power Supply Rejection
Ratio
75
70
V− −0.2
V−
100
Input Common-Mode Voltage For CMRR
TA = 25˚C
TA = −40˚C to
85˚C
−0.2 to 3.0
V
V
++0.2
V+
Range
Range ≥ 50dB
TA = 125˚C
V− +0.2
87
+−0.2
AV
Large Signal Voltage Gain
LMV981(Single)
RL = 600Ω to 1.35V,
104
110
90
VO = 0.2V to 2.5V
RL = 2kΩ to 1.35V,
VO = 0.2V to 2.5V
RL = 600Ω to 1.35V,
VO = 0.2V to 2.5V
RL = 2kΩ to 1.35V,
VO = 0.2V to 2.5V
RL = 600Ω to 1.35V
86
dB
92
91
Large Signal Voltage Gain
LMV982 (Dual)
78
75
81
100
2.62
0.083
2.675
0.025
30
78
VO
Output Swing
2.55
2.53
VIN
=
100mV
0.110
0.130
V
RL = 2kΩ to 1.35V
VIN 100mV
2.65
=
2.64
0.04
0.045
IO
Output Short Circuit Current
Turn-on Time from Shutdown
Sourcing, VO = 0V
VIN = 100mV
20
15
18
12
mA
µs
Sinking, VO = 0V
VIN = −100mV
25
Ton
12.5
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4
2.7V DC Electrical Characteristics (Continued)
−
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 2.7V, V = 0V, VCM = V+/2, VO = V+/2,
+
>
RL 1 MΩ and SHDN tied to V . Boldface limits apply at the temperature extremes. See (Note 10).
Symbol
Parameter
Condition
Min
(Note 6)
Typ
(Note 5)
1.9
Max
(Note 6)
Units
VSHDN
Turn-on Voltage to enable
part
V
Turn-off Voltage
0.8
2.7V AC Electrical Characteristics
−
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 2.7V, V = 0V, VCM = 1.0V, VO = 1.35V,
+
>
RL 1 MΩ and SHDN tied to V . Boldface limits apply at the temperature extremes. See (Note 10).
Symbol
Parameter
Conditions
Min
(Note 6)
Typ
(Note 5)
0.4
Max
(Note 6)
Units
SR
GBW
Φm
Gm
en
Slew Rate
(Note 7)
V/µs
MHz
deg
dB
Gain-Bandwidth Product
Phase Margin
1.4
70
Gain Margin
7.5
Input-Referred Voltage Noise f = 1kHz, VCM = 0.5V
Input-Referred Current Noise f = 1kHz
57
in
0.082
THD
Total Harmonic Distortion
Amp-to-Amp Isolation
f = 1kHz, AV = +1
RL = 600kΩ, VIN = 1VPP
(Note 9)
0.022
123
%
dB
5V DC Electrical Characteristics
−
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 5V, V = 0V, VCM = V+/2, VO = V+/2,
+
>
RL 1 MΩ and SHDN tied to V . Boldface limits apply at the temperature extremes. See (Note 10).
Symbol
Parameter
Condition
LMV981 (Single)
Min
(Note 6)
Typ
(Note 5)
1
Max
(Note 6)
Units
VOS
Input Offset Voltage
4
6
mV
LMV982 (Dual)
1
5.5
14
5.5
7.5
TCVOS
IB
Input Offset Voltage Average
Drift
µV/˚C
nA
Input Bias Current
35
50
25
40
210
230
1
IOS
IS
Input Offset Current
9
nA
Supply Current (per Channel)
116
0.201
0.302
86
µA
µA
In Shutdown
LMV981 (Single)
LMV982 (Dual)
2
3.5
5
CMRR
PSRR
Common Mode Rejection
Ratio
0 ≤ VCM ≤ 3.8V
60
55
50
4.6V ≤ VCM ≤ 5.0V (Note 8)
−0.2V ≤ VCM ≤ 0V
5.0V ≤ VCM ≤ 5.2V
1.8V ≤ V+ ≤ 5V
dB
dB
78
Power Supply Rejection
Ratio
75
100
VCM = 0.5V
70
5
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5V DC Electrical Characteristics (Continued)
−
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 5V, V = 0V, VCM = V+/2, VO = V+/2,
+
>
RL 1 MΩ and SHDN tied to V . Boldface limits apply at the temperature extremes. See (Note 10).
Symbol
Parameter
Condition
Min
(Note 6)
V− −0.2
V−
Typ
(Note 5)
−0.2 to 5.3
Max
(Note 6)
V+ +0.2
V+
Units
CMVR
Input Common-Mode Voltage For CMRR
TA = 25˚C
Range
Range ≥ 50dB
TA = −40˚C to
85˚C
V
TA = 125˚C
V− +0.3
88
V+ −0.3
AV
VO
IO
Large Signal Voltage Gain
(LMV981 Single)
RL = 600Ω to 2.5V,
102
113
VO = 0.2V to 4.8V
RL = 2kΩ to 2.5V,
VO = 0.2V to 4.8V
RL = 600Ω to 2.5V,
VO = 0.2V to 4.8V
RL = 2kΩ to 2.5V,
VO = 0.2V to 4.8V
RL = 600Ω to 2.5V
87
dB
dB
94
93
Large Signal Voltage Gain
LMV982 (Dual)
81
90
78
85
100
82
Output Swing
4.855
4.835
4.890
0.120
4.967
0.037
100
VIN
=
100mV (Note 8)
0.160
0.180
V
RL = 2kΩ to 2.5V
VIN 100mV
4.945
=
4.935
0.065
0.075
Output Short Circuit Current
LMV981, Sourcing, VO = 0V
VIN = 100mV
80
68
58
45
mA
Sinking, VO = 5V
VIN = −100mV
65
Ton
Turn-on Time from Shutdown
Turn-on Voltage to enable
part
8.4
4.2
µs
V
VSHDN
Turn-off Voltage
0.8
5V AC Electrical Characteristics
−
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. V+ = 5V, V = 0V, VCM = V+/2, VO = 2.5V,
+
>
R
1 MΩ and SHDN tied to V .Boldface limits apply at the temperature extremes. See (Note 10).
L
Symbol
Parameter
Conditions
Min
(Note 6)
Typ
(Note 5)
0.42
1.5
Max
(Note 6)
Units
SR
Slew Rate
(Note 7)
V/µs
MHz
deg
dB
GBW
Φm
Gm
en
Gain-Bandwidth Product
Phase Margin
71
Gain Margin
8
Input-Referred Voltage Noise f = 1kHz, VCM = 1V
Input-Referred Current Noise f = 1kHz
50
in
0.07
THD
Total Harmonic Distortion
Amp-to-Amp Isolation
f = 1kHz, AV = +1
RL = 600Ω, VO = 1V
(Note 9)
0.022
123
%
PP
dB
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6
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human body model, 1.5kΩ in series with 100pF. Machine model, 200Ω in series with 100pF.
Note 3: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150˚C. Output currents in excess of 45mA over long term may adversely affect reliability.
Note 4: The maximum power dissipation is a function of T
, θ , and T . The maximum allowable power dissipation at any ambient temperature is
JA A
J(MAX)
P
= (T
–T )/θ . All numbers apply for packages soldered directly into a PC board.
D
J(MAX) A JA
Note 5: Typical Values represent the most likely parametric norm.
Note 6: All limits are guaranteed by testing or statistical analysis.
+
Note 7: V = 5V. Connected as voltage follower with 5V step input. Number specified is the slower of the positive and negative slew rates.
Note 8: For guaranteed temperature ranges, see Input Common-Mode Voltage Range specifications.
+
Note 9: Input referred, V = 5V and R = 100kΩ connected to 2.5V. Each amp excited in turn with 1kHz to produce V = 3V
.
L
O
PP
Note 10: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
>
of the device such that T = T . No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where T
T .
A
J
A
J
See Applications section for information on temperature derating of this device. Absolute Maximum Ratings indicated junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
Connection Diagrams
6-Bump micro SMD
6-Pin SC70-6/SOT23-6
10-Pin MSOP
200214G7
Top View
20021435
200214G6
Top View
Top View
Ordering Information
Package
6-Bump micro SMD
6-Pin SC70
Part Number
Packaging Marking
Transport Media
NSC
Drawing
LMV981BL
LMV981BLX
LMV981MG
LMV981MGX
LMV981MF
LMV981MFX
LMV982MM
LMV982MMX
A
250 Units Tape and Reel
3k Units Tape and Reel
1k Units Tape and Reel
3k Units Tape and Reel
1k Units Tape and Reel
3.5k Units Tape and Reel
1k Unit Tape and Reel
3.5k Unit Tape and Reel
BLA006AAB
A77
MAA06A
MF06A
6-Pin SOT23
A78A
A87A
10-Pin MSOP
MUB10A
7
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Typical Performance Characteristics Unless otherwise specified, VS = +5V, single supply,
TA = 25˚C.
Supply Current vs. Supply Voltage (LMV981)
Sourcing Current vs. Output Voltage
20021422
20021425
Sinking Current vs. Output Voltage
Output Voltage Swing vs. Supply Voltage
20021428
20021449
Output Voltage Swing vs. Supply Voltage
Gain and Phase vs. Frequency
20021450
200214G8
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8
Typical Performance Characteristics Unless otherwise specified, VS = +5V, single supply,
TA = 25˚C. (Continued)
Gain and Phase vs. Frequency
Gain and Phase vs. Frequency
PSRR vs. Frequency
Gain and Phase vs. Frequency
200214G9
200214G10
CMRR vs. Frequency
20021439
200214G11
Input Voltage Noise vs. Frequency
20021458
20021456
9
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Typical Performance Characteristics Unless otherwise specified, VS = +5V, single supply,
TA = 25˚C. (Continued)
Input Current Noise vs. Frequency
THD vs. Frequency
20021466
20021467
THD vs. Frequency
Slew Rate vs. Supply Voltage
20021469
20021468
Small Signal Non-Inverting Response
Small Signal Non-Inverting Response
20021470
20021471
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10
Typical Performance Characteristics Unless otherwise specified, VS = +5V, single supply,
TA = 25˚C. (Continued)
Small Signal Non-Inverting Response
Large Signal Non-Inverting Response
20021472
20021473
Large Signal Non-Inverting Response
Large Signal Non-Inverting Response
20021474
20021475
Short Circuit Current vs. Temperature (Sinking)
Short Circuit Current vs. Temperature (Sourcing)
20021476
20021477
11
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Typical Performance Characteristics Unless otherwise specified, VS = +5V, single supply,
TA = 25˚C. (Continued)
Offset Voltage vs. Common Mode Range
Offset Voltage vs. Common Mode Range
20021436
20021437
Offset Voltage vs. Common Mode Range
20021438
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12
Application Note
1.0 INPUT AND OUTPUT STAGE
The rail-to-rail input stage of this family provides more flex-
ibility for the designer. The LMV981/LMV982 use a compli-
mentary PNP and NPN input stage in which the PNP stage
senses common mode voltage near V− and the NPN stage
senses common mode voltage near V+. The transition from
the PNP stage to NPN stage occurs 1V below V+. Since both
input stages have their own offset voltage, the offset of the
amplifier becomes a function of the input common mode
voltage and has a crossover point at 1V below V+.
This VOS crossover point can create problems for both DC
and AC coupled signals if proper care is not taken. Large
input signals that include the VOS crossover point will cause
distortion in the output signal. One way to avoid such distor-
tion is to keep the signal away from the crossover. For
example, in a unity gain buffer configuration and with VS
=
5V, a 5V peak-to-peak signal will contain input-crossover
distortion while a 3V peak-to-peak signal centered at 1.5V
will not contain input-crossover distortion as it avoids the
crossover point. Another way to avoid large signal distortion
is to use a gain of −1 circuit which avoids any voltage
excursions at the input terminals of the amplifier. In that
circuit, the common mode DC voltage can be set at a level
away from the VOS cross-over point. For small signals, this
transition in VOS shows up as a VCM dependent spurious
signal in series with the input signal and can effectively
degrade small signal parameters such as gain and common
mode rejection ratio. To resolve this problem, the small
signal should be placed such that it avoids the VOS cross-
over point. In addition to the rail-to-rail performance, the
output stage can provide enough output current to drive
600Ω loads. Because of the high current capability, care
should be taken not to exceed the 150˚C maximum junction
temperature specification.
20021459
FIGURE 1. Canceling the Offset Voltage due to Input
Bias Current
Typical Applications
4.0 HIGH SIDE CURRENT SENSING
The high side current sensing circuit (Figure 2) is commonly
used in a battery charger to monitor charging current to
prevent over charging. A sense resistor RSENSE is connected
to the battery directly. This system requires an op amp with
rail-to-rail input. The LMV981/LMV982 are ideal for this ap-
plication because the common mode input range goes up to
the rail.
2.0 SHUTDOWN MODE
The LMV981/LMV982 have a shutdown pin. To conserve
battery life in portable applications, the LMV981/LMV982
can be disabled when the shutdown pin voltage is pulled low.
The shutdown pin can’t be left unconnected. In case shut-
down operation is not needed, the shutdown pin should be
connected to V+ when the LMV981/LMV982 are used. Leav-
ing the shutdown pin floating will result in an undefined
operation mode, either shutdown or active, or even oscillat-
ing between the two modes.
3.0 INPUT BIAS CURRENT CONSIDERATION
The LMV981/LMV982 family has a complementary bipolar
input stage. The typical input bias current (IB) is 15nA. The
input bias current can develop a significant offset voltage.
This offset is primarily due to IB flowing through the negative
feedback resistor, RF. For example, if IB is 50nA and RF is
100kΩ, then an offset voltage of 5mV will develop (VOS = IB
x RF). Using a compensation resistor (RC), as shown in
Figure 1, cancels this effect. But the input offset current (IOS
)
will still contribute to an offset voltage in the same manner.
200214H0
FIGURE 2. High Side Current Sensing
13
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In Figure 3 the circuit is referenced to ground, while in Figure
4 the circuit is biased to the positive supply. These configu-
rations implement the half wave rectifier since the LMV981/
LMV982 can not respond to one-half of the incoming wave-
form. It can not respond to one-half of the incoming because
the amplifier can not swing the output beyond either rail
therefore the output disengages during this half cycle. Dur-
ing the other half cycle, however, the amplifier achieves a
half wave that can have a peak equal to the total supply
voltage. RI should be large enough not to load the
LMV981/LMV982.
Typical Applications (Continued)
5.0 HALF-WAVE RECTIFIER WITH RAIL-TO-GROUND
OUTPUT SWING
Since the LMV981/LMV982 input common mode range in-
cludes both positive and negative supply rails and the output
can also swing to either supply, achieving half-wave rectifier
functions in either direction is an easy task. All that is needed
are two external resistors; there is no need for diodes or
matched resistors. The half wave rectifier can have either
positive or negative going outputs, depending on the way the
circuit is arranged.
200214C4
200214C2
200214C3
FIGURE 3. Half-Wave Rectifier with Rail-To-Ground Output Swing Referenced to Ground
200214C1
200214B9
200214C0
FIGURE 4. Half-Wave Rectifier with Negative-Going Output Referenced to VCC
6.0 INSTRUMENTATION AMPLIFIER WITH
RAIL-TO-RAIL INPUT AND OUTPUT
voltages. Remember that even with rail-to-rail outputs, the
output can not swing past the supplies so the combined
common mode voltages plus the signal should not be
greater that the supplies or limiting will occur. For additional
applications, see National Semiconductor application notes
AN–29, AN–31, AN–71, and AN–127.
Some manufactures make a non-“rail-to-rail”-op amp rail-to-
rail by using a resistive divider on the inputs. The resistors
divide the input voltage to get a rail-to-rail input range. The
problem with this method is that it also divides the signal, so
in order to get the obtained gain, the amplifier must have a
higher closed loop gain. This raises the noise and drift by the
internal gain factor and lowers the input impedance. Any
mismatch in these precision resistors reduces the CMRR as
well. The LMV981/LMV982 is rail-to-rail and therefore
doesn’t have these disadvantages.
Using three of the LMV981/LMV982 amplifiers, an instru-
mentation amplifier with rail-to-rail inputs and outputs can be
made as shown in Figure 5.
In this example, amplifiers on the left side act as buffers to
the differential stage. These buffers assure that the input
impedance is very high and require no precision matched
resistors in the input stage. They also assure that the differ-
ence amp is driven from a voltage source. This is necessary
to maintain the CMRR set by the matching R1-R2 with R3-R4.
The gain is set by the ratio of R2/R1 and R3 should equal R1
and R4 equal R2. With both rail-to-rail input and output
ranges, the input and output are only limited by the supply
200214G4
FIGURE 5. Rail-to-rail instrumentation amplifier
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14
Simplified Schematic
200214A9
15
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Physical Dimensions inches (millimeters)
unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
1. EPOXY COATING
2. Sn/37Pb EUTECTIC BUMP
3. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD.
4. PIN A1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION. REMAINING PINS ARE NUMBERED COUNTER
CLOCKWISE.
5. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS PACKAGE LENGTH AND X3 IS
PACKAGE HEIGHT.
6. REFERENCE JEDEC REGISTRATION MO-211, VARIATION BC.
6-Bump micro SMD
NS Package Number BLA006AAB
X1 = 1.006 0.030mm X2 = 1.514 0.030mm X3 = 0.945 0.100mm
www.national.com
16
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
6-Pin SC70
NS Package Number MAA06A
6-Pin SOT23
NS Package Number MF06A
17
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
10-Pin MSOP
NS Package Number MUB10A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Europe
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Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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