LMX2301TM [NSC]
PLLatinumTM 160 MHz Frequency Synthesizer for RF Personal Communications; PLLatinumTM 160 MHz的频率合成器的射频个人通信
| 型号： | LMX2301TM |
| 厂家： | 
National Semiconductor |
| 描述： | PLLatinumTM 160 MHz Frequency Synthesizer for RF Personal Communications |
| 文件： | 总14页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
November 1996
LMX2301
PLLatinumTM 160 MHz Frequency Synthesizer
for RF Personal Communications
General Description
The LMX2301 is a high performance frequency synthesizer
designed for RF operation up to 160 MHz. It is fabricated
using National’s ABiC IV BiCMOS process.
Features
Y
RF operation up to 160 MHz
Y
2.7V to 5.5V operation
Y
Low current consumption:
e
e
3V
I
2 mA (typ) at V
LMX2301, which employs the digital phase lock loop tech-
nique, combined with a high quality reference oscillator and
a loop filter, provides the tuning voltage for the voltage con-
trolled oscillator to generate a very stable, low noise local
oscillator signal.
CC
CC
Y
Y
Internal balanced, low leakage charge pump
Small-outline, plastic, surface mount TSSOP,
0.173 wide package
×
Serial data is transferred into the LMX2301 via a three line
MICROWIRETM interface (Data, Enable, Clock). Supply volt-
age can range from 2.7V to 5.5V.
Applications
Y
Analog Cellular telephone systems
(AMPS, ETACS, NMT)
Y
The LMX2301 features very low current consumption, typi-
cally 2 mA at 3V.
Portable wireless communications
(PCS/PCN, cordless)
Y
Other wireless communication systems
The LMX2301 is available in a TSSOP 20-pin surface mount
plastic package.
Block Diagram
TL/W/12458–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
MICROWIRETM and PLLatinumTM are trademarks of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation
TL/W/12458
RRD-B30M126/Printed in U. S. A.
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Connection Diagram
LMX2301
TL/W/12458–2
20-Lead (0.173 Wide) Thin Shrink
×
Small Outline Package (TM)
Order Number LMX2301TM or LMX2301TMX
See NS Package Number MTC20
Pin Descriptions
Pin No.
Pin Name
I/O
Description
1
OSC
I
Oscillator input. A CMOS inverting gate input intended for connection to a crystal resonator for
operation as an oscillator. The input has a V /2 input threshold and can be driven from an
IN
CC
external CMOS or TTL logic gate. May also be from a reference oscillator.
Oscillator output.
3
4
5
OSC
O
OUT
t
V
V
Power supply for charge pump. Must be
V
CC
.
P
Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors should be
placed as close as possible to this pin and be connected directly to the ground plane.
CC
6
D
O
O
Internal charge pump output. For connection to a loop filter for driving the input of an external
VCO.
o
7
8
GND
LD
Ground.
Lock detect. Output provided to indicate when the VCO frequency is in ‘‘lock’’. When the loop is
locked, the pin’s output is HIGH with narrow low pulses.
10
11
f
I
I
RF buffer input. Small signal input from the VCO.
IN
CLOCK
High impedance CMOS Clock input. Data is clocked in on the rising edge, into the various
counters and registers.
13
14
DATA
LE
I
I
Binary serial data input. Data entered MSB first. LSB is control bit. High impedance CMOS input.
Load enable input (with internal pull-up resistor). When LE transitions HIGH, data stored in the
shift registers is loaded into the appropriate latch (control bit dependent). Clock must be low
when LE toggles high or low. See Serial Data Input Timing Diagram.
15
16
FC
I
Phase control select (with internal pull-up resistor). When FC is LOW, the polarity of the phase
comparator and charge pump combination is reversed.
BISW
O
Analog switch output. When LE is HIGH, the analog switch is ON, routing the internal charge
pump output through BISW (as well as through D ).
o
17
18
f
O
O
Monitor pin of phase comparator input. CMOS output.
OUT
w
Output for external charge pump. w is an open drain N-channel transistor and requires a pull-up
p
p
resistor.
19
PWDN
I
Power Down (with internal pull-up resistor).
e
e
PWDN
PWDN
HIGH for normal operation.
LOW for power saving.
Power down function is gated by the return of the charge pump to a TRI-STATE condition.
20
w
O
Output for external charge pump. w is a CMOS logic output.
r
r
2,9,12
NC
No connect.
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2
Functional Block Diagram
TL/W/12458–3
Note 1: The power down function is gated by the charge pump to prevent any unwanted frequency jumps. Once the power down pin is brought low the part will go
into power down mode when the charge pump reaches a TRI-STATE condition.
3
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Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Power Supply Voltage
V
CC
V
P
2.7V to 5.5V
a
to 5.5V
Power Supply Voltage
V
CC
40 C to 85 C
b
b
a
0.3V to 6.5V
a
0.3V to 6.5V
V
V
CC
P
b
a
Operating Temperature (T )
A
§
§
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Operating Ratings indicate conditions for which the
device is intended to be functional, but do not guarantee specific perform-
ance limits. For guaranteed specifications and test conditions, see the Elec-
trical Characteristics. The guaranteed specifications apply only for the test
conditions listed.
Voltage on Any Pin
e
b
a
with GND
0V (V )
I
0.3V to V
CC
0.3V
b
a
65 C to 150 C
Storage Temperature Range (T )
S
§
§
a
Lead Temperature (T ) (solder, 4 sec.)
L
260 C
§
Note 2: This device is a high performance RF integrated circuit with an ESD
k
rating
2 keV and is ESD sensitive. Handling and assembly of this device
should only be done at ESD workstations.
k
k
e
e
b
5V; 40 C
Electrical Characteristics V
5V, V
T
A
85 C, except as specified
§
§
CC
P
Symbol
Parameter
Power Supply Current
Conditions
Min
Typ
2.0
3.0
30
Max
Units
mA
e
I
I
V
V
V
V
3.0V
5.0V
3.0V
5.0V
5
CC
CC
CC
CC
CC
e
e
e
mA
Power Down Current
180
350
160
20
mA
CC-PWDN
60
mA
f
f
f
RF Input Operating Frequency
45
5
MHz
MHz
MHz
dBm
IN
Oscillator Input Operating Frequency
Phase Detector Frequency
Input Sensitivity
OSC
w
10
e
b
a
6
Pf
V
CC
2.7V to 5.5V
10
0.5
0.7 V
IN
OSC
IH
V
V
V
Oscillator Sensitivity
OSC
V
PP
IN
High-Level Input Voltage
*
*
V
CC
Low-Level Input Voltage
0.3 V
CC
V
IL
e
e
b
b
I
I
I
I
I
I
High-Level Input Current (Clock, Data)
Low-Level Input Current (Clock, Data)
Oscillator Input Current
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
5.5V
1.0
1.0
1.0
mA
mA
mA
mA
mA
mA
IH
CC
e
e
e
e
e
e
5.5V
0V, V
1.0
IL
IH
IL
IH
IL
CC
e
V
CC
5.5V
100
e
5.5V
5.5V
b
100
0V, V
CC
e
b
1.0
High-Level Input Current (LE, FC)
Low-Level Input Current (LE, FC)
V
CC
1.0
1.0
e
b
100
0V, V
5.5V
CC
*Except f and OSC
IN
IN
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4
k
k
85 C, except as specified (Continued)
e
e
b
5.0V; 40 C
Electrical Characteristics V
5.0V, V
T
A
§
§
CC
P
Symbol
Parameter
Conditions
Min
Typ
Max
Units
mA
e
o
b
5.0
5.0
I
I
I
Charge Pump Output Current
V
V
V /2
P
D
D
D
-source
-sink
-Tri
D
o
o
o
e
V /2
P
mA
D
o
s
s
b
0.5V
Charge Pump TRI-STATE Current
É
0.5V
T
V
D
V
P
o
b
5.0
5.0
nA
e
25 C
§
A
e b
b
b
V
OH
V
OL
V
OH
V
OL
High-Level Output Voltage
Low-Level Output Voltage
I
1.0 mA**
200 mA
V
V
0.8
0.8
V
V
OH
OL
OH
OL
CC
e
I
I
I
1.0 mA**
0.4
0.4
e b
High-Level Output Voltage (OSC
)
V
OUT
CC
e
Low-Level Output Voltage (OSC
)
200 mA
V
OUT
e
e
0.4V
I
I
Open Drain Output Current (w )
V
V
5.0V, V
1.0
mA
mA
X
OL
OH
p
CC
OH
OL
e
Open Drain Output Current (w )
5.5V
100
p
R
Analog Switch ON Resistance
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
Clock to Enable Set Up Time
Enable Pulse Width
100
ON
t
t
t
t
t
t
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
50
10
50
50
50
50
ns
ns
ns
ns
ns
ns
CS
CH
CWH
CWL
ES
EW
**Except OSC
OUT
5
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Functional Description
The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the R15 Latch, and the 11-bit
N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge) into the DATA input, MSB first.
If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the
S Latch (power up counter reset). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter (programmable
divider).
TL/W/12458–1
PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND COUNTER RESET (R15 LATCH)
If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit
latch (which sets the 14-bit R Counter) and the 1-bit R15 Latch, which can be used to force an immediate load of the R and N
counters during a cold power up condition. Serial data format is shown below.
TL/W/12458–14
14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO
(R COUNTER)
1-BIT COUNTER RESET
(R15 LATCH)
Divide
Counter
Reset
R
R
R
R
R
R
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
Ratio
R
15
14 13 12 11 10
Remove
0
1
3
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
1
#
1
0
#
1
0
#
Forced Load
4
Force
Load State
#
The 1-bit counter reset latch controls
whether the R and N counters are im-
mediately forced to load conditions
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes: Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 16383
e
]
N and R latch states are immediately
[
upon power up. If R 15
HIGH, the
R1 to R14: These bits select the divide ratio of the programmable
reference divider.
read into the respective counters.
C: Control bit (set to HIGH level to load R counter and R15 Latch)
Data is shifted in MSB first.
SUGGESTED PROGRAMMING SEQUENCE AFTER COLD POWER-UP
1. Program N counter with desired divide ratio.
e
2. Program R counter with R15 1 and desired divide ratio. (N and R counters hold at load state.)
e
3. Program R counter with R15 0 and desired divide ratio. (N and R counters start counting.)
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6
Functional Description (Continued)
PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 11-bit programmable counter. If the Control Bit (last bit shifted into the Data Register) is LOW,
data is transferred from the 19-bit shift register into an 11-bit latch, which sets the 11-bit programmable Counter. Serial data
format is shown below.
TL/W/12458–15
Note: R8 to R18: Programmable counter divide ratio control bits (3 to 2047)
7 LSB BITS OF N REGISTER
EQUATION FOR OUTPUT FREQUENCY
DETERMINATION
Divide
Ratio
N
7
N
6
N
5
N
4
N
3
N
2
N
1
e
c
f /R
OSC
[
]
f
f
N
VCO
: Output frequency of external voltage controlled oscil-
lator (VCO)
VCO
X
X
X
X
X
X
X
X
N:
Preset divide ratio of binary 11-bit programmable
counter (3 to 2047)
e
Don’t care state
Note:
X
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
f
: Output frequency of the external reference frequency
oscillator
OSC
Divide
N
N
N
N
N
N
N
N
N
N
9
N
8
R:
Preset divide ratio of binary 14-bit programmable ref-
erence counter (3 to 16383)
Ratio
N
18 17 16 15 14 13 12 11 10
3
4
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
0
#
0
1
#
1
0
#
1
0
#
#
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
7
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Functional Description (Continued)
SERIAL DATA INPUT TIMING
TL/W/12458–16
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V /2. The test waveform has an edge rate of 0.6 V/ns with
CC
@
@
e
e
5.5V.
amplitudes of 2.2V
V
2.7V and 2.6V
V
CC
CC
Phase Characteristics
In normal operation, the FC pin is used to reverse the polari-
ty of the phase detector. Both the internal and any external
charge pump are affected.
VCO Characteristics
Depending upon VCO characteristics, FC pin should be set
accordingly:
When VCO characteristics are like (1), FC should be set
HIGH or OPEN CIRCUIT;
When VCO characteristics are like (2), FC should be set
LOW.
When FC is set HIGH or OPEN CIRCUIT, the monitor pin of
the phase comparator input, f , is set to the reference
out
TL/W/12458–17
divider output, f . When FC is set LOW, f
out
is set to the
r
programmable divider output, f .
p
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
TL/W/12458–18
b
a
Notes: Phase difference detection range: 2q to 2q
The minimum width pump up and pump down current pulses occur at the D pin when the loop is locked.
o
e
FC
HIGH
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8
Analog Switch
The analog switch is useful for radio systems that utilize a frequency scanning mode and a narrow band mode. The purpose of
the analog switch is to decrease the loop filter time constant, allowing the VCO to adjust to its new frequency in a shorter
amount of time. This is achieved by adding another filter stage in parallel. The output of the charge pump is normally through the
D
pin, but when LE is set HIGH, the charge pump output also becomes available at BISW. A typical circuit is shown below. The
second filter stage (LPF-2) is effective only when the switch is closed (in the scanning mode).
o
TL/W/12458–19
Typical Crystal Oscillator Circuit
A typical circuit which can be used to implement a crystal
oscillator is shown below.
Typical Lock Detect Circuit
A lock detect circuit is needed in order to provide a steady
LOW signal when the PLL is in the locked state. A typical
circuit is shown below.
TL/W/12458–20
TL/W/12458–21
9
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Typical Application Example
Operational Notes:
TL/W/12458–22
*
VCO is assumed AC coupled.
**
R increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10X to 200X depending on the VCO power
IN
level. f RF impedance ranges from 40X to 100X.
IN
*** 50X termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no terminating
resistor is required. OSC may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias. (See Figure below)
IN
TL/W/12458–23
Application Hints:
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance.
Crosstalk between pins can be reduced by careful board layout.
This is an electrostatic sensitive device. It should be handled only at static free work stations.
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10
Application Information
LOOP FILTER DESIGN
A block diagram of the basic phase locked loop is shown.
TL/W/12458–24
FIGURE 1. Basic Charge Pump Phase Locked Loop
An example of a passive loop filter configuration, including
the transfer function of the loop filter, is shown in Figure 2.
TL/W/12458–25
a
s (C2 R2)
#
(C1 C2 R2)
1
e
Z(s)
2
s
a
a
sC2
sC1
#
#
FIGURE 2. 2nd Order Passive Filter
TL/W/12458–26
Define the time constants which determine the pole and
zero frequencies of the filter transfer function by letting
FIGURE 3. Open Loop Transfer Function
Thus we can calculate the 3rd order PLL Open Loop Gain in
terms of frequency
e
T2
R2 C2
#
(1a)
and
b
a
j0 T2) T1
Kw
K
(1
#
#
VCO
e
0
#
G(s) H(s)
#
#
e
l
s
j
C1 C2
#
2
a
0 C1 N(1
j0 T1)
#
T2 (2)
#
e
T1
R2
#
a
C1
C2
(1b)
From equation 2 we can see that the phase term will be
dependent on the single pole and zero such that
The PLL linear model control circuit is shown along with the
open loop transfer function in Figure 3. Using the phase
detector and VCO gain constants Kw and K
loop filter transfer function Z(s) , the open loop Bode plot
can be calculated. The loop bandwidth is shown on the
Bode plot (0p) as the point of unity gain. The phase margin
is shown to be the difference between the phase at the unity
b
b
1
1
e
b
a
e
w(0)
tan
(0 T2) tan
#
(0 T1)
180 (3)
§
#
[
]
and the
VCO
By setting
[
]
dw
T2
b
2
T1
e
0
2
a
a
(0 T1)
d0
1
(0 T2)
1
(4)
#
#
we find the frequency point corresponding to the phase in-
flection point in terms of the filter time constants T1 and T2.
This relationship is given in equation 5.
b
gain point and 180 .
§
e
0
1/ T2 T1
(5)
#
For the loop to be stable the unity gain point must occur
0
p
b
before the phase reaches
180 degrees. We therefore
want the phase margin to be at a maximum when the magni-
tude of the open loop gain equals 1. Equation 2 then gives
TL/W/12458–27
a
a
Kw
K
T1 (1
#
T2 (1
j0 T2)
#
#
VCO
p
e
C1
e
/Ns
VCO
e
H(s) G(s)
Open Loop Gain
e
i /i
i
e
2
0
N
j0 T1)
#
#
#
Ó
Ó
(6)
p
p
Kw Z(s) K
e
e
i
a
[
G(s)/ 1 H(s) G(s)
]
Closed Loop Gain
i /i
o
11
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Application Information (Continued)
Therefore, if we specify the loop bandwidth, 0 , and the
In choosing the loop filter components a trade off must be
made between lock time, noise, stability, and reference
spurs. The greater the loop bandwidth the faster the lock
time will be, but a large loop bandwidth could result in higher
reference spurs. Wider loop bandwidths generally improve
close in phase noise but may increase integrated phase
noise depending on the reference input, VCO and division
ratios used. The reference spurs can be reduced by reduc-
ing the loop bandwidth or by adding more low pass filter
stages but the lock time will increase and stability will de-
crease as a result.
p
phase margin, w , Equations 1 through 6 allow us to calcu-
p
late the two time constants, T1 and T2, as shown in equa-
tions 7 and 8. A common rule of thumb is to begin your
design with a 45 phase margin.
§
b
secw
tanw
p
p
e
T1
0
(7)
(8)
p
1
e
T2
2
0
T1
#
p
From the time constants T1, and T2, and the loop band-
width, 0 , the values for C1, R2, and C2 are obtained in
THIRD ORDER FILTER
p
equations 9 to 11.
A low pass filter section may be needed for some applica-
tions that require additional rejection of the reference side-
bands, or spurs. This configuration is given in Figure 4. In
order to compensate for the added low pass section, the
component values are recalculated using the new open
loop unity gain frequency. The degradation of phase margin
caused by the added low pass is then mitigated by slightly
increasing C1 and C2 while slightly decreasing R2.
2
a
a
T1 Kw
K
1
1
(0 T2)
#
#
VCO
p
e
C1
#
2
2
T2
0
N
(0 T1)
(9)
(10)
(11)
#
#
0
T2
T1
p
p
e
b
1
C2
C1
R2
#
# J
T2
e
C2
K
(MHz/V)
Voltage Controlled Oscillator (VCO)
Tuning Voltage constant. The fre-
quency vs voltage tuning ratio.
The added attenuation from the low pass filter is:
2
VCO
e
a
]
1
[
ATTEN
20 log (2qf
R3 C3)
(12)
(13)
#
#
Defining the additional time constant as
ref
Kw (mA)
Phase detector/charge pump gain
constant. The ratio of the current out-
put to the input phase differential.
e
T3
R3 C3
#
Then in terms of the attenuation of the reference spurs add-
ed by the low pass pole we have
N
Main divider ratio. Equal to RF /f
opt ref
ATTEN/20
b
2
10
1
RF (MHz)
opt
Radio Frequency output of the VCO at
which the loop filter is optimized.
e
T3
(14)
0
(2q
f
ref
)
#
We then use the calculated value for loop bandwidth 0 in
c
equation 11, to determine the loop filter component values
f
ref
(kHz)
Frequency of the phase detector in-
puts. Usually equivalent to the RF
channel spacing.
in equations 15–17. 0 is slightly less than 0 , therefore
c
the frequency jump lock time will increase.
p
1
e
e
e
T2
2
a
0
(T1
T3)
(15)
(16)
(17)
#
c
2
a
a
a
tanw (T1
T3)
(T1
T3)
a
tanw (T1
T1 T3
#
T3)
#
T3)
a
b
1
0
1
#
c
2
2
a
a
[
]
[
]
(T1
T1 T3
#
#
Ð0
(
2
#
c
2
T2 )
(/2
a
T1 Kw
K
(1
2
0
#
VCO
C1
#
#
2
2
2
2
T3 )
a
a
0
T2
0
N
(1
0
T1 ) (1
#
#
#
c
Ð
(
c
c
http://www.national.com
12
Application Information (Continued)
EXTERNAL CHARGE PUMP
EXAMPLE
e
e
e
50
The LMX PLLatinum series of frequency synthesizers are
equipped with an internal balanced charge pump as well as
outputs for driving an external charge pump. Although the
superior performance of NSC’s on board charge pump elim-
inates the need for an external charge pump in most appli-
cations, certain system requirements are more stringent. In
these cases, using an external charge pump allows the de-
signer to take direct control of such parameters as charge
pump voltage swing, current magnitude, TRI-STATE leak-
age, and temperature compensation.
Typical Device Parameters
Typical System Parameters
b
100, b
n
p
V
V
V
I
5.0V;
P
e
b
4.5V;
0.5V
cntl
wp
e
e
e
0.0V; V
5.0V
wr
e
Design Parameters
I
5.0 mA;
SINK
SOURCE
e
e
V
fn
V
fp
0.8V
e
e
I
I
1 mA
rmax
pmax
e
e
0.3V
V
V
V
R5
R8
OLwp
e
e
100 mV
V
OHwr
One possible architecture for an external charge pump cur-
rent source is shown in Figure 9. The signals w and w in
p
r
the diagram, correspond to the phase detector outputs of
the LMX2301 frequency synthesizer. These logic signals are
converted into current pulses, using the circuitry shown in
Figure 9, to enable either charging or discharging of the
loop filter components to control the output frequency of the
PLL.
Referring to Figure 9, the design goal is to generate a 5 mA
current which is relatively constant to within 0.5V of the
power supply rail. To accomplish this, it is important to es-
tablish as large of a voltage drop across R5, R8 as possible
without saturating Q2, Q4. A voltage of approximately 300
mV provides a good compromise. This allows the current
source reference being generated to be relatively repeat-
able in the absence of good Q1, Q2/Q3, Q4 matching.
(Matched transistor pairs is recommended.) The wp and wr
outputs are rated for a maximum output load current of 1
mA while 5 mA current sources are desired. The voltages
developed across R4, 9 will consequently be approximately
k
258 mV, or 42 mV R8, 5, due to the current density differ-
Ó
TL/W/12458–28
À
ences 0.026*1n (5 mA/1 mA) through the Q1, Q2/Q3, Q4
pairs.
FIGURE 9
In order to calculate the value of R7 it is necessary to first
estimate the forward base to emitter voltage drop (Vfn,p) of
Therefore select
b
0.3V 0.026 1n(5.0 mA/1.0 mA)
#
the transistors used, the V drop of wp, and the V
OL OH
drop
e
e
e
e
e
R
9
e
51.6X
R
R
R
R
4
5
8
6
k
of wr’s under 1 mA loads. (wp’s V 0.1V and wr’s
5 mA
OL
k
V
0.1V.)
OH
0.3V
e
e
300X
300X
Knowing these parameters along with the desired current
allow us to design a simple external charge pump. Separat-
ing the pump up and pump down circuits facilitates the no-
dal analysis and give the following equations.
1.0 mA
0.3V
1.0 mA
i
source
b
b
(5V 0.1V) (0.3V
a
0.8V)
b
V
V
ln
#
T
R5
e
e
3.8 kX
R
7
i
# J
p max
e
1.0 mA
R
4
i
source
i
sink
b
V
R8
V
T
ln
#
i
# J
n max
e
e
R
R
9
5
i
sink
V
R5
i
i
p max
V
R8
e
e
R
R
R
8
6
r max
b
b
b
a
a
(V
V
V
)
(V
R5
Vfp)
Vfn)
p
VOLwp
i
p max
b
(V
)
(V
R8
P
VOHwr
e
7
i
max
13
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Physical Dimensions inches (millimeters) unless otherwise noted
NS Package Number MTC20
20-Lead (0.173 Wide) Thin Shrink Small Outline Package (TM)
×
Order Number LMX2301TM
For Tape and Reel Order Number LMX2301TMX (2500 Units per Reel)
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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a
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