LMX2316TM [NSC]
PLLatinum⑩ Low Power Frequency Synthesizer for RF Personal Communications; 半导体PLLatinum ™低功耗频率合成射频个人通信
| 型号： | LMX2316TM |
| 厂家： | 
National Semiconductor |
| 描述： | PLLatinum⑩ Low Power Frequency Synthesizer for RF Personal Communications |
| 文件： | 总19页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2000
LMX2306/LMX2316/LMX2326
™
PLLatinum Low Power Frequency Synthesizer for RF
Personal Communications
LMX2306
LMX2316
LMX2326
550 MHz
1.2 GHz
2.8 GHz
General Description
Features
n 2.3V to 5.5V operation
The LMX2306/16/26 are monolithic, integrated frequency
synthesizers with prescalers that are designed to be used to
generate a very stable low noise signal for controlling the lo-
cal oscillator of an RF transceiver. They are fabricated using
National’s ABiC V silicon BiCMOS 0.5µ process.
n Ultra low current consumption
n 2.5V VCC JEDEC standard compatible
n Programmable or logical power down mode:
— ICC = 1 µA typical at 3V
The LMX2306 contains a 8/9 dual modulus prescaler while
the LMX2316 and the LMX2326 have a 32/33 dual modulus
prescaler. The LMX2306/16/26 employ a digital phase
locked loop technique. When combined with a high quality
reference oscillator and loop filter, the LMX2306/16/26 pro-
vide the feedback tuning voltage for a voltage controlled os-
cillator to generate a low phase noise local oscillator signal.
Serial data is transferred into the LMX2306/16/26 via a three
wire interface (Data, Enable, Clock). Supply voltage can
range from 2.3V to 5.5V. The LMX2306/16/26 feature ultra
n Dual modulus prescaler:
— LMX2306
— LMX2316/26
8/9
32/33
n Selectable charge pump TRI-STATE® mode
™
n Selectable FastLock mode with timeout counter
™
n MICROWIRE Interface
n Digital Lock Detect
Applications
n Portable wireless communications (PCS/PCN, cordless)
n Wireless Local Area Networks (WLANs)
n Cable TV tuners (CATV)
low current consumption; LMX2306
- 1.7 mA at 3V,
LMX2316 - 2.5 mA at 3V, and LMX2326 - 4.0 mA at 3V.
The LMX2306/16/26 synthesizers are available in a 16-pin
TSSOP surface mount plastic package.
n Pagers
n Other wireless communication systems
Functional Block Diagram
DS100127-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
™
™
™
FastLock , PLLatinum and MICROWIRE are trademarks of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
DS100127
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Connection Diagrams
LMX2306/16/26
LMX2306/16/26
DS100127-2
DS100127-19
16-Lead (0.173” Wide) Thin Shrink Small Outline
Package(TM)
16-pin Chip Scale Package
Order Number LMX2306SLBX, LMX2316SLBX or
LM2326SLBX
Order Number LMX2306TM, LMX2306TMX,
LMX2316TM, LMX2316TMX,
See NS Package Number SLB16A
LMX2326TM or LMX2326TMX
See NS Package Number MTC16
Pin Descriptions
16-Pin 16-Pin
TSSOP CSP
Pin
Name
FLo
I/O
Description
1
15
O
FastLock Output. For connection of parallel resistor to the loop filter. (See Section 1.3.4
FASTLOCK MODES description.)
2
3
4
5
16
1
CPo
GND
GND
fIN
O
Charge Pump Output. For connection to a loop filter for driving the input of an external VCO.
Charge Pump Ground.
Analog Ground.
2
3
I
I
RF Prescaler Complementary Input. A bypass capacitor should be placed as close as possible to
this pin and be connected directly to the ground plane. The complementary input can be left
unbypassed, with some degradation in RF sensitivity.
6
7
4
5
fIN
RF Prescaler Input. Small signal input from the VCO.
VCC1
Analog Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin and be connected directly to the ground plane. VCC1
must equal VCC2
.
8
6
OSCIN
I
I
Oscillator Input. This input is a CMOS input with a threshold of approximately VCC/2 and an
equivalent 100k input resistance. The oscillator input is driven from a reference oscillator.
9
7
8
GND
CE
Digital Ground.
10
Chip Enable. A LOW on CE powers down the device and will TRI-STATE the charge pump output.
Taking CE HIGH will power up the device depending on the status of the power down bit F2. (See
Section 1.3.1 POWERDOWN OPERATION and Section 1.7.1 DEVICE PROGRAMMING AFTER
FIRST APPLYING VCC.)
11
12
13
14
15
9
Clock
Data
LE
I
I
High Impedance CMOS Clock Input. Data for the various counters is clocked in on the rising edge
into the 21-bit shift register.
10
11
12
13
Binary Serial Data Input. Data entered MSB first. The last two bits are the control bits. High
impedance CMOS input.
I
Load Enable CMOS Input. When LE goes HIGH, data stored in the shift registers is loaded into one
of the 3 appropriate latches (control bit dependent).
Fo/LD
VCC2
O
Multiplexed Output of the RF Programmable or Reference Dividers and Lock Detect. CMOS output.
(See Table 4.)
Digital Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin and be connected directly to the ground plane. VCC1
must equal VCC2
.
16
14
VP
Power Supply for Charge Pump. Must be ≥ VCC.
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Min
Max
Units
Power Supply Voltage
Power Supply Voltage
VCC1
2.3
VCC1
VCC
−40
5.5
VCC1
5.5
V
V
VCC1
−0.3V to +6.5V
−0.3V to +6.5V
−0.3V to +6.5V
VCC2
VCC2
Vp
V
Vp
Operating Temperature (TA)
+85
˚C
Voltage on Any Pin
with GND = 0V (VI)
Storage Temperature Range (TS)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended operating conditions indicate condi-
tions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test condi-
tions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed.
−0.3V to VCC + 0.3V
−65˚C to +150˚C
Lead Temperature (TL)
(solder, 4 sec.)
+260˚C
Note 2: This device is a high performance RF integrated circuit with an ESD
<
rating 2 keV and is ESD sensitive. Handling and assembly of this device
should only be done at ESD protected work stations.
Electrical Characteristics
<
<
VCC = 3.0V, Vp = 3.0V; −40˚C TA 85˚C except as specified
Symbol
Parameter
Conditions
Values
Typ
1.7
Units
Min
Max
ICC
Power Supply Current
LMX2306
LMX2316
LMX2326
VCC = 2.3V to 5.5 V
VCC = 2.3V to 5.5V
VCC = 2.3V to 5.5V
VCC = 3.0V
mA
mA
2.5
4.0
mA
ICC-PWDN
fIN
Powerdown Current
1
µA
RF Input Operating
Frequency
LMX2306
LMX2316
LMX2326
VCC = 2.3V to 5.5V
VCC = 2.3V to 5.5V
VCC = 2.3V to 5.5V
VCC = 2.6V to 5.5V
25
0.1
0.1
0.1
5
550
1.2
2.1
2.8
40
MHz
GHz
GHz
GHz
MHz
MHz
dBm
dBm
dBm
dBm
V
fosc
fφ
Maximum Oscillator Frequency
Maximum Phase Detector Frequency
RF Input Sensitivity
10
PfIN
VCC = 3.0V
VCC = 5.0V
VCC =2.3V to 5.5V
OSCIN
−15
−10
+0
+0
−10
+0
Posc
VIH
VIL
Oscillator Sensitivity
−5
High-Level Input Voltage
Low-Level Input Voltage
(Note 4)
0.8 x VCC
(Note 4)
0.2 x
VCC
V
IIH
IIL
High-Level Input Current
Low-Level Input Current
VIH = VCC = 5.5V (Note 4)
−1.0
−1.0
1.0
1.0
µA
µA
VIL = 0V, VCC = 5.5V
(Note 4)
IIH
Oscillator Input Current
Oscillator Input Current
Charge Pump Output Current
VIH = VCC = 5.5V
100
µA
µA
µA
IIL
VIL = 0V, VCC = 5.5V
−100
ICPo-source
VDo = Vp/2, ICPo = LOW
(Note 3)
−250
250
−1.0
1.0
ICPo-sink
ICPo-source
ICPo-sink
ICPo-Tri
VDo = Vp/2, ICPo = LOW
(Note 3)
µA
mA
mA
nA
VDo = Vp/2, ICPo = HIGH
(Note 3)
VCPo = Vp/2, ICPo = HIGH
(Note 3)
Charge Pump TRI-STATE Current
CP Sink vs Source Mismatch
0.5 ≤ VCPo ≤ Vp − 0.5
−1.0
1.0
<
<
−40˚C TA 85˚C
ICPo-sink vs
ICPo-source
VCPo = Vp/2
5
%
TA = 25˚C
3
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Electrical Characteristics (Continued)
<
<
VCC = 3.0V, Vp = 3.0V; −40˚C TA 85˚C except as specified
Symbol Parameter
Conditions
Values
Typ
5
Units
%
Min
Max
ICPo vs VDo CP Current vs Voltage
0.5 ≤ VCPo ≤ Vp − 0.5
TA = 25˚C
ICPo vs T
CP Current vs Temperature
VCPo = Vp/2
5
%
<
<
−40˚C TA 85˚C
VOH
VOL
tCS
High-Level Output Voltage
Low-Level Output Voltage
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
IOH = −500 µA
VCC − 0.4
V
IOL = 500 µA
0.4
V
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
50
10
50
50
50
50
ns
ns
ns
ns
ns
ns
tCH
tCWH
tCWL
tES
Clock Pulse Width Low
Clock to Load Enable Set Up Time
Load Enable Pulse Width
tEW
Note 3: See PROGRAMMABLE MODES for ICP description
o
Note 4: Except f and OSC
.
IN
IN
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4
Charge Pump Current Specification Definitions
DS100127-3
I1 = CP sink current at VCPo = Vp–∆V
I2 = CP sink current at VCPo = Vp/2
I3 = CP sink current at VCPo = ∆V
I4 = CP source current at VCPo = Vp–∆V
I5 = CP source current at VCPo = Vp/2
I6 = CP source current at VCPo = ∆V
∆V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to VCC and ground. Typical values
are between 0.5V and 1.0V
1.
2.
3.
ICPo vs VCPo = Charge Pump Output Current magnitude variation vs Voltage =
1
1
1
[1⁄
2
{ |I1| − |I3|}]/[ ⁄
2
{|I1| + |I3|}] 100% and [ ⁄
2
{|I4| − |I6|}]/[ ⁄
2
*
*
*
*
* *
{|I4| + |I6|}] 100%
ICPo-sink vs ICPo–source = Charge Pump Output Current Sink vs Source Mismatch =
[|I2| − |I5|]/[1⁄
ICPo vs T = Charge Pump Output Current magnitude variation vs Temperature =
2
*
*
{|I2| + |I5|}] 100%
@
@
@
*
@
@
@
*
[|I2 temp| − |I2 25˚C|]/|I2 25˚C| 100% and [|I5 temp| − |I5 25˚C|]/|I5 25˚C| 100%
5
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RF Sensitivity Test Block Diagram
DS100127-15
Note 5: N=10,000 R=50 P=32
Note 6: Sensitivity limit is reached when the error of the divided RF output, FoLD, is greater than or equal to 1 Hz.
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6
1.0 Functional Description
The simplified block diagram below shows the 21-bit data register, a 14-bit R Counter, an 18-bit N Counter, and a 18-bit Function
Latch (intermediate latches are not shown). The data stream is shifted (on the rising edge of LE) into the DATA input, MSB first.
The last two bits are the Control Bits. The DATA is transferred into the counters as follows:
Control
DATA Location
C1
C2
0
0
1
0
1
R Counter
0
N Counter
1
Function Latch
Initialization
1
DS100127-4
1.1 PROGRAMMABLEREFERENCE DIVIDER
If the Control Bits are [C1, C2] = [0,0], data is transferred from the 21-bit shift register into a latch that sets the 14-bit R Counter.
The 4 bits R15–R18 are for test modes, and should be set to 0 for normal use. The LD precision bit, R19, is described in the
LOCK DETECT OUTPUT CHARACTERISTICS section. Serial data format is shown below.
DS100127-5
Note: R15 to R18 are test modes and should be zero for normal operation.
Data is shifted in MSB first.
1.1.1 14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Divide
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
0
•
R
8
0
0
•
R
7
0
0
•
R
6
0
0
•
R
5
0
0
•
R
4
0
0
•
R
3
0
1
•
R
2
1
0
•
R
1
1
0
•
Ratio
3
4
•
0
0
0
0
0
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes: Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 16383
R1 to R14: These bits select the divide ratio of the programmable reference divider.
7
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1.0 Functional Description (Continued)
1.2 PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 5-bit swallow counter (A counter) and the 13-bit programmable counter (B counter). If the Control
Bits are [C1, C2] = [1,0], data is transferred from the 21-bit shift register into a 5-bit latch (which sets the Swallow (A) Counter),
a 13-bit latch (which sets the 13-bit programmable (B) Counter), and the GO bit (See Section 1.3.4 FastLock MODES section)
MSB first. For the LMX2306 the maximum N value is 65535 and the minimum N value is 56. For the LMX2316/26, the maximum
N value is 262143 and the minimum N value is 992. Serial data format is shown below.
DS100127-6
Note: Data is shifted in MSB first.
1.2.1 5-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
LMX2316/26
LMX2306
Divide
N
5
0
0
•
N
4
0
0
•
N
3
0
0
•
N
2
0
0
•
N
1
0
1
•
Divide
N
5
X
X
•
N
4
X
X
•
N
3
0
0
•
N
2
0
0
•
N
1
0
1
•
Ratio
Ratio
0
1
0
1
•
•
31
1
1
1
1
1
7
X
X
1
1
1
Note: Divide ratio: 0 to 31
B ≥ A
Note: Divide ratio: 0 to 7
B ≥ A
X denotes a Don’t Care condition
1.2.2 13-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)
Divide
N
18
0
N
17
0
N
16
0
N
15
0
N
14
0
N
13
0
N
12
0
N
11
0
N
10
0
N
9
0
0
•
N
N
7
1
0
•
N
Ratio
8
0
1
•
6
1
0
•
3
4
•
0
0
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
8191
1
1
1
1
1
1
1
1
1
1
1
1
1
Divide ratio: 3 to 8191 (Divide ratios less than 3 are prohibited) B≥A
1.2.3 PULSE SWALLOW FUNCTION
fvco = [(P x B) + A] x fosc/R
fvco
B:
:
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of binary 13-bit programmable counter (3 to 8191)
A:
Preset divide ratio of binary 5-bit swallow counter (0 ≤ A ≤ 31; A ≤ B for LMX2316/26)
or (0 ≤ A ≤ 7, A ≤ B for LMX2306)
fosc
R:
:
Output frequency of the external reference frequency oscillator
Preset divide ratio of binary 14-bit programmable reference counter (3 to 16383)
Preset modulus of dual modulus prescaler
P:
for the LMX2306; P = 8 for the LMX2316/26; P = 32
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8
1.0 Functional Description (Continued)
1.3 FUNCTION AND INITIALIZATION LATCHES
Both the function and initialization latches write to the same registers. (See Section 1.7.1 DEVICE PROGRAMMING AFTER
FIRST APPLYING VCC section for initialization latch description.)
DS100127-7
TABLE 1. Programmable Modes
C1
C2
F1
F2
F3–5
FoLD
F6
PD
F7
CP
F8
0
1
COUNTER
RESET
POWER DOWN
FASTLOCK
ENABLE
CONTROL
POLARITY
TRI-STATE
F9
F10
F11–14
TIMEOUT
COUNTER
VALUE
F15–F17
F18
FAST-
LOCK
TIMEOUT
COUNTER
ENABLE
TEST
POWER
MODES
DOWN
MODE
CONTROL
TABLE 2. Mode Select Truth Table
POWER
REGISTER
LEVEL
COUNTER
PHASE
CP
RESET
DOWN
TRI-STATE
DETECTOR
POLARITY
NEGATIVE
0
1
RESET
DISABLED
RESET
POWERED
UP
NORMAL
OPERATION
TRI-STATE
POWERED
DOWN
POSITIVE
ENABELED
FUNCTION DESCRIPTION
F1. The Counter Reset enable mode bit F1, when activated, allows the reset of both N and R counters. Upon powering up, the
F1 bit needs to be disabled, then the N counter resumes counting in “close” alignment with the R counter. (The maximum error
is one prescalar cycle).
F2. Refer to Section 1.3.1 POWERDOWN OPERATION section.
F3–5. Controls output of FoLD pin. See FoLD truth table. See Table 4.
F6. Phase Detector Polarity. Depending upon VCO characteristics, F6 bit should be set accordingly. When VCO characteristics
are positive F6 should be set HIGH; When VCO characteristics are negative F6 should be set LOW
F7. Charge Pump TRI-STATE is set using bit F7. For normal operation this bit is set to zero.
F8. When the FastLock Enable bit is set the part is forced into one of the four FastLock modes. See description in Table 5, Fast-
Lock Decoding.
F9. The FastLock Control bit determines the mode of operation when in FastLock (F8 = 1). When not in FastLock mode, FLo
can be used as a general purpose output controlled by this bit. For F9 = 1, FLo is HIGH and for F9 = 0, FLo is LOW. See Table
5 for truth table.
F10. Timeout Counter Enable bit is set to 1 to enable the timeout counter. See Table 5 for truth table.
F11–14. FastLock Timeout Counter is set using bits F11-14. Table 6 for counter values.
F15–17. Function bits F15–F17 are for Test Modes, and should be set to 0 for normal use.
F18. Refer to Section 1.3.1 POWERDOWN OPERATION section.
9
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1.0 Functional Description (Continued)
1.3.1 POWERDOWN OPERATION
Bits F[2] and F[18] provide programmable powerdown modes when the CE pin is HIGH. When CE is LOW, the part is always im-
mediately disabled regardless of powerdown bit status. Refer to Table 3.
Synchronous and asynchronous powerdown modes are both available by MICROWIRE selection. Synchronous powerdown oc-
curs if the F[18] bit (Powerdown Mode) is HIGH when F[2] bit (Powerdown) becomes HIGH. Asynchronous powerdown occurs
if the F[18] bit is LOW when its F[2] bit becomes HIGH.
In the synchronous powerdown mode (F[18] = HIGH), the powerdown function is gated by the charge pump to prevent unwanted
frequency jumps. Once the powerdown program bit F[2] is loaded, the part will go into powerdown mode after the first successive
charge pump event.
In the asynchronous powerdown mode (F[18] = LOW), the device powers down immediately after latching LOW data into bit F[2].
The device returns to an actively powered up condition in either synchronous or asynchronous mode immediately upon LE latch-
ing LOW data into bit F[2].
Activation of a powerdown condition in either synchronous or asynchronous mode including CE pin activated powerdown has the
following effects:
•
•
Removes all active DC current paths.
•
•
•
Debiases the fIN input to a high impedance state.
Disables the oscillator input buffer circuitry.
Forces the R, N, and timeout counters to their load state
conditions.
The MICROWIRE control register remains active and ca-
pable of loading the data.
•
•
Will TRI-STATE the charge pump.
Resets the digital lock detect circuitry.
TABLE 3. Power Down Truth Table
CE(Pin 10)
F[2]
F[18]
Mode
Asynchronous Power Down
Normal Operation
LOW
HIGH
HIGH
HIGH
X
0
1
1
X
X
0
1
Asynchronous Power Down
Synchronous Power Down
TABLE 4. The Fo/LD (pin 14) Output Truth Table
F[5] Fo/LD Output State
F[3]
F[4]
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
TRI-STATE
R Divider Output (fr)
N Divider Output (fp)
Serial Data Output
Digital Lock Detect (See 1.3.2 LOCK DETECT OUTPUT Section)
n Channel Open Drain Lock Detect (See 1.3.2 LOCK DETECT OUTPUT
Section)
1
1
1
1
0
1
Active HIGH
Active LOW
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10
1.0 Functional Description (Continued)
1.3.2 LOCK DETECT OUTPUT CHARACTERISTICS
Output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and the open drain lock detect mode
is selected, the pin’s output is HIGH, with narrow pulses LOW. When digital lock detect is selected, the output will be HIGH when
<
the absolute phase error is 15 ns for three or five consecutive phase frequency detector reference cycles, depending on the
value of R[19]. Once lock is detected the output stays HIGH unless the absolute phase error exceeds 30 ns for a single reference
cycle. Setting the charge pump to TRI-STATE or power down (bits F2, F18) will reset the digital lock detect to the unlocked state.
The LD precision bit, R[19], will select five consecutive reference cycles, instead of three, for entering the locked state when R[19]
= HIGH.
DS100127-13
FIGURE 1. Typical Lock Detect Circuit
1.3.3 LOCK DETECT FILTER CALCULATION
The component values for the open drain lock detect filter can be determined after assessing the qualifications for an in-lock con-
dition. The in-lock condition can be specified as being a particular number (N) of consecutive reference cycles or duration (D)
wherein the phase detector phase error is some factor less than the reference period. In an example where the phase detector
reference period is 10 kHz, one might select the threshold for in-lock as occurring when 5 consecutive phase comparisons have
elapsed where the phase errors are a 1000 times shorter than the reference period (100 ns). Here, N = 5 and F = 1000.
For the lock detect filter shown in Figure 1, when used in conjunction with a open drain (active sink only) lock detect output, the
*
resistor value for R2 would be chosen to be a factor of F R1. Thus, if resistor R1 were pulled low for only 1/1000th of the ref-
erence cycle period, its “effective” resistance would be on par with R2. The two resistors for that duty cycle condition on average
appear to be two 1000x R1 resistors connected across the supply voltage with their common node voltage (Vc) at VCC/2. Phase
errors larger than 1/1000th of the reference cycle period would drag the average voltage of node Vc below VCC/2 indicating an
*
*
out-of-lock status. If the time constant of R2 C1 is now calculated to be N the reference period (500 µs), then the voltage of
node Vc would fall below VCC/2 only after 5 consecutive phase errors whose average pulse width was greater than 100 ns.
1.3.4 FastLock MODES
FastLock enables the designer to achieve both fast frequency transitions and good phase noise performance by dynamically
changing the PLL loop bandwidth. The FastLock modes allow wide band PLL fast locking with seemless transition to a low phase
noise narrow band PLL. Consistent gain and phase margins are maintained by simultaneously changing charge pump current
magnitude, counter values, and loop filter damping resistor. The four FastLock modes in Table 5 are similar to the technique used
in National Semiconductor’s LMX 233X series Dual Phase Locked Loops and are selected by F9, F10, and N19 when F8 is HIGH.
Modes 1 and 2 change loop bandwidth by a factor of two while modes 3 and 4 change the loop bandwidth by a factor of 4. Modes
1 and 2 increase charge pump magnitude by a factor of 4 and should use R2’=R2 for consistent gain and phase margin. Modes
1
3 and 4 increase charge pump magnitude and decrease the counter values by a factor of 4. R2’ = ⁄
3
R2 should be used for con-
sistent stability margin in modes 3 and 4. When F8 is LOW, the FastLock modes are disabled, F9 controls only the FLo output
→
→
level (FLo = F9), and N19 determines the charge pump current magnitude (N19=LOW ICPo = 250 µA, N19=HIGH ICPo
1 mA).
=
11
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1.0 Functional Description (Continued)
DS100127-8
TABLE 5. FastLock Decoding
FastLock Status
F[8]
F[9]
F[10]
N[19]
(Note 7)
1 (Note 7)
1
FastLock State
#
#
#
#
FastLock Mode
FastLock Mode
FastLock Mode
FastLock Mode
1
2
3
4
1
1
1
1
0
0
1
1
0
1
0
1
No Timeout Counter - 1X Divider
Timeout Counter - 1X Divider
No Timeout Counter - 1/4X Divider
Timeout Counter - 1/4X Divider
1 (Note 7)
1
Note 7: When the GO bit N[19] is set to one, the part is forced into the high gain mode. When the timeout counter is activated, termination of the counter cycle resets
the GO bit to 0. If the timeout counter is not activated, N[19] must be reprogrammed to zero in order to remove the high gain state. See below for descriptions of each
individual FastLock mode.
There are two techniques of switching in and out of FastLock. To program the device into any of the FastLock modes, the GO bit
N[19] must be set to one to begin FastLock operation. In the first approach, the timeout counter can be used (FastLock 2 and 4)
to stay in FastLock mode for a programmable number of phase detector reference cycles (up to 63) and then reset the GO bit
automatically. In the second approach (FastLock 1 and 3) without the timeout counter, the PLL will remain in FastLock mode until
the user resets the GO bit via the MICROWIRE serial bus. Once the GO bit is set to zero by the timeout counter or by MICROW-
IRE, the PLL will then return to normal operation. This transition does not effect the charge on the loop filter capacitors and is en-
acted synchronous with the charge pump output. This creates a nearly seamless transition between FastLock and standard
mode.
FastLock Mode 1 In this mode, the output level of the FLo is programmed in a low state while the ICPo is in the 4x state. The
device remains in this state until a command is received, resetting the N[19] bit to zero. Programming N[19]
*
to zero will return the device to normal operation ., i.e., ICPo = 1x and FLo returned to TRI-STATE.
FastLock Mode 2 Identical to mode 1, except the switching of the device out of FastLock is controlled by the Timeout counter.
The device will remain in FastLock until the timeout counter has counted down the appropriate number of
*
phase detector cycles, at which time the PLL returns to normal operation .
FastLock Mode 3 This mode is similar to mode 1 in that the output level of the FLo is low and the ICPo is switched to the 4x state.
Additionally, the R and N divide ratios are reduced by one fourth during the transient, resulting in a 16x im-
proved gain. As in mode 1, the device remains in this state until a MICROWIRE command is received, reset-
*
ting the N[19] bit to zero and returning the device to normal operation .
FastLock Mode 4 Identical to mode 3, except the switching of the device out of FastLock is controlled by the Timeout counter.
The device will remain in FastLock until the timeout counter has counted down the appropriate number of
*
phase detector cycles, at which time the PLL returns to normal operation .
*
Normal Operation FastLock Normal Operation is defined as the device being in low current mode and standard divider values.
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12
1.0 Functional Description (Continued)
TABLE 6. FastLock Timeout Counter Value Programming
Timeout
PD Cycles)
(Note 8)
F11
3
7
11
15
19
23
27
31
35
•
59
63
#
(
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
1
•
•
•
•
0
1
1
1
1
1
1
1
(4)
F12
(8)
F13
(16)
F14
(32)
Note 8: The timeout counter decrements after each phase detector comparison cycle.
1.4 SERIAL DATA INPUT TIMING
DS100127-9
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around V
. The test waveform has an edge rate of 0.6V/ns with
CC/2
@
@
V
CC
amplitudes of 1.84V
V
= 2.3V and 4.4V
= 5.5V.
CC
1.5 PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
DS100127-10
Notes: Phase difference detection range: −2π to +2π
The Phase Detector Polarity F[6] = HIGH
The minimum width pump up and pump down current pulses occur at the ICP pin when the loop is locked.
o
13
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1.0 Functional Description (Continued)
1.6 Typical Application Example
DS100127-11
OPERATIONAL NOTES:
*
VCO is assumed AC coupled.
**
R1 increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω to 200Ω depending on the VCO
power level. f RF impedance ranges from 40Ω to 100Ω.
IN
**
50Ω termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no terminating
resistor is required. OSC may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias. (See Figure below.)
IN
DS100127-12
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14
1.7.4 COUNTER RESET METHOD
1.7 Application Information
This MICROWIRE programming method consists of a func-
tion latch load, [C1, C2] = [0, 1], enabling the counter reset
bit, F[1]. The R and N counter latches are then loaded fol-
lowed by a final function latch load that disables the counter
reset. This provides the same close phase alignment as the
initialization sequence method with direct control over the in-
ternal reset. Note that counter reset holds the counters at
load point and will TRI-STATE the charge pump, but does
not trigger synchronous powerdown. The counter reset
method requires an extra function latch load compared to the
initialization sequence method.
1.7.1 DEVICE PROGRAMMING AFTER FIRST
APPLYING VCC
Three MICROWIRE programming methods can be used to
change the function latch, R counter latch, and N counter
latch contents with close phase alignment of R and N
counters to minimize lock up time after the cold power up.
1.7.2 INITIALIZATION SEQUENCE METHOD
Loading the function latch with [C1, C2] = [1, 1] immediately
followed by an R counter load, then an N counter load, effi-
ciently programs the MICROWIRE. Loading the function
latch with [C1, C2] = [1, 1] programs the same function latch
as a load with [C1, C2] = [0, 1] and additionally provides an
internal reset pulse described below. This program se-
quence insures that the counters are at load point when the
N counter data is latched in and the part will begin counting
in close phase alignment.
1.7.5 DEVICE PROGRAMMING
When programming the LMX2306, LMX2316, and
LMX2326, first determine the frequencies and mode of op-
eration desired. Data register is programmed with a 21-bit
data stream shifted into the R counter, N counter, or the F
latch. The Functional Description section shows the bits for
the R counter, and the corresponding information for the N
counter. The FLo programming information is given in the
FUNCTION AND INITIALIZATION LATCHES section. Typi-
cal numbers for a GSM application example are given. In the
example, the RF output is locking at 950 MHz (fvco) with a
200 kHz channel spacing (fcomparison). The crystal oscillator
reference input is 10 MHz (fosc) and the prescaler value (P)
is 32. An example of both methods of FastLock will be
shown.
The following results from latching the MICROWIRE with an
F latch word, [C1, C2] = [1, 1]:
•
•
The function latch contents are loaded.
An internal pulse resets the R, N, and timeout counters to
load state conditions and will TRI-STATE the charge
pump. If the function latch is programmed for the syn-
chronous powerdown case; CE = HIGH, F[2] = HIGH,
F[18] = HIGH, this internal pulse triggers powerdown.
Refer to Section 1.3.1 POWERDOWN OPERATION sec-
tion for a synchronous powerdown description. Note that
the prescaler bandgap reference and the oscillator input
buffer are unaffected by the internal reset pulse, allowing
close phase alignment when counting resumes.
The last two bits (control bits C1 and C2) of each bit stream
identify which counter or FLo mode will be programmed. For
example, to program the R counter, C1 and C2 will be 0,0.
Immediately proceeding these two bits is the N, R, or F bits
providing the divide ratios and FastLock mode information.
•
Latching the first N counter data after the initialization
word will activate the same internal reset pulse. Succes-
sive N counter data loads without an initialization load will
not trigger the internal reset pulse.
Control Bits
DATA Location
C1
C2
0
0
1
0
1
R Counter
0
N Counter
1.7.3 CE METHOD
1
Function Latch
Initialization
Programming the function latch, R counter latch and N
counter latch while the part is being held in a powerdown
state by CE allows lowest possible power dissipation. After
the MICROWIRE contents have been programmed and the
part is enabled, the R and N counter contents will resume
counting in close phase alignment. Note that after CE transi-
tions from LOW to HIGH, a duration of 1 µs may be required
for the prescaler bandgap voltage and oscillator input buffer
bias to reach steady state.
1
For example, to load the N counter, the last two bits C1 and
C2 must be 10.
Once the control bits have been determined, the frequency
information must be determined. To begin, determine the N
and R counter values as follows:
N = fvco/fcomparison
and
R = fosc/fcomparison
CE can be used to power the part up and down by pin control
in order to check for channel activity. The MICROWIRE does
not need to be reprogrammed each time the part is enabled
and disabled as long as it has been programmed at least
once after VCC was applied.
For this example R and N are determined as follows:
R = 10 MHz/200 kHz = 50
and
N = 950 MHz/200 kHz = 4750
15
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1.7 Application Information (Continued)
1.7.6 N COUNTER
The calculated value of N, and the value of P are now used to determine the values of A and B where A and B are both integer
values:
*
N = P B + A
where B is the divisor and A is the remainder. Therefore:
B = div (N/P)
and
*
A = N − (B P)
For this example, B and A are calculated as follows:
B = div (4750/32) = 148 = 0000010010100
and
*
A = 4750 − (148 32) = 14 = 01110
To load the N counter with these values, the programming bit stream would be as follows. The first bit, the GO bit, (MSB) N[19]
is used for FastLock operation and will be discussed in the F Latch section. The next 13 bits, (N[18]–N[6]) shifted in, are the B
*
counter value, 0000010010100b . Bits N[5]–N[1] are the A counter and are 01110b in this example. The final two bits (the control
bits) are 1,0 identifying the N counter. In programming the N counter, the value of B must be greater than or equal to A, and the
value of B must be greater than or equal to 3.
*
Note: In programming the counter, data is shifted in MSB first.
DS100127-14
1.7.7 R COUNTER
Programming the R counter is done by shifting in the binary value of R calculated previously (50d = 110010b). The first bit shifted
in is R[19] the LD precision bit. The next 4 bits (R[18]–R[15]) shifted in, are used for testing and should always be loaded with
zeros. The R[14]–R[1] bits are used to program the reference divider ratio and should be 00000000110010b for this example. The
final two bits, C[1] and C[2] denote the R counter and should be 0, 0. The resulting bit stream looks as follows:
DS100127-16
1.7.8 F LATCH
To program the device for any of the FastLock modes, C[1] = 0 and C[2] = 1 which direct data to the F latch. The Section 1.3
FUNCTION AND INITIALIZATION LATCH section discusses the 4 modes of FastLock operation. The user must first determine
which FastLock mode will be used. When using any of the FastLock modes, the programmer needs to experimentally determine
the length of time to stay in high gain mode. This is done by looking at the transient response and determining the time at which
the device has settled to within the appropriate frequency tolerance. FastLock mode should be terminated just prior to “lock” to
place the switching phase glitch within the transient settling time. The counter reset mode (F[1] bit) holds both the N and R
counters at load point when F[1] = HIGH. Upon setting F[1] = LOW, the N and R counters will resume counting in close phase
alignment. Other functions of the F latch such as FoLD output control, Phase detector polarity, and charge pump TRI-STATE are
defined in the 1.3 FUNCTION AND INITIALIZATION LATCH section also.
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16
1.7 Application Information (Continued)
1.7.9 FastLock MODE 1 PROGRAMMING
*
The F[1]–F[7] bits will be denoted as ( ) and are dependent on the desired modes of the applicable functions. To program the de-
vice for mode 1 FastLock, the F[8]–F[10] bits are programmed 100, while the N[19] bit is set to 1. The device will stay in the 4X
current mode until another N bit stream is sent with the N[19] bit reset to 0. This gives a bit stream as follows:
DS100127-17
1.7.10 FastLock MODE 2 PROGRAMMING
*
Again, the F[1]–F[7] bits will be denoted as don’t care ( ) but are dependent on the desired modes of the applicable functions.
To program the device for mode 2 FastLock, the F[8]–F[10] bits are programmed 101, while the N[19] bit is set to 1. The device
will stay in the 4X current mode for the programmed number of phase detector cycles. Bits F[11]–F[14] program this number of
cycles and are shown in Table 6. For our example, we will use 27 phase detector cycles, i.e. bits F[11]–F[14] will be 0110b. After
27 phase detector cycles, the N[19] bit returns to zero, bringing the device back to low current mode. The resulting bit stream is
as follows:
DS100127-18
FastLock modes 3 and 4 are programmed in the same manner and give the added 4X gain increase as discussed in Section 1.3.4
FastLock modes.
17
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM)
Order Number LMX2306TM, LMX2316TM or LMX2326TM
For Tape and Reel (2500 Units Per Reel)
Order Number LMX2306TMX, LMX2316TMXor LMX2326TMX
NS Package Number MTC16
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18
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Order Number LMX2306SLBX, LM2316SLBX or LM2326SLBX
NS Package Number SLB16A
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2. A critical component is any component of a life
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can be reasonably expected to cause the failure of
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