LMX2330USLB [NSC]
IC PLL FREQUENCY SYNTHESIZER, 2500 MHz, PQCC24, PLASTIC, CSP-24, PLL or Frequency Synthesis Circuit;
| 型号： | LMX2330USLB |
| 厂家： | 
National Semiconductor |
| 描述： | IC PLL FREQUENCY SYNTHESIZER, 2500 MHz, PQCC24, PLASTIC, CSP-24, PLL or Frequency Synthesis Circuit 信息通信管理 |
| 文件： | 总18页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
May 2001
LMX2330U/LMX2331U/LMX2332U
™
PLLatinum Ultra Low Power Dual Frequency
Synthesizer for RF Personal Communications
LMX2330U 2.5 GHz/600 MHz
Features
n Ultra low current consumption
LMX2331U 2.0 GHz/600 MHz
LMX2332U 1.2 GHz/600 MHz
n 2.7V to 5.5V operation
n Selectable synchronous or asynchronous powerdown
mode:
ICC = 1 µA typical at 3V
General Description
The LMX233xU family of monolithic, integrated dual fre-
quency synthesizers, including prescalers, is to be used as a
local oscillator for RF and first IF of a dual conversion
transceiver.
n Dual modulus prescaler:
LMX2330U
(RF) 32/33 or 64/65
LMX2331U/32U
(RF) 64/65 or 128/129
LMX2330U/31U/32U (IF) 8/9 or 16/17
n Selectable charge pump TRI-STATE® mode
n Selectable charge pump current levels
The LMX233xU contains dual modulus prescalers. A 64/65
or a 128/129 prescaler (32/33 or 64/65 in the 2.5 GHz
LMX2330U) can be selected for the RF synthesizer and a
8/9 or a 16/17 prescaler can be selected for the IF synthe-
sizer. LMX233xU, which employs a digital phase locked loop
technique, combined with a high quality reference oscillator,
provides the tuning voltages for voltage controlled oscillators
to generate very stable, low noise signals for RF and IF local
oscillators. Serial data is transferred into the LMX233xU via
a three wire interface (Data, Enable, Clock). Supply voltage
can range from 2.7V to 5.5V. The LMX233xU family features
very low current consumption;
™
n Selectable Fastlock mode
n Upgrade and compatible to LMX233xL family
n Available in 20 - Lead TSSOP and 24 - Pin CSP
Applications
n Portable Wireless Communications
(PCS/PCN, cordless)
n Cordless and cellular telephone systems
n Wireless Local Area Networks (WLANs)
n Cable TV tuners (CATV)
LMX2330U—3.3 mA at 3V, LMX2331U—2.9 mA at 3V,
LMX2332U—2.5 mA at 3V.
n Other wireless communication systems
The LMX233xU are available in TSSOP 20-pin and CSP
24-pin surface mount plastic packages.
Functional Block Diagram
DS101366-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
™
™
™
Fastlock , MICROWIRE and PLLatinum are trademarks of National Semiconductor Corporation.
© 2001 National Semiconductor Corporation
DS101366
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Connection Diagrams
Chip Scale Package (SLB)
(Top View)
Thin Shrink Small Outline Package (TM)
(Top View)
DS101366-2
Order Number LMX2330UTM, LMX2331UTM or
LMX2332UTM
NS Package Number MTC20
DS101366-39
Order Number LMX2330USLB, LMX2331USLB or
LMX2332USLB
NS Package Number SLB24A
Pin Descriptions
Pin No.
LMX233xULSLB
24-pinCSP
Package
Pin No.
LMX233xUTM
20-pin TSSOP
Package
Pin
I/O
Description
Name
24
1
VCC
1
—
Power supply voltage input for RF analog and RF digital circuits. Input
may range from 2.7V to 5.5V. VCC1 must equal VCC2. Bypass
capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
2
3
2
3
VP1
—
O
Power Supply for RF charge pump. Must be ≥ VCC.
Do RF
Internal charge pump output. For connection to a loop filter for driving
the input of an external VCO.
4
5
6
4
5
6
GND
—
Ground for RF digital circuitry.
fIN RF
fIN RF
I
I
RF prescaler input. Small signal input from the VCO.
RF prescaler complementary input. A bypass capacitor should be
placed as close as possible to this pin and be connected directly to the
ground plane. Capacitor is optional with some loss of sensitivity.
7
8
7
8
GND
—
I
Ground for RF analog circuitry.
OSCin
Oscillator input. The input has a VCC/2 input threshold and can be
driven from an external CMOS or TTL logic gate.
™
10
11
9
GND
FoLD
—
O
Ground for IF digital, MICROWIRE , FoLD, and oscillator circuits.
10
Multiplexed output of the RF/IF programmable or reference dividers,
RF/IF lock detect signals and Fastlock mode. CMOS output (see
Programmable Modes).
12
14
11
12
Clock
Data
I
I
High impedance CMOS Clock input. Data for the various counters is
clocked in on the rising edge, into the 22-bit shift register.
Binary serial data input. Data entered MSB first. The last two bits are
the control bits. High impedance CMOS input.
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2
Pin Descriptions (Continued)
Pin No.
LMX233xULSLB
24-pinCSP
Package
Pin No.
LMX233xUTM
20-pin TSSOP
Package
Pin
I/O
Description
Name
15
13
LE
I
Load enable high impedance CMOS input. When LE goes HIGH, data
stored in the shift registers is loaded into one of the 4 appropriate
latches (control bit dependent).
16
17
14
15
GND
fIN IF
—
I
Ground for IF analog circuitry.
IF prescaler complementary input. A bypass capacitor should be placed
as close as possible to this pin and be connected directly to the ground
plane. Capacitor is optional with some loss of sensitivity.
18
19
20
16
17
18
fIN IF
GND
Do IF
I
IF prescaler input. Small signal input from the VCO.
—
O
Ground for IF digital, MICROWIRE, FoLD, and oscillator circuits.
IF charge pump output. For connection to a loop filter for driving the
input of an external VCO.
22
23
19
20
VP2
—
—
Power Supply for IF charge pump. Must be ≥ VCC.
VCC2
Power supply voltage input for IF analog, IF digital, MICROWIRE,
FoLD, and oscillator circuits. Input may range from 2.7V to 5.5V. VCC
must equal VCC1. Bypass capacitors should be placed as close as
possible to this pin and be connected directly to the ground plane.
2
1, 9, 13, 21
X
NC
—
No connect.
3
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Block Diagram
DS101366-3
Note: The RF prescaler for the LMX2331U/32U is either 64/65 or 128/129, while the prescaler for the LMX2330U is 32/33 or 64/65.
Note: V 1 supplies power to the RF prescaler, N-counter, R-counter and phase detector. V 2 supplies power to the IF prescaler, N-counter, phase detector,
CC
CC
R-counter along with the OSC buffer, MICROWIRE, and F LD. V 1 and V 2 are clamped to each other by diodes and must be run at the same voltage level.
in
o
CC
CC
Note: V 1 and V 2 can be run separately as long as V ≥ V
.
P
P
P
CC
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4
Absolute Maximum Ratings (Notes 1,
2)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
VCC
2.7V to 5.5V
VCC to +5.5V
VP
Power Supply Voltage
Operating Temperature (TA)
−40˚C to +85˚C
VCC
−0.3V to +6.5V
−0.3V to +6.5V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate condi-
tions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test condi-
tions, see the Electrical Characteristics. The guaranteed specifications apply
only for the conditions listed.
VP
Voltage on Any Pin
with GND = 0V (VI)
Storage Temperature Range (TS)
Lead Temperature (solder 4 sec.) (TL)
−0.3V to VCC+0.3V
−65˚C to +150˚C
+260˚C
Note 2: This device is a high performance RF integrated circuit with an ESD
<
rating 2 kV and is ESD sensitive. Handling and assembly of this device
should only be done at ESD protected work stations.
Electrical Characteristics
<
<
VCC = 3.0V, VP = 3.0V; −40˚C TA 85˚C, except as specified
Value
Symbol
Parameter
Conditions
Units
Min
Typ
3.3
2.3
2.9
1.9
2.5
1.5
1.0
1.0
Max
4.3
3.4
3.8
2.5
3.3
2.0
1.3
10
ICC
Power
Supply
Current
LMX2330U RF + IF
LMX2330U RF Only
LMX2331U RF + IF
LMX2331U RF Only
LMX2332U RF + IF
LMX2332U RF Only
LMX233xU IF Only
mA
ICC-PWDN Powerdown Current
(Note 3)
µA
fIN RF
Operating
Frequency
LMX2330U
LMX2331U
LMX2332U
LMX233xU
0.5
0.2
0.1
45
2.5
2.0
1.2
600
GHz
MHz
fIN IF
Operating
Frequency
fOSC
fφ
Oscillator Frequency
5
40
MHz
MHz
Maximum Phase Detector
Frequency
10
PfIN RF RF Input Sensitivity
VCC = 3.0V
−15
−10
0
0
0
dBm
dBm
dBm
VPP
V
VCC = 5.5V
PfIN IF
VOSC
VIH
IF Input Sensitivity
VCC = 2.7V to 5.5V
−10
Oscillator Sensitivity
0.5
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
(Note 4)
(Note 4)
0.8 VCC
VIL
0.2 VCC
1.0
V
IIH
VIH = VCC = 5.5V
(Note 4)
−1.0
−1.0
µA
IIL
Low-Level Input Current
VIL = 0V, VCC = 5.5V
(Note 4)
1.0
µA
IIH
Oscillator Input Current
Oscillator Input Current
VIH = VCC = 5.5V
VIL = 0V, VCC = 5.5V
IOH = −500 µA
100
µA
µA
V
IIL
−100
VOH
High-Level Output Voltage
(for FoLD)
VCC − 0.4
VOL
Low-Level Output Voltage (for
FoLD)
IOL = 500 µA
0.4
V
tCS
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
See Data Input Timing
See Data Input Timing
See Data Input Timing
50
10
50
ns
ns
ns
tCH
tCWH
5
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Electrical Characteristics (Continued)
<
<
VCC = 3.0V, VP = 3.0V; −40˚C TA 85˚C, except as specified
Value
Typ
Symbol
Parameter
Conditions
Units
Min
50
Max
tCWL
tES
Clock Pulse Width Low
See Data Input Timing
See Data Input Timing
See Data Input Timing
ns
ns
ns
Clock to Load Enable Set Up Time
Load Enable Pulse Width
50
tEW
50
Note 3: Clock, Data and LE = GND or V
.
cc
Note 4: Clock, Data and LE does not include f RF, f IF and OSC .
IN
IN
IN
Charge Pump Characteristics
<
VCC = 3.0V, VP = 3.0V; −40˚C TA ≤ 85˚C, except as specified
Value
Symbol
Parameter
Conditions
Units
Min
Typ
−3.8
3.8
Max
IDo-SOURCE
Charge Pump Output
Current
VDo = VP/2, ICPo = HIGH (Note 5)
VDo = VP/2, ICPo = HIGH (Note 5)
VDo = VP/2, ICPo = LOW (Note 5)
VDo = VP/2, ICPo = LOW (Note 5)
0.5V ≤ VDo ≤ VP − 0.5V
mA
mA
mA
mA
I
I
I
I
Do-SINK
Do-SOURCE
Do-SINK
Do-TRI
−0.95
0.95
Charge Pump
TRI-STATE Current
−2.5
2.5
10
nA
I
Do-SINK vs
CP Sink vs
VDo = VP/2
3
%
%
%
I
Do-SOURCE
Source Mismatch (Note 7)
CP Current vs Voltage
(Note 6)
TA = 25˚C
IDo vs VDo
IDo vs TA
0.5 ≤ VDo ≤ VP − 0.5V
TA = 25˚C
10
10
15
CP Current vs
VDo = VP/2
Temperature (Note 8)
−40˚C ≤ TA ≤ 85˚C
Note 5: See PROGRAMMABLE MODES for I description.
Do
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6
Charge Pump Current Specification Definitions
DS101366-37
I1 = CP sink current at V = V − ∆V
Do
P
I2 = CP sink current at V = V /2
Do
P
I3 = CP sink current at V = ∆V
Do
I4 = CP source current at V = V − ∆V
Do
P
I5 = CP source current at V = V /2
Do
P
I6 = CP source current at V = ∆V
Do
∆V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V
and ground. Typical values are between 0.5V and 1.0V.
CC
Note 6: I vs V
=
Do
Charge Pump Output Current magnitude variation vs Voltage =
Do
1
1
[1⁄
2
{|I1| − |I3|}]/[ ⁄
2
{|I1| + |I3|}] 100% and [1⁄
2
{|I4| − |I6|}]/[ ⁄
2
*
*
*
*
* *
{|I4| + |I6|}] 100%
Note 7: I
vs I
=
Charge Pump Output Current Sink vs Source Mismatch =
Do-sink
Do-source
[|I2| − |I5|]/[1⁄
2
{|I2| + |I5|}] 100%
Charge Pump Output Current magnitude variation vs Temperature =
*
*
Note 8: I vs T
=
A
Do
@
@
@
*
@
@
@
*
[|I2 temp| − |I2 25˚C|]/|I2 25˚C| 100% and [|I5 temp| − |I5 25˚C|]/|I5 25˚C| 100%
7
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RF Sensitivity Test Block Diagram
DS101366-38
Note 1: N = 10,000
R = 50
P = 64
Note 2: Sensitivity limit is reached when the error of the divided RF output, F LD, is ≥ 1 Hz.
o
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8
Functional Description
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and the 15- and 18-bit N Counters
(intermediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first.
The data stored in the shift register is loaded into one of 4 appropriate latches on the rising edge of LE. The last two bits are the
Control Bits. The DATA is transferred into the counters as follows:
Control Bits
DATA Location
C1
0
C2
0
IF R Counter
RF R Counter
IF N Counter
RF N Counter
0
1
1
0
1
1
DS101366-6
PROGRAMMABLE REFERENCE DIVIDERS (IF AND RF R COUNTERS)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.
DS101366-7
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Divide
R
R
R
R
R
R
R
9
0
0
•
R
8
0
0
•
R
7
0
0
•
R
6
0
0
•
R
5
0
0
•
R
4
0
0
•
R
3
0
1
•
R
2
1
0
•
R
1
1
0
•
Ratio 15 14 13 12 11 10
3
4
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
•
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
9
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Functional Description (Continued)
PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch
(which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data
format is shown below. For the IF N counter bits 5, 6, and 7 are don’t care bits. The RF N counter does not have don’t care
bits.
DS101366-8
7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)
RF
Divide
IF
Divide
N
7
N
6
N
5
N
4
N
3
N
2
N
1
N
7
N
6
N
5
N
4
N
3
N
2
N
1
Ratio
Ratio
A
0
A
0
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
X
X
•
X
X
•
X
X
•
0
0
•
0
0
•
0
0
•
0
1
•
1
1
•
•
127
1
1
1
1
1
1
1
15
X
X
X
1
1
1
1
Notes: Divide ratio: 0 to 127
B ≥ A
X = DON’T CARE condition
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER)
Divide
N
N
N
N
N
N
N
N
N
N
9
N
18 17 16 15 14 13 12 11 10
8
Ratio
B
3
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
1
0
•
1
0
•
4
•
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited)
B ≥ A
PULSE SWALLOW FUNCTION
fVCO = [(P x B) + A] x fOSC/R
fVCO
B:
:
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
Preset divide ratio of binary 7-bit swallow counter
A:
(0 ≤ A ≤ 127 {RF}, 0 ≤ A ≤ 15 {IF}, A ≤ B)
fOSC
R:
:
Output frequency of the external reference frequency oscillator
Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P:
Preset modulus of dual moduIus prescaler (for IF; P = 8 or 16;
for RF; LMX2330U: P = 32 or 64
LMX2331U/32U: P = 64 or 128)
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10
Functional Description (Continued)
PROGRAMMABLE MODES
Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge pump
TRI-STATE and the output of the FoLD pin. The prescaler and powerdown modes are selected with bits N19 and N20. The
programmable modes are shown in Table 1. Truth table for the programmable modes and FoLD output are shown in Table 2 and
Table 3.
TABLE 1. Programmable Modes
C1
C2
R16
R17
R18
IF Do
R19
R20
0
0
IF Phase
IF ICPo
IF LD
IF Fo
Detector Polarity
RF Phase
TRI-STATE
RF Do
0
1
RF ICPo
RF LD
RF Fo
Detector Polarity
TRI-STATE
C1
1
C2
0
N19
N20
IF Prescaler
RF Prescaler
Pwdn IF
1
1
Pwdn RF
TABLE 2. Mode Select Truth Table
Phase Detector Polarity
(Note 11)
Do TRI-STATE
(Note 9)
ICPo
IF
2330L RF
2331L/32L RF
Prescaler
64/65
Pwdn
(Note 10) Prescaler Prescaler
(Note 9)
Pwrd Up
Pwrd Dn
0
1
Negative
Normal Operation
TRI-STATE
LOW
HIGH
8/9
32/33
64/65
Positive
16/17
128/129
Note 9: Refer to POWERDOWN OPERATION in Functional Description.
Note 10: The I LOW current state = 1/4 x I HIGH current.
CPo
CPo
Note 11: PHASE DETECTOR POLARITY
Depending upon VCO characteristics, R16 bit should be set accordingly: (see figure right)
When VCO characteristics are positive like (1), R16 should be set HIGH;
When VCO characteristics are negative like (2), R16 should be set LOW.
VCO Characteristics
DS101366-9
11
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Functional Description (Continued)
TABLE 3. The FoLD (Pin 10) Output Truth Table
RF R[19]
IF R[19]
RF R[20]
IF R[20]
Fo Output State
Disabled (Note 12)
(RF LD)
(IF LD)
(RF Fo)
(IF Fo)
0
0
1
0
1
0
0
1
1
0
1
0
1
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
1
0
1
0
1
1
1
1
0
IF Lock Detect (Note 13)
1
RF Lock Detect (Note 13)
1
RF/IF Lock Detect (Note 13)
IF Reference Divider Output
RF Reference Divider Output
IF Programmable Divider Output
RF Programmable Divider Output
Fastlock (Note 14)
X
X
X
X
0
0
IF Counter Reset (Note 15)
RF Counter Reset (Note 15)
IF and RF Counter Reset (Note 15)
1
1
X = don’t care condition
Note 12: When the F LD output is disabled, it is actively pulled to a low logic state.
o
Note 13: Lock detect output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked.
Note 14: The Fastlock mode utilizes the F LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
o
occurs whenever the RF loop’s lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock).
Note 15: The IF Counter Reset mode resets IF PLL’s R and N counters and brings IF charge pump output to a TRI-STATE condition. The RF Counter Reset mode
resets RF PLL’s R and N counters and brings RF charge pump output to a TRI-STATE condition. The IF and RF Counter Reset mode resets all counters and brings
both charge pump outputs to a TRI-STATE condition. Upon removal of the Reset bits then N counter resumes counting in “close” alignment with the R counter. (The
maximum error is one prescaler cycle.)
POWERDOWN OPERATION
Powerdown Mode Select Table
Synchronous and asynchronous powerdown modes are
both available by MICROWIRE selection. Synchronous pow-
erdown occurs if the respective loop’s R18 bit (Do
TRI-STATE) is LOW when its N20 bit (Pwdn) becomes HI.
Asynchronous powerdown occurs if the loop’s R18 bit is HI
when its N20 bit becomes HI.
R18
0
N20
0
Powerdown Status
PLL Active
PLL Active
(Charge Pump Output TRI-STATE)
Synchronous Powerdown Initiated
Asynchronous Powerdown Initiated
1
0
0
1
1
1
In the synchronous powerdown mode, the powerdown func-
tion is gated by the charge pump to prevent unwanted
frequency jumps. Once the powerdown program bit N20 is
loaded, the part will go into powerdown mode when the
charge pump reaches a TRI-STATE condition.
In the asynchronous powerdown mode, the device powers
down immediately after the LE pin latches in a HI condition
on the powerdown bit N20.
Activation of either the IF or RF PLL powerdown conditions
in either synchronous or asynchronous modes forces the
respective loop’s R and N dividers to their load state condi-
tion and debiasing of its respective fIN input to a high imped-
ance state. The oscillator circuitry function does not become
disabled until both IF and RF powerdown bits are activated.
The MICROWIRE control register remains active and ca-
pable of loading and latching data during all of the power-
down modes.
The device returns to an actively powered up condition in
either synchronous or asynchronous modes immediately
upon LE latching LOW data into bit N20.
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12
Functional Description (Continued)
SERIAL DATA INPUT TIMING
DS101366-10
Note 1: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Note 2: t = Data to Clock Set-Up Time
cs
t
t
t
t
t
= Data to Clock Hold Time
CH
= Clock Pulse Width High
= Clock Pulse Width Low
CWH
CWL
= Clock to Load Enable Set-Up Time
= Load Enable Pulse Width
ES
EW
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V /2. The test waveform has an edge rate of 0.6 V/ns with
CC
@
@
V
CC
amplitudes of 2.2V
V
= 2.7V and 2.6V
= 5.5V.
CC
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
DS101366-11
Notes: Phase difference detection range: −2π to +2π
The minimum width pump up and pump down current pulses occur at the D pin when the loop is locked.
o
R16 = HIGH
13
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Typical Application Example
DS101366-12
Operational Notes:
*
VCO is assumed AC coupled.
**
R
increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω to 200Ω depending on the VCO
IN
power level. f RF impedance ranges from 40Ω to 100Ω. f IF impedances are higher.
IN
IN
***
Adding RC filters to the V
lines is recommended to reduce loop-to-loop noise coupling.
CC
DS101366-13
Application Hints:
Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful
board layout.
This is an electrostatic sensitive device. It should be handled only at static free work stations.
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14
Application Information
A block diagram of the basic phase locked loop is shown in Figure 1.
DS101366-14
FIGURE 1. Basic Charge Pump Phase Locked Loop
LOOP GAIN EQUATIONS
A linear control system model of the phase feedback for a
PLL in the locked state is shown in Figure 2. The open loop
gain is the product of the phase comparator gain (Kφ), the
VCO gain (KVCO/s), and the loop filter gain Z(s) divided by
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in Figure 3, while
the complex impedance of the filter is given in Equation (1).
(4)
From Equations (2), (3) we can see that the phase term will
be dependent on the single pole and zero such that the
phase margin is determined in Equation (5).
−1
φ(ω) = tan
(ω • T2) − tan−1 (ω • T1) + 180˚
(5)
A plot of the magnitude and phase of G(s)H(s) for a stable
loop, is shown in Figure 4 with a solid trace. The parameter
φp shows the amount of phase margin that exists at the point
the gain drops below zero (the cutoff frequency wp of the
loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop band-
width, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison
frequency also diminishes, the spurs would have increased
by approximately 6 dB. In the proposed Fastlock scheme,
the higher spur levels and wider loop filter conditions would
exist only during the initial lock-on phase—just long enough
to reap the benefits of locking faster. The objective would be
to open up the loop bandwidth but not introduce any addi-
tional complications or compromises related to our original
design criteria. We would ideally like to momentarily shift the
curve of Figure 4 over to a different cutoff frequency, illus-
trated by the dotted line, without affecting the relative open
loop gain and phase relationships. To maintain the same
gain/phase relationship at twice the original cutoff frequency,
other terms in the gain and phase Equation (4) and Equation
(5) will have to compensate by the corresponding “1/w” or
“1/w2” factor. Examination of equations Equations (2), (3)
and Equation (5) indicates the damping resistor variable R2
could be chosen to compensate the “w”’ terms for the phase
margin. This implies that another resistor of equal value to
R2 will need to be switched in parallel with R2 during the
initial lock period. We must also insure that the magnitude of
the open loop gain, H(s)G(s) is equal to zero at wp’ = 2wp.
DS101366-15
FIGURE 2. PLL Linear Model
DS101366-16
FIGURE 3. Passive Loop Filter
(1)
The time constants which determine the pole and zero fre-
quencies of the filter transfer function can be defined as
(2)
and
K
vco, Kφ, N, or the net product of these terms can be
T2 = R2 • C2
(3)
changed by a factor of 4, to counteract the w2 term present
in the denominator of Equation (2) and Equation (3). The Kφ
term was chosen to complete the transformation because it
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, ω, the filter time constants T1 and T2,
and the design constants Kφ, KVCO, and N.
15
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Application Information (Continued)
can readily be switched between 1X and 4X values. This is
accomplished by increasing the charge pump output current
from 1 mA in the standard mode to 4 mA in Fastlock.
DS101366-17
FIGURE 4. Open Loop Response Bode Plot
FASTLOCK CIRCUIT IMPLEMENTATION
A diagram of the Fastlock scheme as implemented in Na-
tional Semiconductors LMX233xU PLL is shown in Figure 5.
When a new frequency is loaded, and the RF Icpo bit is set
high, the charge pump circuit receives an input to deliver 4
times the normal current per unit phase error while an open
drain NMOS on chip device switches in a second R2 resistor
element to ground. The user calculates the loop filter com-
ponent values for the normal steady state considerations.
The device configuration ensures that as long as a second
identical damping resistor is wired in appropriately, the loop
will lock faster without any additional stability considerations
to account for. Once locked on the correct frequency, the
user can return the PLL to standard low noise operation by
sending a MICROWIRE instruction with the RF Icpo bit set
low. This transition does not affect the charge on the loop
filter capacitors and is enacted synchronously with the
charge pump output. This creates a nearly seamless change
between Fastlock and standard mode.
DS101366-18
FIGURE 5. Fastlock PLL Architecture
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16
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM)
Order Number LMX2330UTM, LMX2331UTM or LMX2332UTM
*
For Tape and Reel (2500 units per reel)
Order Number LMX2330UTMX, LMX2331UTMX or LMX2332UTMX
NS Package Number MTC20
17
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Pin Chip Scale Package
Order Number LMX2330USLB, LMX2331USLB or LMX2332USLB
*
For Tape and Reel (2500 Units per Reel)
Order Number LMX2330USLBX, LMX2331USLBX or LMX2332USLBX
NS Package Number SLB24A
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systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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