LMX2350SLBX_技术文档

March 2001

LMX2350/LMX2352

PLLatinum Fractional N RF / Integer N IF

Dual Low Power Frequency Synthesizer

LMX2350 2.5 GHz/550 MHz

LMX2352 1.2 GHz/550 MHz

LMX2352 family features very low current consumption; typi-

cally LMX2350 (2.5 GHz) 6.5 mA, LMX2352 (1.2 GHz) 4.75

mA at 3.0V. The LMX2350/2352 are available in a 24-pin

TSSOP and 24-pin CSP surface mount plastic package.

General Description

The LMX2350/2352 is part of a family of monolithic inte-

grated fractional N/ Integer N frequency synthesizers de-

signed to be used in a local oscillator subsystem for a radio

transceiver. It is fabricated using National’s 0.5µ ABiC V

silicon BiCMOS process. The LMX2350/2352 contains dual

modulus prescalers along with modulo 15 or 16 fractional

compensation circuitry in the RF divider. A 16/17 or 32/33

prescale ratio can be selected for the LMX2350, and the

LMX2352 provides 8/9 or 16/17 prescale ratios. The IF

circuitry for both the LMX2350 and LMX2352 contains an 8/9

prescaler, and is fully programmable. Using a fractional N

phase locked loop technique, the LMX2350 /52 can gener-

ate very stable low noise control signals for UHF and VHF

voltage controlled oscillators (VCOs).

Features

n 2.7 V to 5.5 V operation

n Low current consumption

LMX2350: Icc = 6.75mA typ at 3v

LMX2352: Icc = 5.00mA typ at 3v

n Programmable or logical power down mode

Icc = 5 µA typ at 3v

n Modulo 15 or 16 fractional RF N divider supports ratios

of 1, 2, 3, 4, 5, 8, 15, or 16

n Programmable charge pump current levels

RF 100µA to 1.6mA in 100µA steps

IF 100µA or 800 µA

n Digital filtered lock detect

For the RF PLL, a highly flexible 16 level programmable

charge pump supplies output current magnitudes from

100µA to 1.6mA. Two uncommitted CMOS outputs can be

used to provide external control signals, or configured to

Applications

n Portable wireless communications (PCS/PCN, cordless)

n Dual mode cellular telephone systems

n Zero blind slot TDMA systems

™

FastLock

mode. Serial data is transferred into the

n Spread spectrum communication systems (CDMA)

n Cable TV Tuners (CATV)

LMX2350/2352 via a three wire interface (Data, LE, Clock).

Supply voltage can range from 2.7 V to 5.5 V. The LMX2350/

Block Diagram

DS100831-1

DS100831

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Connection Diagrams

DS100831-2

Order Number LMX2350TM or LMX2352TM

NS Package Number MTC24

DS100831-22

Pin Descriptions

Pin No.

for CSP

Pin No. Pin Name

for

I/O

Description

Package TSSOP

package

24

1

2

OUT0

Vcc_RF

O

-

Programmable CMOS output. Level of the output is controlled by IF_N [17] bit.

RF PLL power supply voltage input. Must be equal to Vcc_IF. May range from 2.7 V to

5.5 V. Bypass capacitors should be placed as close as possible to this pin and be

connected directly to the ground plane.

2

3

4

V_p

-

Power supply for RF charge pump. Must be ≥V_ccand V_cc.

RF IF

RF

CP_o

O

RF charge pump output. Connected to a loop filter for driving the control input of an

external VCO.

RF

4

5

6

5

6

7

GND

-

I

Ground for RF PLL digital circuitry.

fin RF

RF prescaler input. Small signal input from the VCO.

RF prescaler complimentary input. A bypass capacitor should be placed as close as

possible to this pin and be connected directly to the ground plane.

7

8

9

GND

-

Ground for RF PLL analog circuitry.

OSCx

I/O

Dual mode oscillator output or RF R counter input. Has a Vcc/2 input threshold when

configured as an input and can be driven from an external CMOS or TTL logic gate.

Can also be configured as an output to work in conjunction with OSCin to form a

crystal oscillator. (See functional description 1.1 and programming description 3.1.)

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2

Pin Descriptions (Continued)

Pin No.

for CSP

Pin No. Pin Name

for

I/O

Description

Package TSSOP

package

9

10

OSCin

I

Oscillator input which can be configured to drive both the IF and RF R counter inputs

or only the IF R counter depending on the state of the OSC programming bit. (See

functional description 1.1 and programming description 3.1.)

10

11

12

FoLD

O

I

Multiplexed output of N or R divider and RF/IF lock detect. Active High/Low CMOS

output except in analog lock detect mode. (See programming description 3.1.5.)

RF PLL Enable. Powers down RF N and R counters, prescaler, and will TRI-STATE^®

the charge pump output when LOW. Bringing RF_EN high powers up RF PLL

depending on the state of RF_CTL_WORD. (See functional description 1.9.)

RF_EN

12

13

IF_EN

I

IF PLL Enable. Powers down IF N and R counters, prescaler, and will TRI-STATE the

charge pump output when LOW. Bringing IF_EN high powers up IF PLL depending on

the state of IF_CTL_WORD. (See functional description 1.9.)

13

14

15

14

15

16

CLOCK

DATA

LE

I

High impedance CMOS Clock input. Data for the various counters is clocked into the

24 - bit shift register on the rising edge.

Binary serial data input. Data entered MSB first. The last two bits are the control bits.

High impedance CMOS input.

Load enable high impedance CMOS input. Data stored in the shift registers is loaded

into one of the 4 internal latches when LE goes HIGH. (See functional description 1.7.)

16

17

18

GND

fin IF

-

I

Ground for IF analog circuitry.

IF prescaler complimentary input. A bypass capacitor should be placed as close as

possible to this pin and be connected directly to the ground plane.

18

19

20

19

20

21

fin IF

GND

CPo_IF

I

-

IF prescaler input. Small signal input from the VCO.

Ground for IF digital circuitry.

O

IF charge pump output. For connection to a loop filter for driving the input of an

external VCO.

21

22

23

Vp_IF

-

Power supply for IF charge pump. Must be ≥ V_ccand V_cc.

RF IF

Vcc_IF

IF power supply voltage input. Must be equal to Vcc_RF. Input may range from 2.7 V to

5.5 V. Bypass capacitors should be placed as close as possible to this pin and be

connected directly to the ground plane.

23

24

OUT1

O

Programmable CMOS output. Level of the output is controlled by IF_N [18] bit.

3

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Value

Parameter

Power Supply Voltage

Symbol

Vcc_RF

Vcc_IF

Vp_RF

Vp_IF

Vi

Min

-0.3

-65

Typ

Max

6.5

Units

V

6.5

V

6.5

V

6.5

V

Voltage on any pin with GND = 0 volts

Storage Temperature Range

Vcc + 0.3

+150

+260

V

Ts

C˚

Lead Temperature (Solder 4 sec.)

T_L

Recommended Operating Conditions

Value

Typ

Parameter

Symbol

Vcc_RF

Vcc_IF

Vp_RF

Vp_IF

Min

Max

Units

Power Supply Voltage

2.7

Vcc_RF

Vcc

5.5

Vcc_RF

5.5

V

C

Vcc

5.5

Operating Temperature

TA

-40

+ 85

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage

to the device may occur. Operating Ratings indicate conditions for which the

device is intended to be functional, but do not guarantee specific perfor-

mance limits. For guaranteed specifications and test conditions, see the

Electrical Characteristics. The guaranteed specifications apply only for the

test conditions listed.

Note 2: This Device is a high performance RF integrated circuit with an ESD

<

rating

2 KV and is ESD sensitive. Handling and assembly of this device

should only be done at ESD-free workstations.

<

Electrical Characteristics (V_cc= V_cc= V_P= V_P_IF= 3.0V; −40˚ C T_A85˚ C except as specified)

RF

IF

RF

Sym-

bol

Parameter

Conditions

Min

Typ

Max

Units

General

I_cc

Power Supply Current

LMX2350

LMX2352

RF and IF,

V_cc= 2.7V to 5.5V

6.5

8.75

6.0

mA

RF and IF,

4.75

V

_cc= 2.7V to 5.5V

LMX2350/52 IF only, V_cc= 2.7V to 5.5V

RF_EN = IF_EN = LOW

1

5

2.2

20

mA

µA

I_CC-PWDNPower Down Current

f_inRF

RF Operating

Frequency

LMX2350

Prescaler = 32 (Note 3)

Prescaler = 16 (Note 3)

Prescaler = 8 (Note 3)

1.2

0.5

0.25

10

2.5

1.2

0.5

550

50

GHz

MHz

LMX2352

f_inIF

f_OSC

IF Operating Frequency

Oscillator Frequency

No load on OSCx (Note 3)

2

With resonator load on

OSCx (Note 3)

2

20

fφ

Phase Detector Frequency

RF Input Sensitivity

RF and IF

10

0

MHz

dBm

V_PP

Pf_{in RF}

2.7V≤V_CC≤3.0V

3.0V≤V_CC≤5.5V

2.7 V≤V_CC≤ 5.5V

OSCin, OSCx

−15

−10

0.5

0

Pf_{in IF}

V_OSC

IF Input Sensitivity

Oscillator Sensitivity

0

V_CC

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4

<

Electrical Characteristics (V_cc= V_cc= V_P= V_P_IF= 3.0V; −40˚ C T_A85˚ C except as

RF

IF

RF

specified) (Continued)

All Min/Max specifications are guaranteeed by design, or test, or statistical methods.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Charge Pump

ICPo-_source

RF

RF Charge Pump

Output Current (see

Programming

VCPo Vp/2, RF_CP_WORD = 0000

−100

µA

ICPo-_{sink RF}

VCPo = Vp/2, RF_CP_WORD = 0000

VCPo = Vp/2, RF_CP_WORD = 1111

100

µA

Description 3.2.2)

ICPo-_source

RF

−1.6

mA

ICPo-_{sink RF}

VCPo = Vp/2, RF_CP_WORD = 1111

1.6

mA

µA

ICPo-_source

IF

IF Charge Pump Output VCPo = Vp/2, CP_GAIN_8 = 0

Current (see

−100

Programming

Description 3.1.4)

ICPo-_{sink IF}

VCPo = Vp/2, CP_GAIN_8 = 0

VCPo = Vp/2, CP_GAIN_8 = 1

100

µA

ICPo-_source

IF

−800

ICPo-_{sink IF}

ICPo-_Tri

VCPo = Vp/2, CP_GAIN_8 = 1

800

µA

nA

Charge Pump

TRI-STATE Current

0.5 ≤ VCPo ≤ Vp - 0.5

-2.5

2.5

10

<

-40˚ C TA 85˚ C

ICPo-_sink

vs.

ICPo-_source

CP Sink vs. Source

Mismatch

VCPo = Vp/2

TA = 25˚ C

RFICPo

= 400 µA - 1.6 mA

3

4

8

%

ICPo vs.

VCPo

CP Current vs. Voltage

0.5 ≤ VCPo ≤ Vp -

0.5

RFICPo

= 800 µA - 1.6 mA

15

T_A= 25˚ C

ICPo vs. T

CP Current vs

Temperature

VCPo = Vp/2

<

-40˚ C TA 85˚ C

Digital Interface

V_IH

V_IL

I_IH

High-level Input Voltage (Note 4)

0.8 Vcc

V

Low-level Input Voltage

High-level Input Current

Low-level Input Current

Oscillator Input Current

(Note 4)

0.2 Vcc

1.0

V

V_IH= V_CC= 5.5 V, (Note 4)

V_IL= 0, V_CC= 5.5 V, (Note 4)

V_IH= V_CC= 5.5 V

−1.0

µA

V

I_IL

1.0

I_IH

100

I_IL

V_IL= 0, V_CC= 5.5 V

I_OH= −500 µA

−100

V_OH

High-level Output

Voltage

V_CC−0.4

V_OL

High-level Output

Voltage

I_OL= 500 µA

0.4

V

MICROWIRE Timing

t_CSData to Clock Setup

See Data Input Timing

50

10

ns

Time

t_CH

Data to Clock Hold

Time

t_CWH

t_CWL

t_ES

Clock Pulse Width High

Clock Pulse Width Low

See Data Input Timing

50

ns

Clock to Load Enable

Set Up Time

t_EW

Load Enable Pulse

Width

See Data Input Timing

50

ns

Note 3: Minimum operating frequencies are not production tested - only characterized.

Note 4: except fin, OSCin and OSCx

5

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Charge Pump Current Specification Definitions

DS100831-7

I1 = CP sink current at V = Vp − ∆V

Do

I2 = CP sink current at V = Vp/2

Do

I3 = CP sink current at V = ∆V

Do

I4 = CP source current at V = Vp − ∆V

Do

I5 = CP source current at V = Vp/2

Do

I6 = CP source current at V = ∆V

Do

∆V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V

and ground. Typical values are between 0.5V and 1.0V.

CC

1

2

Note 5: I vs V = Charge Pump Output Current magnitude variation vs Voltage = [¹⁄

2

{||1| − ||3|}]/[ ⁄

2

{||1| + ||3|}] 100% and [ ⁄

2

*

{||4| − ||6|}]/[ ⁄ {||4| +

Do

*

||6|}] 100%

= Charge Pump Output Current Sink vs Source Mismatch = [||2| − ||5|]/[¹⁄

Do-source

2

* *

{||2| + ||5|}] 100%

Note 6: I

vs I

Do-sink

@

*

@

Note 7: I vs T = Charge Pump Output Current magnitude variation vs Temperature = [||2 temp| − ||2 25˚C|]/||2 25˚C| 100% and [||5 temp| − ||5

Do

A

@

*

25˚C|]/||5 25˚C| 100%

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6

RF Sensitivity Test Block Diagram

DS100831-8

Note: N = 10,000 R = 50 P = 32

Note: Sensitivity limit is reached when the error of the divided RF output, F LD, is ≥ 1 Hz.

o

Typical Performance Characteristics

I_CCvs V_CC

LMX2350

I_CCvs V_CC

LMX2352

DS100831-9

DS100831-10

I_CPOTRI-STATE vs

CP_OVoltage

Charge Pump Current vs CP_OVoltage

RF_CP_WORD = 0000 and 0111

IF CP_GAIN_8 = 0 and 1

DS100831-11

DS100831-12

7

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Typical Performance Characteristics (Continued)

Charge Pump Current vs CP_OVoltage

RF_CP_WORD = 0011 and 1111

Sink vs Source Mismatch

(See (Note 6) under Charge Pump Current

Specification Definitions)

DS100831-13

DS100831-14

RF Input Impedance

V_CC= 2.7V to 5.5V, f_IN= 50 MHz to

3 GHz (f_INCapacitor = 100 pF)

IF Input Impedance

V_CC= 2.7V to 5.5V, f_IN= 10 MHz to

1 GHz (f_INCapacitor = 100 pF)

DS100831-15

DS100831-16

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Typical Performance Characteristics (Continued)

LMX2350 RF Sensitivity vs Frequency

LMX2352 RF Sensitivity vs Frequency

DS100831-18

DS100831-17

IF Input Sensitivity vs Frequency

Oscillator Input Sensitivity vs Frequency

DS100831-19

DS100831-20

LMX2350 V_PVoltage vs V_PLoad Current in Vdoubler

Mode, T = 25˚C

DS100831-21

9

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and a 10 bit B Counter. The LMX2350 is capable of operat-

ing from 500 MHz to 1.2 GHz with the 16/17 prescaler

offering a continuous integer divide range from 272 to

16399, and 1.2 GHz to 2.5 GHz with the 32/33 prescaler

offering a continuous integer divide range from 1056 to

32767. The LMX2352 RF N counter is 18 bits with 14 bits

integer divide and 4 bits fractional. The integer part is con-

figured as a 4 bit A Counter and a 10 bit B Counter. The

LMX2352 is capable of operating from 250 MHz to 500 MHz

with the 8/9 prescaler offering a continuous integer divide

range from 72 to 8199, and 500MHz to 1.2 GHz with 16/17

prescaler offering a continuous integer divide range from 272

to 16383. The RF counters for the LMX2350 family also

contain fractional compensation, programmable in either

1/15 or 1/16 modes. Both LMX2350 and LMX2352 IF N

counters are 15 bit integer dividers configured with a 3 bit A

Counter and a 12 bit B Counter offering a continuous integer

divide range from 56 to 32,767 over the frequency range of

10 MHz to 550 MHz. The IF N counters do not include

fractional compensation.

Functional Description

1.0 General

The basic phase-lock-loop (PLL) configuration consists of a

high-stability crystal reference oscillator, a frequency synthe-

sizer such as the National Semiconductor LMX2350/52, a

voltage controlled oscillator (VCO), and a passive loop filter.

The frequency synthesizer includes a phase detector, cur-

rent mode charge pump, as well as programmable reference

[R] and feedback [N] frequency dividers. The VCO frequency

is established by dividing the crystal reference signal down

via the R counter to obtain a frequency that sets the com-

parison frequency. This reference signal, fr, is then pre-

sented to the input of a phase/frequency detector and com-

pared with another signal, fp, the feedback signal, which was

obtained by dividing the VCO frequency down by way of the

N counter and fractional circuitry. The phase/frequency de-

tector’s current source outputs pump charge into the loop

filter, which then converts the charge into the VCO’s control

voltage. The phase/frequency comparator’s function is to

adjust the voltage presented to the VCO until the feedback

signal’s frequency (and phase) match that of the reference

signal. When this ’phase-locked’ condition exists, the RF

VCO’s frequency will be N+F times that of the comparison

frequency, where N is the integer divide ratio and F is the

fractional component. The fractional synthesis allows the

phase detector frequency to be increased while maintaining

the same frequency step size for channel selection. The

division value N is thereby reduced giving a lower phase

noise referred to the phase detector input, and the compari-

son frequency is increased allowing faster switching times.

1.3.1 Prescaler

The RF and IF inputs to the prescaler consist of fin and /fin;

which are complimentary inputs to differential pair amplifiers.

The complimentary inputs are internally coupled to ground

with a 10 pF capacitor. These inputs are typically AC coupled

to ground through external capacitors as well. The input

buffer drives the A counter’s ECL D-type flip flops in a dual

modulus configuration. A 16/17 or 32/33 prescale ratio can

be selected for the LMX2350, and the lower frequency

LMX2352 provides 8/9 or 16/17 prescale ratios. The IF

circuitry for both the LMX2350 and LMX2352 contain an 8/9

prescaler. The prescaler clocks the subsequent CMOS flip-

flop chain comprising the fully programmable A and B

counters.

1.1 Reference Oscillator Inputs

The reference oscillator frequency for the RF and IF PLL’s is

provided by either an external reference through the OSCin

pin and OSCx pin, or an external crystal resonator across

the OSCin and OSCx pins. OSCin/OSCx block can operate

to 50MHz with an input sensitivity of 0.5Vpp. The OSC bit

(see programming description 3.1.1), selects whether the

oscillator input pins OSCin and OSCx drive the IF and RF R

counters separately (Low) or by a common input signal path

(Hi). The common OSC mode allows the user to form a local

crystal oscillator circuit or drive the OSCin pin from an ex-

ternal signal source. When a crystal resonator is connected

between OSCin and OSCx along with 2 external capacitors

to form a crystal oscillator both reference chains are driven

simultaneously. When a TCXO is connected only at the

OSCin input pin and not at the OSCx pin, the TCXO drives

both IF R counter and RF R counter. When configured as

separate inputs, the OSCin pin drives the IF R counter while

the OSCx drives the RF R counter. The inputs have a Vcc/2

input threshold and can be driven from an external CMOS or

TTL logic gate.

1.3.2 Fractional Compensation

The fractional compensation circuitry of the LMX2350 and

LMX2352 RF dividers allow the user to adjust the VCO’s

tuning resolution in 1/16 or 1/15 increments of the phase

detector comparison frequency. A 4 bit register is pro-

grammed with the fractions desired numerator, while another

bit selects between fractional 15 and 16 modulo base de-

nominator (see programming description 4.2.4). An integer

average is accomplished by using a 4 bit accumulator. A

variable phase delay stage compensates for the accumu-

lated integer phase error, minimizing the charge pump duty

cycle, and reducing spurious levels. This technique elimi-

nates the need for compensation current injection in to the

loop filter. Overflow signals generated by the accumulator

are equivalent to 1 full VCO cycle, and result in a pulse

swallow.

1.4 Phase/Frequency Detector

The RF and IF phase(/frequency) detectors are driven from

their respective N and R counter outputs. The maximum

frequency at the phase detector inputs is about 10 MHz for

some high frequency VCO due to the minimum continuous

divide ratio of the dual modulus prescaler. For example if the

phase detector frequency exceeds 2.37 MHz, there are

higher chances of running into illegal divide ratios, because

the mimimum continuous divide ratio of the LMX2350 with

32/33 prescaler is 1056. The phase detector outputs control

the charge pumps. The polarity of the pump-up or pump-

down control is programmed using RF_PD_POL or IF_PD-

_POL depending on whether RF/IF VCO characteristics are

positive or negative (see programming descriptions 3.1.4

1.2 Reference Dividers (R Counters)

The RF and IF R Counters are clocked through the oscillator

block either separately or in common. The maximum fre-

quency is 50MHz. Both R Counters are 15 bit CMOS

counters with a divide range from 3 to 32,767. (See program-

ming description 3.1.3.)

1.3 Programmable Dividers (N Counters)

The RF and IF N Counters are clocked by the small signal fin

RF and fin IF input pins respectively. The LMX2350 RF N

counter is 19 bits with 15 bits integer divide and 4 bits

fractional. The integer part is configured as a 5 bit A Counter

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10

signal is also selectable. The lock detect output is always low

when the PLL is in power down mode. See programming

descriptions 3.1.5, 4.6 - 4.8 for more details.

Functional Description (Continued)

and 3.2.2). The phase detector also receives a feedback

signal from the charge pump, in order to eliminate dead

zone.

1.9 Power Control

Each PLL is individually power controlled by device enable

pins or MICROWIRE power down bits. The enable pins

override the power down bits except for the V2_EN bit. The

RF_EN pin controls the RF PLL; IF_EN pin controls the IF

PLL. When both pins are high, the power down bits deter-

mine the state of power control (see programming descrip-

tion 3.2.1.2). Activation of any PLL power down mode results

in the disabling of the respective N counter and de-biasing of

its respective Fin input (to a high impedance state). The R

counter functionality also becomes disabled when the power

down bit is activated. The reference oscillator block powers

down and the OSCin pin reverts to a high impedance state

when both RF and IF enable pins or power down bit’s are

asserted, unless the V2_EN bit (RF_R[22]) is high. Power

down forces the respective charge pump and phase com-

parator logic to a TRI-STATE condition. A power down

counter reset function resets both N and R counters. Upon

powering up the N counter resumes counting in “close”

alignment with the R counter (The maximum error is one

prescaler cycle). The MICROWIRE control register remains

active and capable of loading and latching in data during all

of the power down modes.

1.5 Charge Pump

The phase detector’s current source outputs pump charge

into an external loop filter, which then converts the charge

into the VCO’s control voltage. The charge pumps steer the

charge pump output, CPo, to Vcc (pump-up) or ground

(pump-down). When locked, CPo is primarily in

a

TRI-STATE^®mode with small corrections. The RF charge

pump output current magnitude is programmable from 100

µA to 1.6 mA in 100 µA steps as shown in table in program-

ming description 3.2.2. The IF charge pump is set to either

100µA or 800µA levels using bit IF_R [19] (see programming

description 3.1.4).

1.6 Voltage Doubler

The Vp_RFpin is normally driven from an external power

supply over a range of Vcc to 5.5v to provide current for the

RF charge pump circuit. An internal voltage doubler circuit

connected between the Vcc and VpRF supply pins alter-

±

nately allows Vcc = 3v ( 10%) users to run the RF charge

pump circuit at close to twice the Vcc power supply voltage.

The voltage doubler mode is enabled by setting the V2_EN

bit (RF_R [22]) to a HIGH level. The voltage doubler’s

charge pump driver originates from the RF oscillator input

(OSCx). The device will not totally powerdown until the

V2_EN bit is programmed low. The average delivery current

of the doubler is less than the instantaneous current demand

of the RF charge pump when active and is thus not capable

of sustaining a continuous out of lock condition. A large

external capacitor connected to Vp_RFis therefore needed to

control power supply droop when changing frequencies. Re-

fer to the application note AN-1119 for more details.

™

1.7 MICROWIRE Serial Interface

The programmable functions are accessed through the MI-

CROWIRE serial interface. The interface is made of 3 func-

tions: clock, data and latch enable (LE). Serial data for the

various counters is clocked in from data on the rising edge of

clock, into the 24- bit shift register. Data is entered MSB first.

The last two bits decode the internal register address. On the

rising edge of LE, data stored in the shift register is loaded

into one of the 4 appropriate latches (selected by address

bits). A complete programming description is included in the

following sections.

1.8 Fo/LD Multifunction Output

The Fo/LD output pin can deliver several internal functions

including analog/digital lock detects, and counter outputs.

See programming description 3.1.5 for more details.

1.8.1 Lock Detect

A digital filtered lock detect function is included with each

phase detector through an internal digital filter to produce a

logic level output available on the Fo/LD output pin if se-

lected. The lock detect output is high when the error between

the phase detector inputs is less than 15 nsec for 5 consecu-

tive comparison cycles. The lock detect output is low when

the error between the phase detector outputs is more than

30 nsec for one comparison cycle. An analog lock detect

11

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Programming Description

2.0 INPUT DATA REGISTER

The descriptions below describe the 24-bit data register loaded through the MICROWIRE Interface. The data register is used to

program the 15-bit IF_R counter register, and the 15-bit RF_R counter register, the 15-bit IF_N counter register, and the 19-bit

RF_N counter register. The data format of the 24-bit data register is shown below. The control bits CTL [1:0] decode the internal

register address. On the rising edge of LE, data stored in the shift register is loaded into one of the 4 appropriate latches (selected

by address bits). Data is shifted in MSB first

MSB

LSB

CTL [1:0]

DATA [21:0]

23

2

1

0

2.1 Register Location Truth Table

CTL [1:0]

DATA Location

1

0

1

0

1

0

1

IF_R register

IF_N register

RF_R register

RF_N register

2.2 Register Content Truth Table

First Bit

REGISTER BIT LOCATION

16 15 14 13 12 11 10

Last Bit

23

22

21 20 19

FoLD

18

17

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

IF_R

IF_N

OSC

FRAC_16

IF_CP_WORD

CMOS

IF_R_CNTR

IF_NB_CNTR

RF_R_CNTR

RF_NA_CNTR

IF_CTL_WORD

IF_NA_CNTR

FRAC_CNTR

RF_R DLL_MODE V2_EN

RF_N RF_CTL_WORD

RF_CP_WORD

RF_NB_CNTR

3.0 PROGRAMMABLE REFERENCE DIVIDERS

3.1 IF_R Register

If the Control Bits (CTL [1:0]) are 0 0, when LE is transitioned high data is transferred from the 24-bit shift register into a latch

which sets the IF PLL 15-bit R counter divide ratio. The divide ratio is programmed using the bits IF_R_CNTR as shown in table

3.1.3. The ratio must be ≥ 3. The IF_CP_WORD [1:0], programs the IF charge pump magnitude and polarity shown in 3.1.4. The

OSC bit is used to enable the crystal oscillator mode. FoLD [2:0] is used to set the function of the Lock Detect output (pin 11),

according to table 3.1.3.

MSB

OSC

23

LSB

0

FRAC_16

22

FoLD [2:0]

21

IF_CP_WORD [1:0]

18 17

IF_R_CNTR [14:0]

16

0

1

19

2

0

3.1.1 OSC

(IF_R[23])

The OSC bit, IF_R [23], selects whether the oscillator input pins OSCin and OSCx drive the IF and RF R counters separately or

by a common input signal path. When the OSC bit = 1, a crystal resonator can be connected between OSCin and OSCx together

with 2 capacitors to form a crystal oscillator. When OSC = 0 , the OSCin pin drives the IF R counter while the OSCx drives the

RF R counter.

3.1.2 FRAC_16

(IF_R[22])

The FRAC_16 bit, IF_R [22], is used to set the fractional compensation at either 1/16 and 1/15 resolution. When FRAC-16 is set

to one, the fractional modulus is set to 1/16 resolution, and FRAC_16 = 0 corresponds to 1/15 (See section 4.2.4).

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12

Programming Description (Continued)

3.1.3 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)

IF_R_CNTR/RF_R_CNTR

(IF_R[2]-[16])

Divide Ratio

14

0

13

0

12

0

11

0

10

0

9

0

-

8

0

-

7

0

-

6

0

-

5

0

-

4

0

-

3

0

-

2

0

1

-

1

0

-

0

1

0

-

3

4

-

0

-

32,767

1

Notes: Divide ratio: 3 to 32,767 (Divide ratios less than 3 are prohibited).

RF_R_CNTR/IF_R_CNTR These bits select the divide ratio of the programmable reference dividers.

3.1.4 IF_CP_WORD

(IF_R[17]-[18])

IF_CP_WORD

CP_GAIN_8

(IF_R [17] - [18] )

IF_PD_POL

BIT

LOCATION

FUNCTION

0

1

CP_GAIN_8

IF_PD_POL

IF_R [18]

IF_R [17]

IF Charge Pump Current Gain

IF Phase Detector Polarity

1X

8X

Negative

Positive

CP_GAIN_8 is used to toggle the IF charge pump current magnitude between 1x mode (100 uA typ) and 8x mode (800uA typ).

IF_PD_POL is set to one when IF VCO characteristics are positive. When IF VCO frequency decreases with increasing control

voltage IF_PD_POL should set to zero.

3.1.5 FoLD* Programming Truth Table

(IF_R[19]-[21])

FoLD

Fo/LD OUTPUT STATE

IF and RF Analog Lock Detect (Open Drain)

IF Digital Lock Detect

RF Digital Lock Detect

IF and RF Digital Lock Detect

IF R counter

0 0 0

1 0 0

0 1 0

1 1 0

0 0 1

1 0 1

IF N counter

0 1 1

1 1 1

RF R counter

RF N counter

*FoLD - Fout/Lock Detect PROGRAMMING BITS

3.2 RF_R Register

If the Control Bits (CTL [1:0]) are 1 0, data is transferred from the 24-bit shift register into the RF_R register latch which sets the

RF PLL 15-bit R counter divide ratio. The divide ratio is programmed using the RF_R_CNTR word as shown in table 3.1.3. The

divide ratio must be ≥ 3. The bits used to control the voltage doubler (V2_EN) and RF Charge Pump (RF_CP_WORD) are

detailed in 3.2.2.

MSB

LSB

0

DLL_MODE

23

V2_EN

22

RF_CP_WORD [4:0]

21

RF_R_CNTR [14:0]

16

1

17

2

0

13

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Programming Description (Continued)

3.2.1 (RF_R [22 - 23] )

DLL_MODE

V2_EN

BIT

LOCATION

FUNCTION

0

1

DLL_MODE

V2_EN

RF_R [23]

Delay Line Loop Calibration

Mode

Slow

Fast

RF_R [22]

RF_Voltage Doubler Enable

Disabled

Enabled

1. V2_EN bit when set high enables the voltage doubler for the RF Charge Pump supply.

2. DLL_MODE bit should be set to one for normal usage.

3.2.2 RF_CP_WORD

(RF_R[17]-[21])

CP_8X

CP_4X

CP_2X

CP_1X

RF_PD_POL

RF_PD_POL ( RF_R[17] ) should be set to one when RF VCO characteristics are positive. When RF VCO frequency decreases

with increasing control voltage RF_PD_POL should be set to zero.

CP_1x, CP_2x, CP_4x, and CP_8x are used to step the RF Charge Pump output current magnitude from 100 uA to 1.6 mA in

100uA steps as shown in the table below.

RF Charge Pump Output Truth Table

ICPo uA (typ)

CP8x

CP4x

CP2x

CP1x

RF_R[21]

RF_R[20]

RF_R[19]

RF_R[18]

100

200

300

400

-

0

-

0

-

0

1

-

0

1

0

1

-

900

-

1

-

0

-

0

-

0

-

1600

1

4.0 PROGRAMMABLE DIVIDERS (N COUNTERS)

4.1 IF_N Register

If the Control Bits (CTL [1:0]) are 01, data is transferred from the 24-bit shift register into the IF_N register latch which sets the

PLL 15 bit programmable N counter value and various control functions. The IF_N counter consists of the 3-bit swallow counter

(A counter), and the 12 bit programmable counter (B counter). Serial data format is shown below in tables 4.1.2 and 4.1.3. The

divide ratio (IF_NB_CNTR) must be ≥3. The divide ratio is programmed using the bits IF_N_CNTR as shown in tables 4.1.2 and

4.1.3. The divide ratio must be ≥56. The CMOS [3:0] bits program the 2 CMOS outputs detailed in section 4.4.

MSB

LSB

1

IF_CTL_WORD [2:0]

23

CMOS [3:0]

20

IF_NB_CNTR [11:0]

16

IF_NA_CNTR [2:0]

4

0

1

21

17

5

2

0

4.1.1 IF_CTL_WORD

(IF_R[21]-[23])

MSB

LSB

PWDN_MODE

IF_CNT_RST

PWDN_IF

Note: See section 4.2.1.2 for IF control word truth table.

www.national.com

14

Programming Description (Continued)

4.1.2 3-BIT IF SWALLOW COUNTER DIVIDE RATIO (IF A COUNTER)

Swallow Count

(IF_N[2]−[4])

IF_NA_CNTR

(A)

0

2

0

-

1

0

-

0

1

-

1

-

7

1

Note: Swallow Counter Value: 0 to 7

IF_NB_CNTR ≥ IF_NA_CNTR

Minimum continuous count = 56 ( A=0, B=7)

4.1.3 12-BIT IF PROGRAMMABLE COUNTER DIVIDE RATIO (IF B COUNTER)

IF_NB_CNTR

(IF_N[5]-[16])

Divide Ratio

11

0

10

0

9

0

-

8

0

-

7

0

-

6

0

-

5

0

-

4

0

-

3

0

-

2

1

0

-

0

1

0

-

3

0

1

-

4

-

0

-

4,095

1

Note: Divide ratio: 3 to 4095 (Divide ratios less than 3 are prohibited)

IF_NB_CNTR ≥ IF_NA_CNTR

N divider continuous integer divide ratio 56 to 32,767.

4.2 RF_N Register

If the control bits (CTL[2:0]) are 11, data is transferred from the 24-bit shift register into the RF_N register latch which sets the RF

PLL 19 bit programmable N counter register and various control functions. The RF N counter consists of the 5-bit swallow counter

(A counter) the 10 bit programmable counter (B counter), and 4 bit fractional counter. Serial data format is shown below. The

divide ratio (RF_NB_CNTR) must be ≥3, and must be ≥ the swallow counter value + 2; RF_NB_CNTR≥ ( RF_NA_CNTR+2).

MSB

LSB

1

RF_CTL_WORD [2:0]

23

RF_NB_CNTR [9:0]

20

RF_NA_CNTR [4:0]

10

FRAC_CONT [3:0]

5

1

21

11

6

2

0

4.2.1.1 RF_CTL_WORD

(RF_N[21]-[23])

MSB

LSB

RF_CNT_RST

PWDN_RF

PRESC_SEL

4.2.1.2 RF/IF Control Word Truth Table

BIT

FUNCTION

0

1

Reset

IF_CNT_RST/RF_CNT_RST

PWDN_IF/PWDN_RF

PWDN_MODE

IF/RF counter reset

Normal Operation

Powered up

IF/RF power down

Powered down

Power down mode select

Prescaler Modulus select

Asynchronous power down

Synchronous power down

PRESC

LMX2350

16/17

32/33

(0.5 to 1.2 GHz operation)

(1.2 to 2.5 GHz operation)

LMX2352

8/9

16/17

(0.25 to 0.5 GHz operation)

(0.5 to 1.2 GHz operation)

The Counter Reset enable bit when activated allows the

reset of both N and R counters. Upon powering up, the N

counter resumes counting in ’close’ alignment with the R

counter (the maximum error is one prescaler cycle).

pump and phase comparator logic to a TRI-STATE condition.

The MICROWIRE control register remains active and ca-

pable of loading and latching in data during all of the power

down modes.

Activation of the PLL power down bits result in the disabling

of the respective N counter divider and de-biasing of its

respective fin inputs (to a high impedance state). The re-

spective R counter functionality also becomes disabled

when the power down bit is activated. The OSCin pin reverts

to a high impedance state when both RF and IF power down

bits are asserted. Power down forces the respective charge

Both synchronous and asynchronous power down modes

are available with the LMX2350 family in order to adapt to

different types of applications. The power down mode bit

IF_N[21] is used to select between synchronous and asyn-

chronous power down. The MICROWIRE control register

remains active and capable of loading and latching in data

during all of the power down modes.

15

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4.2.2 5-BIT RF SWALLOW COUNTER DIVIDE RATIO

Programming Description (Continued)

(RF A COUNTER)

(RF_N[6]-[10])

Synchronous Power down Mode

Swallow Count

RF_NA_CNTR

One of the PLL loops can be synchronously powered down

by first setting the power down mode bit HIGH (IF_N[21] = 1)

and then asserting its power down bit (IF_N[22] or RF_N[22]

= 1). The power down function is gated by the charge pump.

Once the power down bit is loaded, the part will go into

power down mode upon the completion of a charge pump

pulse event.

(A)

0

4

0

-

3

0

-

2

1

0

1

-

0

-

0

-

1

-

31

1

Note: Swallow Counter Value LMX2350: 0 to 31; LMX2352: 0 to 15

RF_NB_CNTR ≥ RF_NA_CNTR + 2

Asynchronous Power down Mode

One of the PLL loops can be asynchronously powered down

by first setting the power down mode bit LOW (IF_N[21] = 0)

and then asserting its power down bit (IF_N[22] or RF_N[22]

= 1). The power down function is NOT gated by the charge

pump. Once the power down bit is loaded, the part will go

into power down mode immediately.

4.2.3 10-BIT RF PROGRAMMABLE COUNTER DIVIDE

RATIO (RF B COUNTER) (RF_N[11]-[20])

RF_NB_CNTR

Divide Ratio

9

0

-

8

0

-

7

0

-

6

0

-

5

0

-

4

0

-

3

0

-

2

0

1

-

1

0

-

0

1

0

-

Prescaler select is used to set the RF prescaler. The

LMX2350 is capable of operating from 500 MHz to 1.2 GHz

with the 16/17 prescaler, and 1.2 GHz to 2.5 GHz with the

32/33 prescaler selection. The LMX2352 is capable of oper-

ating from 250 MHz to 500 MHz with the 8/9 prescaler, and

500MHz to 1.2GHz with 16/17 prescaler selection.

3

4

-

1,023

1

Note: Divide ratio: 3 to 1023 (Divide ratios less than 3 are prohibited)

RF_NB_CNTR ≥ RF_NA_CNTR + 2

4.2.4 FRACTIONAL MODULUS ACCUMULATOR (FRAC_CNTR)

(RF_N[2]-[5])

Fractional Ratio (F)

FRAC_CNTR

Modulus 15

Modulus 16

RF_N[5]

RF_N[4]

RF_N[3]

RF_N[2]

0

1/15

2/15

-

0

-

0

-

0

1

-

0

1

0

-

1/16

2/16

-

14/15

N/A

14/16

15/16

1

0

1

4.3 PULSE SWALLOW FUNCTION

fvco = [N + F] x [fosc / R ]

N = (P x B) + A

F:

Fractional ratio (contents of FRAC_CNTR divided by

the fractional modulus)

fosc: Output frequency of the external reference frequency

oscillator

fvco: Output frequency of external voltage controlled oscil-

lator (VCO)

R:

Preset divide ratio of binary 15-bit programmable ref-

erence counter (3 to 16383)

B:

Preset divide ratio of binary 10-bit programmable

counter

P:

Preset modulus of dual modulus prescaler

(LMX2350:RF P=16 or 32, IF P=8)

A:

Preset value of binary 4 or 5-bit swallow counter (0 ≤

A ≤ 31 {RF} , 0 ≤ A ≤ 15 {IF} , A+2 ≤ B {RF}, A ≤ B {IF})

(LMX2352:RF P=8 or 16, IF P=8)

4.4 CMOS (Programmable CMOS outputs)

(IF_N[17]-[20])

MSB

LSB

OUT_0

FastLock

TEST

OUT_1

Note: Test bit is reserved and should be set to zero for normal usage.

www.national.com

16

Programming Description (Continued)

4.4.1 Programmable CMOS Output Truth Table

BIT

LOCATION

FUNCTION

0

1

OUT_0

IF_N[17]

OUT0 CMOS output pin level

set

LOW

HIGH

OUT_1

IF_N[18]

IF_N[20]

OUT1 CMOS output pin level

set

LOW

HIGH

FastLock

FastLock mode select

CMOS output

FastLock mode

When the FastLock bit is set to one, OUT_0 and OUT_1 are don’t care bits. FastLock mode utilizes the OUT0 and OUT1 output

pins to synchronously switch between active low and TRI-STATE. The OUT0 = LOW state occurs whenever the RF loop’s CP_8X

is selected HIGH while the FastLock bit is set HIGH (see programming description 3.2.2). The OUT0 pin reverts to TRI-STATE

when the CP_8X bit is LOW. Similarly for the IF loop, the synchronous activation of OUT1= LOW or TRI-STATE, is dependent on

whether the CP_GAIN_8 is high or low respectively (see programming description 3.1.4).

4.5 SERIAL DATA INPUT TIMING

DS100831-3

Note: Data shifted into register on clock rising edge. Data is shifted in MSB first.

TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around Vcc/2. The test waveform has an edge rate of 0.6 V/nsec

@

with amplitudes of 2.2V Vcc=2.7 V and 2.6V Vcc = 5.5 V.

17

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Programming Description (Continued)

4.6 LOCK DETECT DIGITAL FILTER

The Lock Detect Digital Filter compares the difference between the phase of the inputs of the phase detector to a RC generated

delay of approximately 15nS. To enter the locked state (Lock = HIGH) the phase error must be less than the 15nS RC delay for

5 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to approximately 30nS. To exit the locked

state (Lock = LOW), the phase error must become greater than the 30nS RC delay. When the PLL is in the power down mode,

Lock is forced LOW. A flow chart of the digital filter is shown at right.

DS100831-4

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18

Programming Description (Continued)

4.7 ANALOG LOCK DETECT FILTER

When the Fo/LD output is configured in analog lock detect mode an external lock detect circuit is needed in order to provide a

steady LOW signal when the PLL is in the locked state. A typical circuit is shown below. The fold output is active low (open drain)

only when analog lock detect mode is selected.

DS100831-5

4.8 TYPICAL LOCK DETECT TIMING

DS100831-6

19

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Physical Dimensions inches (millimeters) unless otherwise noted

Molded TSSOP, JEDEC Plastic Package (MTC24)

Order Number LMX2350TM or LMX2352TM

NS Package MTC24

www.national.com

20

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded CSP, JEDEC Plastic Package (SLB24A)

Order Number LMX2350SLB or LMX2352SLB

NS Package SLB24A

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型号：	LMX2350SLBX
厂家：	National Semiconductor
描述：	IC PLL FREQUENCY SYNTHESIZER, 2500 MHz, PQCC24, LAMINATE, CSP-24, PLL or Frequency Synthesis Circuit 信息通信管理
文件：	总23页 (文件大小：441K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMX2350SLBX [NSC]

相关型号：

LMX2350TM

LMX2350TM/NOPB

LMX2350TMX

LMX2350TMX/NOPB

LMX2352

LMX2352TM

LMX2352TM

LMX2352TM/NOPB

LMX2352TMX

LMX2352TMX/NOPB

LMX2353

LMX2353SLBX