LMX3161 [NSC]
Single Chip Radio Transceiver; 单芯片无线电收发器
| 型号： | LMX3161 |
| 厂家： | 
National Semiconductor |
| 描述： | Single Chip Radio Transceiver |
| 文件： | 总14页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
November 1999
LMX3161
Single Chip Radio Transceiver
vides a low cost, high performance solution for communica-
tions systems. The RSSI output may be used for channel
quality monitoring.
General Description
The LMX3161 Single Chip Radio Transceiver is a monolithic,
integrated radio transceiver optimized for use in a Digital En-
hanced Cordless Telecommunications (DECT) system. It is
The Single Chip Radio Transceiver is available in a 48-pin
7mm X 7mm X 1.4mm PQFP surface mount plastic pack-
age.
fabricated using National’s ABiC
V BiCMOS process
=
(fT 18 GHz).
The LMX3161 contains phase locked loop (PLL), transmit
and receive functions. The 1.1 GHz PLL block is shared be-
tween transmit and receive section. The transmitter includes
a frequency doubler, and a high frequency buffer. The re-
ceiver consists of a 2.0 GHz low noise mixer, an intermediate
frequency (IF) amplifier, a high gain limiting amplifier, a fre-
quency discriminator, a received signal strength indicator
(RSSI), and an analog DC compensation loop. The PLL,
doubler, and buffers can be used to implement open loop
modulation along with an external VCO and loop filter. The
circuit features on-chip voltage regulation to allow supply
voltages ranging from 3.0V to 5.5V. Two additional voltage
regulators provide a stable supply source to external dis-
crete stages in the Tx and Rx chains.
Features
n Single chip solution for DECT RF transceiver
n RF sensitivity to −93 dBm; RSSI sensitivity to −100 dBm
n Two regulated voltage outputs for discrete amplifiers
n High gain (85 dB) intermediate frequency strip
n Allows unregulated 3.0V–5.5V supply voltage
n Power down mode for increased current savings
n System noise figure 6.5 dB (typ)
Applications
n Digital Enhanced Cordless Telecommunications (DECT)
n Personal wireless communications (PCS/PCN)
n Wireless local area networks (WLANs)
n Other wireless communications systems
The IF amplifier, high gain limiting amplifier, and discrimina-
tor are optimized for 110 MHz operation, with a total IF gain
of 85 dB. The single conversion receiver architecture pro-
Block Diagram
DS012815-1
™
MICROWIRE is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS012815
www.national.com
LMX3161 Pin Diagram
DS012815-2
Top View
Order Number LMX3161VBH or LMX3161VBHX
See NS Package Number VBH48A
www.national.com
2
LMX3161 Pin Diagram (Continued)
Pin No.
Pin Name
VCC
I/O
—
O
Description
1
2
Power supply for CMOS section of PLL and ESD bussing.
MIXEROUT
VCC
IF output from the mixer.
3
—
—
I
Power supply for mixer section.
4
GND
RFIN
Ground.
5
RF input to the mixer.
6
GND
Tx VREG
VCC
—
—
—
—
O
Ground.
7
Regulated power supply for external PA gain stage.
8
Power supply for analog sections of PLL and doubler.
9
GND
TxOUT
GND
VCC
Ground.
10
11
12
13
14
15
16
Frequency doubler output.
—
—
—
—
I
Ground.
Power supply for analog sections of PLL and doubler.
GND
GND
fIN
Ground.
Ground.
RF Input to PLL and frequency doubler.
CE
I
Chip Enable. Pulling LOW powers down entire chip. Taking CE HIGH powers up the
appropriate functional blocks depending on the state of bits F6, F7, F11, and F12
programmed in F-latch. It is necessary to initialize the internal registers once, after the
power up reset. The registers’ contents are kept even in power-down condition.
17
18
19
20
21
VP
Do
—
O
Power supply for charge pump.
Charge pump output. For connection to a loop filter for driving the input of an external VCO.
VCC
—
—
O
Power supply for CMOS section of PLL and ESD bussing.
Ground.
GND
OUT 0
Programmable CMOS output. Refer to Function Register Programming Description section
for details.
22
23
24
Rx PD/OUT 1
Tx PD/OUT 2
PLL PD
I/O Receiver power down control input or programmable CMOS output. Refer to Function
Register Programming Description section for details.
I/O Transmitter power down control input or programmable CMOS output. Refer to Function
Register Programming Description section for details.
I
PLL power down control input. LOW for PLL normal operations, and HIGH for PLL power
saving.
™
25
26
27
28
29
CLOCK
DATA
LE
I
I
I
I
I
MICROWIRE clock input. High impedance CMOS input with Schmitt Trigger.
MICROWIRE data input. High impedance CMOS input with Schmitt Trigger.
MICROWIRE load enable input. High impedance CMOS input with Schmitt Trigger.
Oscillator input. High impedance CMOS input with feedback.
OSCIN
S FIELD
DC compensation circuit enable. While LOW, the DC compensation circuit is enabled and
the threshold is updated through the DC compensation loop. While HIGH, the switch is
opened, and the comparator threshold is held by the external capacitor.
30
31
32
33
34
35
36
37
38
39
40
41
RSSIOUT
THRESH
DC COMPIN
DISCOUT
GND
O
O
I
Received signal strength indicator (RSSI) output.
Threshold level to external comparator.
Input to DC compensation circuit.
Demodulated output of discriminator.
Ground.
O
—
—
I
VCC
Power supply for the discriminator circuit.
Quadrature input for tank circuit.
Power supply for limiter output stage.
Ground.
QUADIN
VCC
—
—
—
—
—
GND
VCC
Power supply for limiter gain stages.
Ground.
GND
VCC
Power supply for IF amplifier gain stages.
3
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LMX3161 Pin Diagram (Continued)
Pin No.
42
Pin Name
LIMIN
GND
I/O
I
Description
IF input to the limiter.
Ground.
43
—
O
—
—
I
44
IFOUT
VCC
IF output from IF amplifier.
Power supply for IF amplifier output.
Ground.
45
46
GND
47
IFIN
IF input to IF amplifier.
48
Rx VREG
—
Regulated power supply for external LNA stages.
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4
Absolute Maximum Ratings (Notes 1, 2)
Recommended Operating
Conditions
Power Supply Voltage (VCC
)
−0.3V to +6.5V
−0.3V to +6.5V
VP
Supply Voltage (VCC
)
3.0V to 5.5V
VCC to 5.5V
Voltage on Any Pin with
(VP)
=
GND 0V (VI)
−0.3V to VCC +0.3V
−65˚C to +150˚C
+260˚C
Operating Temperature (TA)
−10˚C to +70˚C
Storage Temperature Range (TS)
Lead Temp. (solder, 4 sec)(TL)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate condi-
tions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test condi-
tions, see the Electrical Characteristics section. The guaranteed specifica-
tions apply only for the test conditions listed.
Note 2: This device is a high performance RF integrated circuit with an ESD
<
rating
KeV and is ESD sensitive. Handling and assembly of this device
should only be done at ESD work stations.
Electrical Characteristics
=
=
The following specifications are guaranteed for VCC 3.6V and TA 25˚C, unless otherwise specified.
Symbol
Parameter
Current Consumption
Conditions
Min
Typ
Max
Unit
IDD, RX
IDD, TX
-Open-Loop Receive Mode
-Open-Loop Transmit Mode
PLL & TX chain powered down
PLL & RX chain powered down
RX & TX chain powered down
—
—
—
—
50
27
6
60
37
8
mA
mA
mA
µA
IDD, PLL -Closed-Loop PLL Mode
IPD
-Power Down Mode
—
70
=
=
= =
1780 MHz (fIN 890 MHz)
MIXER
fRF
fRF 1.89 GHz, fIF 110 MHz, f
LO
RF Frequency Range
(Note 3)
(Note 4)
1.7
—
—
—
—
14
−24
—
—
—
—
—
—
—
—
—
2.0
—
—
—
14
—
—
—
—
—
—
—
—
—
—
GHz
MHz
Ω
fIF
IF Frequency
110
15-j5
ZIN
Input Impedance, RFIN
Output Impedance, Mixer Out
Noise Figure (Single Side Band)
Conversion Gain
160-j70
ZOUT
NF
Ω
(Notes 5, 6)
(Note 5)
10
17
dB
GC
dB
P1dB
OIP3
Input 1dB Compression Point
Output 3rd Order Intercept Point
Fin to RF Isolation
(Note 5)
−20
7.5
dBm
dBm
dB
(Note 5)
=
F
F
IN-RF
FIN 890 MHz
−30
−10.6
−30
−30
−30
−30
−30
=
fIN 1780 MHz
dB
=
fIN 2670 MHz
dB
=
IN-IF
Fin to IF Isolation
RF to IF Isolation
fIN 890 MHz
dB
=
fIN 1780 MHz
dB
=
fIN 2670 MHz
dB
=
RF–IF
IF AMPLIFIER
PIN 0 to −85 dB
dB
=
fIN 110 MHz
NF
Noise Figure
(Note 7)
(Note 7)
—
15
—
—
8
11
—
—
—
dB
dB
Ω
AV
Gain
24
150–j120
ZIN
Input Impedance
Output Impedance
190–j20
ZOUT
Ω
=
IF LIMITER
fIN 110 MHz
−3
=
Sens
IFIN
Limiter/Discriminator Sensitivity
IF Limiter Input Impedance
BER 10
—
—
−65
100–j300
—
—
dBm
Ω
=
DISCRIMINATOR
fIN 110 MHz
Disc Gain
1X Mode
—
—
10
33
—
—
mV/˚
mV/˚
mV
mV
V
(mV/˚ of Phase Shift from Tank Circuit)
3X Mode
VOUT
Discriminator Output Peak to Peak
Voltage
1X Mode (Note 8)
3X Mode (Note 8)
Nominal (Note 10)
80
160
580
—
400
1.2
—
—
VOS
Disc. Output DC Voltage
1.82
—
DISCOUT Disc. Output Impedance
300
Ω
5
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Electrical Characteristics (Continued)
=
=
The following specifications are guaranteed for VCC 3.6V and TA 25˚C, unless otherwise specified.
Symbol
Parameter
Conditions
fIN 110 MHz
Min
Typ
Max
Unit
=
RSSI (Note 11)
RSSIout Output Voltage
=
@
PIN −80 dBm IFIN input pin
0.12
0.9
11
0.2
1.2
18
0.6
—
V
V
=
@
PIN −20 dBm IFIN input pin
=
@
Slope
PIN −90 to −30 dBm LIMIN input pin
25
mV/d
B
=
@
RSSI
Dynamic Range
PIN min −90 dBm LIMIN input pin
Centered at 1.5V
—
60
—
dB
DC COMPENSATION CIRCUIT
VOS
VI/O
RSH
Input Offset Voltage
−5
—
—
1.0
+5
—
mV
VPP
Ω
Input/Output Voltage Swing
Sample and Hold Resistor
2000
3000
3600
=
FREQUENCY SYNTHESIZER
PIN −14 to −9 dBm
fIN
Input Frequency Range
Input Signal Level
(Note 9)
500
—
—
−11.5
—
1200
—
MHz
dBm
MHz
Vpp
=
PIN
ZIN 200Ω (Note 15)
fOSC
VOSC
Oscillator Frequency Range
Oscillator Sensitivity
(Note 12)
(Note 12)
5
20
0.5
—
1.0
—
=
=
IDo-source Charge Pump Output Current
Vdo
V
P/2, Icpo LOW
−1.5
—
mA
(Note 14)
=
=
IDo-sink
Vdo
V
P/2, Icpo LOW
—
—
1.5
−6.0
6.0
—
—
—
mA
mA
mA
nA
(Note 14)
= =
V P/2, Icpo HIGH
(Note 14)
IDo-source
Vdo
=
=
IDo-sink
Vdo
V
P/2, ICPO HIGH
—
—
(Note 14)
IDo-Tri
0.5 ≤ Vdo ≤ Vp − 0.5
−1.0
1.0
=
TA 25˚C
=
=
FREQUENCY DOUBLER
fIN 945 MHz, fOUT 1.89 GHz
fOUT
Output Frequency Range
Output Signal Level
(Note 13)
1770
−10
—
—
−3
1900
—
MHz
dBm
dBm
dBm
Ω
= =
PIN −11.5 dBm, fOUT 1.89 GHz
POUT
=
=
Fundamental Output Power
Harmonic Output Power
Output Impedance
PIN −11.5 dBm, fOUT 945 MHz
−22
−13.5
−15
—
=
=
PIN −11.5 dBm, fOUT 2.835 GHz
—
−24
ZOUT
TX chain powered up
—
25+j60
15-j30
TX chain powered down
—
—
Ω
VOLTAGE REGULATOR
VO Output Voltage
DIGITAL INPUT/OUTPUT PINS
=
ILOAD 5 mA
2.55
2.75
2.90
V
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
Input Current
2.4
0.0
−10
2.4
—
—
—
—
—
—
VCC
0.8
10
V
V
<
<
IIH
GND VIN VCC
µA
V
=
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
IOH −0.5 mA
—
=
IOL 0.5 mA
0.4
V
Note 3: The mixer section is tested at 1.89 GHz, and it is guaranteed by design to operate within 1.7
— 2.0 GHz range.
Note 4: The IF section of this device is designed for optimum operating performance at 110 MHz to meet the DECT specifications.
Note 5: The matching network used on RF consists of a series 3.3 pF capacitance into the pin. The matching circuit used on MIXER
consists of a series 100
IN
OUT
nH inductance and a shunt 12 pF capacitance into the pin.
Note 6: Noise Figure measurements are made with 890 MHz BPF on the F input and matching networks on RF and MIXER
IN IN OUT
.
Note 7: The matching network used on IF consists of a series 33 nH inductance and a shunt 1.8 pF capacitance into the pin.
IN
Note 8: The discriminator is with the DC level centered at 1.5V. The unloaded Q of the tank is 40.
Note 9: The frequency synthesizer section is guaranteed by design to operate within 500 - - 1200 MHz range.
Note 10: Nominal refers to zero DC offsets programmed for the discriminator.
Note 11: It depends on loss of inter-stage filter. These specifications are for an inter-stage filter with a loss of 8 dB.
Note 12: The frequency synthesizer section is guaranteed by design to operate for OSC input frequency within 5 — 20 MHz range and minimun amplitude of 0.5
IN
V
.
pp
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6
Electrical Characteristics (Continued)
Note 13: The doubler section is tested at 1.89 GHz, and it is guaranteed by design to operate within 1.7
— 1.9 GHz range.
Note 14: See Function Register Programming Description for Icp description.
o
Note 15: Tested in a 50Ω environment.
AC Timing Characteristics
Serial Data Input Timing
TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has
an skew rate of 0.6 V / ns.
DS012815-3
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Symbol
MICROWIRE Interface
Parameter
Conditions
Min
Typ
Max
Unit
™
tCS
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
Refer to Test Condition.
Refer to Test Condition.
Refer to Test Condition.
Refer to Test Condition.
Refer to Test Condition.
Refer to Test Condition.
50
10
50
50
50
50
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
tCH
tCWH
tCWL
tES
Clock Pulse Width Low
Clock to Load Enable Set Up Time
Load Enable Pulse Width
tEW
7
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PLL Functional Description
The simplified block diagram below shows the building blocks of frequency synthesizer and all internal registers, which are 20-bit
data register, 18-bit F-latch, 12-bit N-counter, and 6-bit R-counter.
DS012815-4
The DATA stream is clocked into the data register on the rising edge of CLOCK signal, MSB first. The last two bits are the control
bits to indicate which register to be written. Upon the rising edge of the LE (Load Enable) signal, the rest of data bits is transferred
to the addressed register accordingly. The decoding scheme of the two control bits is as follows:
Control Bits
Register
C2
0
C1
0
N-Counter
R-Counter
F-Latch
1
0
X
1
=
Note: X Don’t Care Condition
Programmable Feedback Divider (N-Counter)
The N-counter consists of the 6-bit swallow counter (A-counter) and the 6-bit programmable counter (B-counter). When the con-
trol bits are “00”, data is transferred from the 20-bit shift register into two 6-bit latches. One latch sets the A-counter while the other
sets the B-counter. The serial data format is shown below.
MSB
REGISTER’S BIT MAPPING
11 10
N-COUNTER’s Divide Ratio
LSB
19
18
X
17
16
15
X
14
X
13
12
9
8
7
6
5
4
3
2
1
0
RESERVED
C2 C1
X
X
X
N12 N11 N10 N9
N8
N7
N6
N5
N4 N3 N2 N1
0
0
=
Note: X Don’t Care Condition
Swallow Counter Divide Ratio (A-Counter)
Divide Ratio, A
N6
0
N5
0
N4
0
N3
0
N2
0
N1
0
0
1
0
0
0
0
0
1
*
*
*
*
*
*
*
63
1
1
1
1
1
1
Note: Divide ratio must be from 0 to 63, and B must be ≥ A.
Programmable Counter Divide Ratio (B-Counter)
Divide Ratio, B
N12
N11
N10
N9
N8
1
N7
1
3
4
0
0
*
0
0
*
0
0
*
0
1
0
0
*
*
*
*
63
1
1
1
1
1
1
Note: Divide ratio must be from 3 to 63, and B must be ≥ A.
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8
Programmable Reference Divider (R-Counter)
If the control bits are “10”, data is transferred from the 20-bit shift register into a latch, which sets the 6-bit R-counter. The serial
data format is shown below.
MSB
REGISTER’S BIT MAPPING
LSB
19
18
X
17
X
16
X
15
X
14
13
12
11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
R-COUNTER’s Divide Ratio
C2 C1
X
X
X
X
X
X
X
X
R6 R5 R4 R3 R2 R1
1
0
=
Note: X Don’t Care Condition
Reference Counter Divide Ratio (R-Counter)
Divide Ratio, R
R6
0
R5
0
R4
0
R3
0
R2
1
R1
1
3
4
0
0
0
1
0
0
*
*
*
*
*
*
*
63
1
1
1
1
1
1
Note: Divide ratio must be from 3 to 63.
Pulse Swallow Function
fvco
:
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of binary 6-bit programmable counter (3 to 63)
Preset divide ratio of binary 6-bit swallow counter (0 ≤ A ≤ P, A ≤ B)
: Output frequency of the external reference frequency oscillator
B:
A:
fOSC
R:
Preset divide ratio of binary 6-bit programmable reference counter (3 to 63)
Preset modulus of dual modulus prescaler (32 or 64)
P:
Receiver Functional Description
The simplified block diagram below shows the mixer, IF amplifier, limiter, and discriminator. In addition, the DC compensation cir-
cuit, doubler, and voltage regulator for an external LNA stage are shown.
DS012815-5
Note: The receiver can be powered down, either by hardware through the Rx PD pin, or by software through the programming of F6 bit in F-Latch. The power
down control method is determined by the settings of F11 and F12 in F-Latch. (Refer to Function Register Programming Description section for details.)
9
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Transmitter Functional Description
The simplified block diagram below shows the doubler and voltage regulator for an external transmit gain stage.
DS012815-6
Note: The transmitter can be powered down, either by hardware through the Tx PD pin, or by software through the programming of F7 bith in F-Latch. The
power down control method is determined by the settings of F11 and F12 in F-Latch. (Refer to Function Register Programming Description section for details.)
Function Register Programming Description (F-Latch)
If the control bits are “1X”, data is transferred from the 20-bit shift register into the 18-bit F-latch. Serial data format is shown
below.
MSB
REGISTER’S BIT MAPPING
12 11 10
MODE CONTROL WORD
F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1
LSB
19
18
17
16
15
14
13
9
8
7
6
5
4
3
2
1
0
C2 C1
F18
X
1
=
Note: X Don’t Care Condition
Various modes of operation can be programmed with the function register bits F1–F18, including the phase detector polarity,
charge pump TRI-STATE® and CMOS outputs. In addition, software or hardwire power down modes can be specified with bits
F11 and F12.
Mode
Control
Bit
Setting to
Setting to
Model Control Description
Prescaler modules select.
“0” to Select
“1” to Select
F1
32/33
64/65
F2
Phase detector polarity. It is used to reverse the polarity of
the phase detector according to the VCO characteristics.
Negative VCO
Characteristics
Positive VCO
Characteristics
F3
Charge pump current gain select.
LOW Charge Pump
Current (1X Icpo).
HIGH Charge Pump
Current (4X Icpo).
F4
F5
F6
TRI-STATE charge pump output.
Normal Operation
—
Force to TRI-STATE
—
Reserved. Setting to “0” always.
Receive chain power down control. Software power down
Power Up RX Chain
Power Down RX Chain
can only be activated when both F11 and F12 are set to “0”.
F7
Transmit chain power down control. Software power down
Power Up TX Chain
Power Down TX Chain
can only be activated when both F11 and F12 are set to “0”.
=
=
OUT 0 HIGH
F8
F9
Out 0 CMOS output.
OUT 0 LOW
=
=
OUT 1 HIGH
Out 1 CMOS output. Functions only in software power down
OUT 1 LOW
mode, when both F11 and F12 are set to “0”.
=
=
F10
Out 2 CMOS output. Functions only in software power down
OUT 2 LOW
OUT 2 HIGH
mode, when both F11 and F12 are set to “0”.
F11
F12
Power down mode select.
Software
Power Down
Hardware
Power Down
Set both F11 and F12 to “0” for software power down mode.
Set both F11 and F12 to “1” for hardwire power down mode.
Other combinations are reserved for test mode.
F13
F14
Demodulator gain select
1X Gain Mode
3X Gain Mode
Demodulator DC level shift +/− level shifting polarity
Set Negative Polarity
Set Positive Polarity
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10
Function Register Programming Description (F-Latch) (Continued)
Mode
Setting to
Setting to
Control
Bit
Model Control Description
Demodulator DC level shift of 1.000V
Demodulator DC level shift of 0.500V
Demodulator DC level shift of 0.250V
Demodulator DC level shift of 0.125V
“0” to Select
“1” to Select
F15
No Shift
No Shift
No Shift
No Shift
Shift the DC Level
by 1.000V
F16
F17
F18
Shift the DC Level
by 0.500V
Shift the DC Level
by 0.250V
Shift the DC Level
by 0.125V
Power Down Mode/Control Table
=
=
= =
Hardwire Power Down Mode (F11 F12 1)
Software Power Down Mode (F11 F12 0)
Pin/Bit
Setting to “0”
means
Setting to “1”
means
Pin/Bit
Setting to “0”
means
Setting to “1”
means
F6
F7
Receiver ON
Transmitter ON
PLL ON
Receiver OFF
Transmitter OFF
PLL OFF
Rx PD
Tx PD
PLL PD
CE
Receiver OFF
Transmitter OFF
PLL ON
Receiver ON
Transmitter ON
PLL OFF
PLL PD
CE
LMX3161 OFF
LMX3161 ON
LMX3161 OFF
LMX3161 ON
11
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Typical Application
DS012815-7
DECT System Calculation for 3.6V Operation
DS012815-11
Note: Assumes 50 dB attenuation of interferer by the SAW filter and 8 dB attenuation by the LC filter. Cascaded totals in Input IP3 are calculated at the output
of the interstage filter.
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12
Loop Filter Design Consideration
DS012815-8
FIGURE 1. Conventional PLL Architecture
PASSIVE LOOP FILTER
Open loop gain H(s) G(s)
Loop Gain Equations
=
=
A linear control system model of the phase feedback for a
PLL in the locked state is shown in Figure 2. The open loop
gain is the product of the phase comparator gain (K φ ), the
VCO gain (Kvco/s), and the loop filter gain Z(s) divided by the
gain of the feedback counter modulus (N). The passive loop
filter configuration used is displayed in Figure 3, while the
complex impedance of the filter is given in Equation (2).
=
θi/θe
Kφ Z(s)K VCO/Ns
(1)
(2)
The time constants which determine the pole and zero fre-
quencies of the filter transfer function can be defined as
(3)
and
=
T2 R2 • C2
(4)
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, ω, the filter time constants T1 and T2,
and the design constants Kφ, Kvco, and N.
DS012815-9
FIGURE 2. PLL Linear Model
(5)
From Equations (3), (4) we can see that the phase term will
be dependent on the single pole and zero such that the
phase margin is determined in Equation (6).
DS012815-10
−1
=
φ (ω) tan
(ω • T 2) − tan−1 (ω • T 1) + 180˚ (6)
FIGURE 3. Passive Loop Filter
13
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Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead (7mm x 7mm) Molded Plastic Quad Flat Package, JEDEC
For Tape and Reel (2500 Units per Reel)
Order Number LMX3161VBH or LMX3161VBHX
NS Package Number VBH48A
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