LMX3305_09 [NSC]
Triple Phase Locked Loop for RF Personal Communications; 三重锁相环用于射频个人通信
| 型号： | LMX3305_09 |
| 厂家： | 
National Semiconductor |
| 描述： | Triple Phase Locked Loop for RF Personal Communications |
| 文件： | 总26页 (文件大小：586K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OBSOLETE
April 28, 2009
LMX3305
Triple Phase Locked Loop for RF Personal
Communications
General Description
Features
The LMX3305 contains three Phase Locked Loops (PLL) on
a single chip. It has a RF PLL, an IF Rx PLL and an IF Tx PLL
for CDMA applications. The RF fractional-N PLL uses a
16/17/20/21 quadruple modulus prescaler for PCS applica-
tion and a 8/9/12/13 quadruple modulus prescaler for cellular
application. Both quadruple modulus prescalers offer modulo
1 through 16 fractional compensation circuitry. The RF frac-
tional-N PLL can be programmed to operate from 800 MHz to
1400MHz in cellular band and 1200MHz to 2300 MHz in PCS
band. The IF Rx PLL and the IF Tx PLL are integer-N fre-
quency synthesizers that operate from 45 MHz to 600 MHz
with 8/9 dual modulus prescalers. Serial data is transferred
into the LMX3305 via a microwire interface (Clock, Data, &
LE).
Three PLLs integrated on a single chip
■
■
RF PLL fractional-N counter
16/17/20/21 RF quadruple modulus prescaler for PCS
application
■
8/9/12/13 RF quadruple modulus prescaler for cellular
application
■
2.7V to 3.6V option
■
■
■
Low current cmon: I= 9 mA (typ) at 3.0V
Programmle or al wer down mode: ICC = 10 µA
(typ) at 3
RF PLck feature with timeout counter
Digital lock de
■
■
■
■
Mowire Interfacwith data preset
pin SP package
The RF PLL provides a fastlock feature allowing the loop
bandwidth to be increased by 3X during initial lock-on.
The supply voltage of the LMX3305 ranges from 2.7V to 3.6V.
It typically consumes 9 mA of supply current and is packaged
in a 24-pin CSP package.
Applions
■
CDMA Cellular telephone systems
Block Diagram
10136101
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation
101361
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
Functional Block Diagram
10136102
Connection Diagram
10136103
Top View
Order Number LMX3305SLBX
See NS Package Number SLB24A
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
Pin Descriptions
Pin No.
Pin Name
RF_CPo
I/O
Description
1
O
Charge pump output for RF PLL. For connection to a loop filter for driving the input of an external
VCO.
2
3
4
RF_GND
RF_FIN
PWR RF PLL ground.
I
RF prescaler input. Small signal input from the RF Cellular or PCS VCO.
RF_VCC
PWR RF PLL power supply voltage. Input may range from 2.7V to 3.6V. Bypass capacitors should be
placed as close as possible to this pin and be connected directly to the ground plane. Tx VCC
Rx VCC = RF VCC
=
.
5
Lock_Det
O
Multiplexed output of the RF, Rx, and Tx PLL's analog or digital lock detects. The outputs from
the R, N and Fastlock counters can also be selected for test purposes. Refer to Section 2.3.4
for more detail.
6
7
N/C
No Connect.
RF_En
I
I
I
I
RF PLL enable pin. A LOW on RF En powers dowthe RF PLL and TRI-STATE®s the RF PLL
charge pump.
8
9
Rx_En
Tx_En
Clock
Rx PLL enable pin. A LOW on Rx En powerdown Rx L and TRI-STATEs the Rx PLL
charge pump.
Tx PLL enable pin. A LOW on Tx En porwn the Tx PLL and TRI-STATEs the Tx PLL
charge pump.
10
High impedance CMOS clock inpuData for the various counters is clocked on the rising edge
into the CMOS input.
11
12
Data
LE
I
I
Binary serial data input. Data entereSB t.
High impedance CMOS input. When LE s LOW, data is transferred into the shift registers.
When LE goes HIGH, datransferred from the internal registers into the appropriate latches.
13
14
Tx_FIN
I
Tx prescaler input. Small signpuom the Tx VCO.
Tx_CPo
O
Charge pump outpLL. Foconnection to a loop filter for driving the input of an external
VCO.
15
16
Tx_GND
Tx_VCC
Tx PLL ground.
PWR Tx PLL powsupply input. Input may range from 2.7V to 3.6V. Bypass capacitors should
be places close as possible to this pin and be connected directly to the ground plane. Tx
VCC = Rx F C
.
17
18
OSCIN
I
PLL rference inpuhich has a VCC/2 input threshold and can be driven from an external CMOS
ogic gate. The R counter is clocked on the falling edge of the OSCIN signal.
Rx_VCC
PWR supply voltage. Input ranges from 2.7V to 3.6V. Bypass capacitors should be
place as possible to this pin and be connected directly to the ground plane. Tx VCC
=
VCC F VCC
.
19
20
Rx_GND
Rx_CPo
L ground.
e pump output for Rx PLL. For connection to a loop filter for driving the input of an external
O.
21
22
Rx_FIN
I
Rx prescaler input. Small signal input from the Rx VCO.
RF_Sw1
O
An open drain NMOS output which can be use for bandswitching or Fastlocking the RF PLL.
(During Fastlock mode a second loop filter damping resistor can be switched in parallel with the
first to ground.) Refer to Section 2.5.3 for more detail.
23
24
RF_Sw2
VP
O
O
An open drain NMOS output which can be use for bandswitching or Fastlocking the RF PLL.
(During Fastlock mode a second loop filter damping resistor can be switched in parallel with the
first to ground.) Refer to Section 2.5.3 for more detail.
RF PLL charge pump power supply. An internal voltage doubler can be enabled in 3V
applications to allow the RF charge pump to operate over a wider tuning range.
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Lead Temp. (solder, 4 sec.) (TL)
ESD - Whole Body Model (Note 2)
+240°C
2 kV
Absolute Maximum Ratings (Notes 1, 2)
Power Supply Voltage (PLL VCC
(Note 3)
Supply Voltage (VP)
)
−0.3V to +6.5V
−0.3V to +6.5V
Recommended Operating
Conditions (Note 1)
Power Supply Voltage (PLL VCC
(Note 3)
Voltage on any Pin with
GND = 0V (VI)
)
−0.3V to VCC +0.3V
−65°C to +150°C
2.7V to 3.6V
PLL VCC to 5.5V
Storage Temperature Range (TS)
Supply Voltage (VP) (Note 3)
Operating Temperature (TA)
−30°C to +85°C
Electrical Characteristics
(VCC = VP = 3V, −30°C < TA < 85°C except as specified)
Value
Typ
Symbol
Parameter
Conditions
Unit
Max
Min
GENERAL
ICC
Power Supply Current
RF = On, Rx = On, Tx = On
9.0
10
15
mA
µA
2.7V ≤ VCC ≤ 3.6V
ICC-PWDN Power Down Current
75
2300
1400
600
25
fIN
PCS Operating Frequency
Cellular Operating Frequency
IF Operating Frequency (Rx, Tx)
Oscillator Frequency
1200
800
45
MHz
fOSC
fφ
19.68
MHz
MHz
dBm
VPP
Phase Detector Frequency
PCS/Cellular/IF Input Sensitivity
10
PfIN
−15
0.5
+0
2.7V ≤ VC3.6V
FO
PfOSC
RF PN
IF PN
Oscillator Sensitivity
RF Phase Noise
VCC
−70
−70
dBc/Hz
dBc
IF Phase Noise
Fractional Spur @ 10 kHz
Fractional Spur Harmonic
1 er (Note 4)
−50
Attenuate 6 dB/OCT
after 10 kHz
dBc
Tsw
Switching Speed
1 kHLoop Filter, 60 MHz Jump to
Wi1 kHz
4.0
ms
CHARGE PUMP
RF IDo
RF Charge Pump Source
VDo = VP/2 (Note 5)
INOM
INOM
100
−22
−22
80
22
22
%
%
Source
RF IDo Sink RF Charge Pump nt
VDo = VP/2 (Note 5)
VDo = VCC/2 (Note 5)
IF IDo
IF Charge Pump nt
120
µA
Source
IF IDo Sink IF Charge Pump Sink ent
IDo-TRI Charge Pump TRI-STATE Current
VDo = VCC/2 (Note 5)
(Note 6)
−80
−100
−120
1000
µA
pA
IDo Sink vs Charge Pump Sink vs Source Mismatch TA = 25°C (Note 7)
IDo Source
3
10
%
IDo vs VDo
IDo vs TA
Charge Pump Current vs Voltage
TA = 25°C (Note 6)
8
5
15
10
%
%
Charge Pump Current vs Temperature (Note 7)
DIGITAL INPUTS AND OUTPUTS
VIH
VIL
VOL
IIH
High-Level Input Voltage
Low-Level Input Voltage
Low-Level Output Voltage
High-Level Input Current
Low-Level Input Current
OSCIN High-Level Input Current
VCC = 2.7V to 3.6V
VCC = 2.7V to 3.6V
IOL = 2 mA
0.8 VCC
V
V
0.2 VCC
0.4
V
VIH = VCC = 3.6V
VIL = 0V, VCC = 3.6V
VIH = VCC = 3.6V
−1.0
−1.0
1.0
µA
µA
µA
IIL
1.0
IIH
100
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Value
Typ
Symbol
Parameter
Conditions
VIL = 0V, VCC = 3.6V
Unit
Min
−100
50
Max
IIL
OSCIN Low-Level Input Current
Data to Clock Setup Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
µA
ns
ns
ns
ns
ns
ns
tCS
tCH
10
tCWH
TCWL
tENSL
tENW
50
50
Clock to Load_En Setup Time
Load_En Pulse Width
50
50
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical
Characteristics.
Note 2: This device is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device should be done on ESD protected
workstations.
Note 3: PLL VCC represents RF VCC, Tx VCC and Rx VCC collectively.
Note 4: Guaranteed by design. Not tested in production.
Note 5: INOM = 100 µA, 400 µA, 700 µA or 900 µA for RF charge pump.
Note 6: For RF charge pump, 0.5 ≤ VDo ≤ VP - 0.5; for IF charge pump, 0.5 ≤ VDo ≤ VCC - 0.5.
Note 7: For RF charge pump, VDo = VP/2, for IF charge pump, VDo = VCC/2.
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Charge Pump Current Specification
Definitions
10136104
I1 = CP sink current at VDo = VP − ΔV
I2 = CP sink current at VDo = VP/2
I3 = CP sink current at VDo = ΔV
I4 = CP source current at VDo = VP − ΔV
I5 = CP source current at VDo = VP/2
I6 = CP source current at VDo = ΔV
ΔV = Voltage offset from positive and negative rails. Depn Vuning range relative to VCC and ground. Typical values are between 0.5V and 1.0V.
1. IDo vs VDo = Charge Pump Output Current magnitude variation vs age =
[½ * {|I1| − |I3|}] / [½ * {|I1| + |I3|}] * 100% and | − |I6|}] / {|I4| + |I6|}] * 100%
2. IDo-sink vs IDo-source = Charge Pump Output ource Mismatch =
[|I2| − |I5|] / [½ * {|I2| + |I5|}] * 100%
3. IDo vs TA = Charge Pump Output Current magnin vs Temperature =
[|I2 @ temp| − |I2 @ 25°C|] / |I2 @ 0% and @ temp| − |I5 @ 25°C|] / |I5 @ 25°C| * 100%
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The Rx and Tx N-counters are each a 13-bit integer divisor,
fully programmable from 56 to 8,191 over the frequency range
from 45 MHz–600 MHz. The Rx and Tx N-counters do not
include fractional compensation.
1.0 Functional Description
The LMX3305 phase-lock-loop (PLL) system configuration
consists of a high-stability crystal reference oscillator, three
frequency synthesizers, three voltage controlled oscillators
(VCO), and three passive loop filters. Each of the frequency
synthesizers includes a phase detector, a current mode
charge pump, as well as programmable reference [R] and
feedback [N] frequency dividers. The VCO frequency is es-
tablished by dividing the crystal reference signal down via the
R-counter to obtain a comparison reference frequency. This
reference signal (fR) is then presented to the input of a phase/
frequency detector and compared with the feedback signal
(fN), which is obtained by dividing the VCO frequency down
by way of the N-counter, and fractional circuitry. The phase/
frequency detector's current source output pumps charge into
the loop filter, which then converts the charge into the VCO's
control voltage. The function of phase/frequency comparator
is to adjust the voltage presented to the VCO until the feed-
back signal frequency and phase match that of the reference
signal. When the RF PLL is in a “Phase-Locked” condition,
the RF VCO frequency will be (N + F) times that of the com-
parison frequency, where N is the integer divide ratio, and F
is the fractional component. The fractional synthesis allows
the phase detector frequency to be increased while maintain-
ing the same frequency step size for channel selection. The
divider ratio N is thereby reduced giving a lower phase noise
referred to the phase detector input, and the comparison fre-
quency is increased allowing faster switching time.
1.5 FRACTIONAL COMPENSATION
The fractional compensation circuitry of the LMX3305 RF di-
vider allows the user to adjust the VCO tuning resolution in
1/2 through 1/16th increments of the phase detector compar-
ison frequency. A 4-bit denominator register (FRAC_D) se-
lects the fractional modulo base. The integer averaging is
accomplished by using a 4-bit accumulator. A variable phase
delay stage compensates for the accumulated integer phase
error, minimizes the charge pump duty cycle and reduces the
spurious levels. This technique eliminates the need for com-
pensation current injection into the loop filter. An overflow
signal generated by the accumulator is equivalent to one full
RF VCO cycle, and esults in a pulse swallow.
1.6 PHASE/FRUENY DETECTORS
The RF and IF preqncy detectors are driven from
their respee N- anunter outputs. The maximum fre-
quency aphase detetor inputs is 10 MHz unless limited
by the imcontinuous divide ratio of the multi-modulus
prescaler. The e detector output controls the charge
pu. The polarity of the pump-up or pump-down control is
pramed using RF_PD_POL, Rx_PD_POL, or
TPOL pending on whether RF or IF VCO charac-
teristire ositive or negative. The phase detector also
receives edback signal from the charge pump in order to
eliminate dead zones.
1.1 REFERENCE OSCILLATOR INPUTS
The reference oscillator frequency for the RF and IF PLLs are
provided from the external references through the OSCIN pin
OSCIN input can operate up to 25 MHz with input sen
of 0.5 VPP minimum and it drives RF, Rx and Tx R-co
OSCIN input has a VCC/2 input threshold that can be
from an external CMOS or TTL logic gate. Typically
OSCIN is connected to the output of a crystal ollator.
ARGE PUMPS
The phase detector's current source output pumps charge in-
to an external loop filter, which then converts it into the VCO's
control voltage. The charge pump steers the charge pump
output CPo to VCC (pump-up) or Ground (pump-down). When
locked, CPo is primarily in a TRI-STATE mode with small cor-
rections. The IF charge pump output current magnitudes are
nominally 100 µA. The RF charge pump output currents can
be programmed by the RF_Icpo bits at 100 µA, 400 µA, 700
µA, or 900 µA.
1.2 REFERENCE DIVIDERS (R-COUNTERS
The RF, Rx and Tx R-counters are clocked through ths-
cillator block. The maximum frequency MHz. All , Rx
and Tx R-counters are CMOS designunter is 8-
bit in length with programmable divi2 to 255.
The Rx and Tx R-counters are 10-bit with pro-
grammable divider ratio from 2 3.
1.8 VOLTAGE DOUBLER (VP)
The VP pin is normally driven from an external power supply
over a range of VCC to 5.5V to provide current for the RF
charge pump circuit. An internal voltage doubler circuit con-
nected between the VCC and VP supply pins alternately allows
VCC = 3V (±10%) users to run the RF charge pump circuit at
close to twice the VCC power supply voltage. The voltage
doubler mode is enabled by setting the V2X bit to a HIGH
level. The voltage doubler's charge pump driver originates
from the oscillator input. The device will not totally powerdown
until the V2X bit is programmed LOW. The average delivery
current of the doubler is less than the instantaneous current
demand of the RF charge pump when active and is thus not
capable of sustaining a continuous out of lock condition. A
large external capacitor connected to VP (=0.1 µF) is needed
to control power supply droop when changing frequencies.
1.3 PRESCALERS
The LMX3305 has
a 16adruple modulus
prescaler for the PCS applicat8/9/12/13 quadruple
modulus prescaler for the cellular application. The Rx and Tx
prescalers are dual modulus with 8/9 modulus ratio. Both RF/
IF prescalers' outputs drive the subsequent CMOS flip-flop
chain comprising the programmable N feedback counters.
1.4 FEEDBACK DIVIDERS (N-COUNTERS)
The RF, Rx and Tx N-counters are clocked by the output of
RF, Rx and Tx prescalers respectively. The RF N-counter is
composed of two parts: the 15 MSB bits comprise the integer
portion and the 4 LSB bits comprise the fractional portion. The
RF fractional N divider is fully programmable from 80 to 32767
over the frequency range from 1200 MHz-2300 MHz for PCS
application and 40 to 16383 over the frequency range from
800 MHz-1400 MHz for cellular application. The 4-bit frac-
tional portion of the RF counter represents the fraction's
numerator. The fraction's denominator base is determined by
the four FRAC_D register bits.
1.9 MICROWIRE INTERFACE
The programmable register set is accessed through the mi-
crowire serial interface. The interface is comprised of three
signal pins: Clock, Data, and LE. After the LE goes LOW, se-
rial data is clocked into the 32-bit shift register upon the rising
edge of Clock MSB first. The last three data bits shifted into
the shift register select one of five addresses. When LE goes
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HIGH, data is transferred from the shift registers into one of
the four register bank latches. Selecting the address <000>
presets the data in the four register banks. The synthesizer
can be programmed even in the power down (or not enabled)
state.
1.10 LOCK DETECT OUTPUTS
The open-drain Lock Detect is available in the LMX3305 to
provide a digital or analog lock detect indication for the sum
of the active PLLs. In the digital lock detect mode, an internal
digital filter produces a logic level HIGH at the lock detect
output when the error between the phase detector inputs is
less than 15 ns for five consecutive comparison cycles. The
lock detect output is LOW when the error between the phase
detector inputs is more than 30 ns for one comparison cycle.
In the analog lock detect mode, the lock detect pin becomes
active low whenever any of the active PLLs are charge pump-
ing. The Lock_Det pin can also be programmed to provide
the outputs of the R, N or fastlock timeout counters.
1.11 POWER CONTROL
Each PLL is individually power controlled by the microwire
power down bits Rx_PWDN, Tx_PWDN and RF_PWDN. Al-
ternatively, the PLLs can also be power controlled by the
Tx_En, Rx_En, and RF_En pins. The enable pins override
the power down bits except for the V2X bit. When the respec-
tive PLL's enable pin is high, the power down bits determine
the state of power control. Activation of any PLL power down
modes result in the disabling of the respective N counter and
de-biasing of its respective fIN input (to a high impedance
state). The R counter functionality also becomes disabled
when the power down bit is activated. The reference oscillator
block powers down and the OSCIN pin reverts to a hig
impedance state when all of the enable pins are LOW
of the power down bits are programmed HIGH, unle
bit is HIGH. Power down forces the respective charge
and phase comparator logic to a TRI-STATE conditi
power down counter reset function resets both nd R coun
ters of the respective PLL. Upon powering ue N ter
resumes counting in “close” alignment with the ter e
maximum error is one prescaler cycle). The microwire cool
register remains active and capable of land latcng in
data during all of the power down mo
2.0 Programming Descri
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I F _ R 0
I F _ R 1
I F _ N 0
R F _ R 0
R F _ R 1
R F _ N 0
R F _ N 1
V 2 X
R F _ R S T
R x _ R S T
R x _ P W D N
I F _ N 1
I F _ N 2
R x _ P D _ P O L
I F _ R 2
R F _ P D _ P O L
R F _ R 2
R F _ N 2
I F _ R 3
I F _ R 4
I F _ R 5
I F _ R 6
I F _ R 7
I F _ R 8
I F _ R 9
I F _ N 3
I F _ N 4
I F _ N 5
I F _ N 6
I F _ N 7
I F _ N 8
I F _ N 9
N 1 0
I F _
I F _ N 1 2
1 3
I F _ N 1 4
R F _ R 3
R F _ P W R D F N _ N 3
R F _ N 4
R F _ I c p o
R F _ R 4 P C S
R F _ R 5 F b p s
R F _ R 6
R F _ N 5
R F _ N 6
F _ R
R F _ N 7
R 8
R F _ N 8
R F _ R 9
R F _ N 9
F S T S W 1
T S W 2
F S T M 1
I F _ R 1 0
R F _ R 1 0
R F _ R 1 1
R F _ R 1 2
R F _ R 1 3
R F _ R 1 4
R F _ N 1 0
I F _ R 1 1
I F _ R 1 2
I F _ R 1 3
I F _
R F _ N 1 1
R F _ N 1 2
R F _ N 1 3
R F _ N 1 4
F S T M 2
P W D N
I F _ R 1 5
R 1
I F _ 7
I F _ N 1 5
I F _ N 1 6
I F _ N 1 7
I F _ N 1 8
I F _ N 1 9
I F _ N 2 0
I F _ N 2 1
I F _ N 2 2
I F _ N 2 3
I F _ N 2 4
I F _ N 2 5
I F _ N 2 6
I F _ N 2 7
I F _ N 2 8
R F _ R 1 5
R F _ R 1 6
R F _ R 1 7
R F _ R 1 8
R F _ R 1 9
R F _ R 2 0
R F _ R 2 1
R F _ R 2 2
R F _ R 2 3
R F _ R 2 4
R F _ R 2 5
R F _ R 2 6
R F _ R 2 7
R F _ R 2 8
R F _ N 1 5
R F _ N 1 6
R F _ N 1 7
R F _ N 1 8
R F _ N 1 9
R F _ N 2 0
R F _ N 2 1
R F _ N 2 2
R F _ N 2 3
R F _ N 2 4
R F _ N 2 5
R F _ N 2 6
R F _ N 2 7
R F _ N 2 8
S T
O L
F _ R 1 8
I F _ R 1 9
I F _ R 2 0
I F _ R 2 1
I F _ R 2 2
I F _ R 2 3
I F _ R 2 4
I F _ R 2 5
I F _ R 2 6
I F _ R 2 7
I F _ R 2 8
P
I F _ R
I F _ N
R F _ R
R F _ N
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
I F _ R 0
I F _ N 0 V 2 X
R F _ R 0
R F _ R 1
R F _ N 0
R F _ N 1
R x _ P W D N
R x _ R S T I F _ R 1
I F _ N 1
I F _ N 2
R F _ R S T
P O L
R x _ P D _ I F _ R 2
R F _ P D _ P O R L F _ R 2
R F _ R 3
R F _ N 2
R F _ P W D N
I F _ R 3
I F _ R 4
I F _ R 5
I F _ R 6
I F _ R 7
I F _ R 8
I F _ R 9
I F _ N 3
I F _ N 4
I F _ N 5
I F _ N 6
I F _ N 7
I F _ N
I F _ N 9
I F _ N 1 0
I F
_ N 1 2
I F _ N 1 3
I F _ N 1 4
R F _ N 3
R F _ N 4
R F _ N 5
R F _ N 6
R F _ N 7
R F _ N 8
R F _ N 9
R F _ N 1 0
R F _ N 1 1
R F _ N 1 2
R F _ N 1 3
R F _ N 1 4
R F _ I c p o
P C S
R F _ R 4
F _ R 5
6
R F _ R 7
R F _ R 8
R F _ R 9
R F _ R 1 0
R F _ R 1 1
R F _ R 1 2
R F _ R 1 3
R F _ R 1 4
F b p s
F S T S W 1
F S T S W 2
F S T M 1
I F _ R 1 0
I F _ R 1 1
I F _ R 1 2
I F _ R 3
I F 1 4
F S T M 2
P W D N
_ R 1 5
I F 1 7
I F _ N 1 5
I F _ N 1 6
I F _ N 1 7
R F _ R 1 5
R F _ R 1 6
R F _ R 1 7
R F _ N 1 5
R F _ N 1 6
R F _ N 1 7
I F _ R 1 8
I F _ R 1 9
I F _ N 1 8
I F _ N 1 9
R F _ R 1 8
R F _ R 1 9
R F _ N 1 8
R F _ N 1 9
I F _ R 2 0
I F _ R 2 1
I F _ R 2 2
I F _ R 2 3
I F _ R 2 4
I F _ R 2 5
I F _ N 2 0
I F _ N 2 1
I F _ N 2 2
I F _ N 2 3
I F _ N 2 4
I F _ N 2 5
R F _ R 2 0
R F _ R 2 1
R F _ R 2 2
R F _ R 2 3
R F _ R 2 4
R F _ R 2 5
R F _ N 2 0
R F _ N 2 1
R F _ N 2 2
R F _ N 2 3
R F _ N 2 4
R F _ N 2 5
I F _ R 2 6
I F _ R 2 7
I F _ R 2 8
I F _ N 2 6
I F _ N 2 7
I F _ N 2 8
R F _ R 2 6
R F _ R 2 7
R F _ R 2 8
R F _ N 2 6
R F _ N 2 7
R F _ N 2 8
P
I F _ R
I F _ N
R F _ R
R F _ N
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
I F _ R 0
R x _ R S T I F _ R 1
R x _ P D I _ F P _ R O 2 L
I F _ R 3
I F _ R 4
I F _ R 5
I F _ R 6
I F _ R 7
I F _ R 8
I F _ R 9
I F _ R 1 0
I F _ R 1 1
I F _ R 1 2
I F _ R 3
I F 1
_ R 1 5
I F R 1 7
_ I P F O _ R L 1 8
I F _ R 1 9
I F _ R 2 0
I F _ R 2 1
I F _ R 2 2
I F _ R 2 3
I F _ R 2 4
I F _ R 2 5
I F _ R 2 6
I F _ R 2 7
I F _ R 2 8
I F _ R
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
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2.3.1 10-Bit IF Programming Reference Divider Ratio (Tx
R Counter, Rx R Counter)
Divide Ratio
Tx_R_CNTR [9:0] or Rx_R_CNTR [9:0]
2
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
1
•
3
•
1023
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio for both Tx and Rx R counters are from 2 to 1023.
2.3.2 Tx_PD_POL (IF_R[18])
2.3.4 LD (IF_R[16]-[13])
This bit sets the polarity of the Tx phase detector. It is set to
one when Tx VCO characteristics are positive. When Tx VCO
frequency decreases with increasing control voltage,
Tx_PD_POL should be set to zero.
The LD pin is a multiplexed output. When in lock detect mode,
LD does ANDing function on the active PLLs. The RF frac-
tional test mode is only intended for factory testing.
2.3.3 Tx_RST (IF_R[17])
This bit will reset the Tx R and N counters when it is set to
one. For normal operation, Tx_RST should be set to zero.
Lock Detect Output Truth Tab
LD [3:0]
LD Pin Functn
Output Format
Open Drain
Open Drain
CMOS
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
Digital Lock Detect
Analog Lock Dete
Rx R Counter
1
0
1
0
1
0
1
0
1
Rx N Counter
CMOS
Tx R Counr
CMOS
Tx N Counter
CMOS
RF R er
CMOS
RF
CMOS
Reout Counter
RF Test Mode
CMOS
Analog
Lock Detect Digital Filter
Once in lock (Lock Det = HIGH), the RC delay is changed to
approximately 30 ns. To exit the locked state (Lock Det =
LOW), the phase error must become greater than the 30 ns
RC delay. When the PLL is in the powerdown mode, Lock Det
is forced HIGH. A flow chart of the digital filter is shown below.
The Lock Detect Digital Filter compares the nce e-
tween the phase of the inputs of the phase detector to C
generated delay of approximately 15 nnter the cked
state (Lock Det = HIGH) the phase less than
the 15 ns RC delay for five consece cycles.
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
10136105
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Typical Lock Detect Timing
10136106
2.3.5 Rx_PD_POL (IF_R[2])
2.3.6 Rx_R(IF_R
This bit sets the polarity of the Rx phase detector. It is set to
one when Rx VCO characteristics are positive. When Rx VCO
frequency decreases with increasing control voltage,
Rx_PD_POL should set to zero.
This bit weset the Rx and N counters when it is set to
one. Fooroperation, Rx_RST should be set to zero.
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14
101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
I F _ N 0
I F _ N 1
R x _ P W D N
I F _ N 2
I F _ N 3
I F _ N 4
I F _ N 5
I F _ N 6
I F _ N 7
I F _ N 8
I F _ N 9
I F _ N 1 0
I F _ N 1 1
I F _ N 1 2
I F _ N 1 3
I F _ N 1 4
T x _ P W D I F N _ N
I F _ N 1 6
1
I F _ N 1 9
F _ N 2 0
I F _ N 2 1
I F _ N 2 2
I F _ N 2 3
I F _ N 2 4
I F _ N 2 5
I F _ N 2 6
I F _ N 2 7
I F _ N 2 8
I F _ N
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
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2.4.1 3-Bit IF Swallow Counter Divide Ratio (Tx A Counter,
Rx A Counter)
Divide Ratio
Tx_NA_CNTR [2:0] or Rx_NA_CNTR [2:0]
0
1
•
0
0
•
0
0
•
0
1
•
7
1
1
1
Divide ratio is from 0 to 7
Tx_NB_CNTR ≥ Tx_NA_CNTR and Rx_NB_CNTR ≥ Rx_NA_CNTR
2.4.2 10-Bit IF Programmable Counter Divide Ratio (Tx B
Counter, Rx B Counter)
Divide
Ratio
Tx_NB_CNTR [9:0] or Rx_NB_CNTR [9:0]
3
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
1
•
1
0
•
1
0
•
4
•
1023
1
1
1
1
1
1
1
1
1
1
Divide ratio is from 3 to 1023 (Divide ratios less than 3 are prohibited)
Tx_NB_CNTR ≥ Tx_NA_CNTR and Rx_NB_CNTR ≥ Rx_NA_CNTR
N = PB + A
B = N div P
A = N mod P
2.4.3 Tx_PWDN (IF_N[15])
2.4.4 DN (IF_N[1])
This bit will asynchronously powerdown the Tx PLL when set
to one. For normal operation, it should be set to zero.
This bit will asynchronously powerdown the Rx PLL when set
to oneor normal operation, it should be set to zero.
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
R F _ R 0
R F _ R 1
R F _ R 2
V 2 X
R F _ R S T
R F _ P D _ P O L
R F _ R 3
R F _ R 4
R F _ R 5
R F _ R 6
R F _ R 7
R F _ R 8
R F _ R 9
R F _ I c p o
F S T S W 1
F S T S W 2
F S T M 1
R F _ R 1 0
R F _ R 1 1
R F _ R 1 2
R F _ R 1 3
R F _ R 1 4
R F _ 5
R F _ R
R 7
R F _ R 1 9
R F _ R 2 0
R F _ R 2 1
R F _ R 2 2
R F _ R 2 3
R F _ R 2 4
R F _ R 2 5
R F _ R 2 6
R F _ R 2 7
R F _ R 2 8
F S T M 2
R F _ R
17
101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
www.national.com
2.5.1 8-Bit RF Programming Reference Divider Ratio (RF
R Counter)
Divide Ratio
RF_R_CNTR [7:0]
2
3
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
1
•
•
255
1
1
1
1
1
1
1
1
Divide ratio for RF R counter is from 2 to 255.
2.5.2 FSTL_CNTR (RF_R[20]-[14])
detector cycles the fastlock mode remains in HIGH gain is the
binary FSTL_CNTR value loaded multiplied by eight.)
The Fastlock Timeout Counter is a 10 bit counter wherein only
the seven MSB bits are programmable. (The number of phase
Phase Detect
Cycles
FSTL_CNTR [6:0]
24
32
0
0
•
0
0
•
0
0
•
0
0
•
0
1
1
0
•
1
0
•
•
1008
1016
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2.5.3 FSTM (RF_R[13]-[12]) and FSTSW (RF_R[11]-[10])
Whbit FSTM2 and/or FSTM1 is set HIGH, the RF fastlock
iablAs a new frequency is loaded, RF_Sw2 pin and/
ow1 pigoes to a LOW state to switch in the damping
resisthRF CPo is set to a higher gain, and fastlock
timeout cter starts counting. Once the timeout counter fin-
ishes counting, the PLL returns to its normal operation (the
cpo n is forced to 100 µA irrespective of RF_Icpo bits).
Fastlock enables the designer to achieve both fast frequency
transitions and good phase noise performance by dynami-
cally changing the PLL loop bandwidth. The Fastlock modes
allow wide band PLL fast locking with seamless transition to
a low phase noise narrow band PLL. Consistent gain and
phase margins are maintained by simultaneously changing
charge pump current magnitude and loop filter damping
sistor. In the LMX3305, the RF fastlock can achieve su
tial improvement in lock time by increasing the charg
current by 4X, 7X or 9X, which causes a 2X, 2.6X or
crease in the loop bandwidth respectively. The dampin
sistors are connected to FSTSW pins.
bit FSTM2 and/or FSTM1 is set LOW, pins RF_Sw2
and/or RF_Sw1 can be toggled HIGH or LOW to drive other
devices. RF_Sw2 and/or RF_Sw1 can also be set LOW to
switch in different damping resistors to change the loop filter
performance. FSTSW bits control the output states of the
RF_Sw2 and RF_Sw1 pins.
RF_R[12] FSTM1
RF_R[10] FSTSW
RF_Sw1 Output Function
0
0
1
0
RSw1 pin reflects RF_SwBit “0” logic state
RF_Sw1 pin reflects RF_SwBit “1” logic state
RF_Sw1 pin LOW while T.O. counter is active
RF_R[13] FSTM2
RSTSW
RF_Sw2 Output Function
RF_Sw2 pin reflects RF_SwBit “0” logic state
RF_Sw2 pin reflects RF_SwBit “1” logic state
RF_Sw2 pin LOW while T.O. counter is active
0
0
1
2.5.4 FRAC_CAL (RF_R[9]-[5])
tional spur. Improvements can be made by selecting the bits
to be one greater or less than the denominator value. For ex-
ample, in the 1/16 fractional mode, these four bits can be
programmed to 15 or 17. In normal operation, these bits
should be set to zero.
These five bits allow the users to optimize the fractional cir-
cuitry, therefore reducing the fractional reference spurs. The
MSB bit, RF_R[9], activates the other four calibration bits
RF_R[8]-[5]. These four bits can be adjusted to improve frac-
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
2.5.5 RF_Icpo (RF_R[4]-[3])
These two bits set the charge pump gain of the RF PLL. The
user is able to set the charge pump gain during the acquisition
phase of the fastlock mode to 4X, 7X or 9X.
Charge Pump Gain
100 µA
RF_R[4]
RF_R[3]
0
0
1
1
0
1
0
1
400 µA
700 µA
900 µA
2.5.6 RF_PD_POL (RF_R[2])
2.5.8 V2X (RF_R[0])
This bit sets the polarity of the RF phase detector. It is set to
one when RF VCO characteristics are positive. When RF
VCO frequency decreases with increasing control voltage,
RF_PD_POL should be set to zero.
V2X when set high enables the voltage doubler for the RF
charge pump supply.
2.5.7 RF_RST (RF_R[1])
This bit will reset the RF R and N counters when it is set to
one. For normal operation, RF_RST should be set to zero.
19
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
R F _ N 0
R F _ N 1
R F _ N 2
R F _ N 3
R F _ P W D N
R F _ N 4
R F _ N 5
R F _ N 6
R F _ N 7
R F _ N 8
R F _ N 9
P C S
F b p s
R F _ N 1 0
R F _ N 1 1
R F _ N 1 2
R F _ N 1 3
R F _ N 1 4
R F 1 5
R F _ N 6
_ 7
R F _ N 1 9
R F _ N 2 0
R F _ N 2 1
R F _ N 2 2
R F _ N 2 3
R F _ N 2 4
R F _ N 2 5
R F _ N 2 6
R F _ N 2 7
R F _ N 2 8
R F _ N
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20
101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
2.6.1 RF_N_CNTR (RF_N[28]-[14])
N = PC + 4B + A
The RF N counter value is determined by three counter values
that work in conjunction with four prescalers. This quadruple
modulus prescaler architecture allows lower minimum con-
tinuous divide ratios than are possible with a dual modulus
prescaler architecture. For the determination of the A, B, and
C counter values, the fundamental relationships are shown
below.
C ≥ max {A,B} + 2
The A, B, and C values can be determined as follows:
C = N div P
B = (N - CP) div 4
A = (N - CP) mod 4
N REGISTER FOR THE CELLULAR (8/9/12/13) PRESCALER OPERATING IN FRACTIONAL MODE
Divide
Ratio
1-23
RF_N_CNTR [14:0]
C Word
B Word
A Word
Divide Ratios Less than 24 are impossible since it is required that C ≥ 3
24-39
40
Some of these N values are Legal Divide Ratios, some are not
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
1
1
.
0
0
1
1
.
0
0
0
0
0
0
.
0
0
1
.
41
0
.
…
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N REGISTER FOR THE PCS (16/17/20/21) PRESCALER ONG IN FRACTIONAL MODE
RF_N_CNTR 4:0]
Divide
Ratio
1-47
C Word
B Word
A Word
Divide Ratios Less than 48 are impossnce s required that C ≥ 3
48-79
80
Some of these N values are Legal Divitios, some are not
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
0
0
.
1
1
.
0
0
.
1
1
.
0
0
0
1
0
0
.
0
0
.
0
1
.
81
…
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
2.6.2 FRAC_N (RF_N[13]-[10])
These four bits, the fractional accumulator mods numer
tor, set the fractional numerator values in the ction.
Modulus Numerator
FRAC_N [3:0]
0
1
0
0
0
0
0
•
0
0
1
•
0
1
0
•
2
•
14
15
1
1
1
1
0
1
21
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
2.6.3 FRAC_D (RF_N[9]-[6])
These four bits, the fractional accumulator modulus denomi-
nator, set the fractional denominator from 1/2 to 1/16 resolu-
tion.
Modulus Denominator
FRAC_D [3:0]
1-8
Not Allowed
9
10-14
15
1
•
1
0
0
•
1
0
0
•
1
0
1
•
1
0
16
MODULUS NUMERATOR (FRAC_N) AND DENOMINATOR (FRAC_D) PROGRAMMING
Fractional
Numerator
(FRAC_N)
RF_N[13]-
[10]
Fractional Denominator, (FRAC_D)
RF_N[9]-[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 111101 1110 1111 0000
0=0000
1=0001
Functions like an integer-N PLL as fractl componens set to 0.
*
*
*
*
*
*
*
111/11 1/12 1/13 1/14 1/15 1/16
(8/16) (5/15) (4/16) (3/15) (2/12) (2/14) (2/16)
*
*
*
*
*
*
2=0010
3=0011
4=0100
5=0101
6=0110
7=0111
2/9 2/10 2/11 2/12 2/13 2/14 2/15 2/16
(10/1 (8/16) (6/15) (4/12) (4/14) (4/
5)
*
*
*
*
*
3/9 3/10 3/11 3/12 3/13 3/14 3/15 3/16
4/9 4/10 4/11 4/12 4/13 4/14 4/15 4/16
5/9 5/10 5/11 5/12 5/13 5/14 5/15 5/16
6/9 6/10 6/11 6/12 6/13 6/14 6/15 6/16
7/9 7/10 7/11 7/12 7/13 7/14 7/15 7/16
(12/1 (9/15) (6/12) (6/16/16)
6)
*
*
*
(12/1 (8//16)
5)
*
*
(10/1 (10/1 (10/1
4)
*
6)
*
(12/1 (12/1
4)
6)
*
(14/1
6)
FRAC_D en 1 to 8 are not allowed.
8=1000
9=1001
10=1010
8/9 8/10 8/11 8/12 8/13 8/14 8/15 8/16
9/10 9/11 9/12 9/13 9/14 9/15 9/16
10/1 10/1 10/1 10/1 10/1 10/16
1
2
3
4
5
11=1011
12=1100
13=1101
14=1110
15=1111
11/1 11/1 11/1 11/1 11/16
2
3
4
5
12/1 12/1 12/1 12/16
3
4
5
13/1 13/1 13/16
4
5
14/1 14/16
5
15/16
Remark: The *(FRAC_N / FRAC_D) denotes that the fraction number can be represented by (FRAC_N / FRAC_D) as indicated in the parenthesis. For example,
1/2 can be represented by 8/16.
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22
101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
2.6.4 FBPS (RF_N[5])
bit is set to one, the RF PLL will operate in the PCS mode and
when it is set to zero, the cellular mode.
This bit when set to one will bypass the delay line calculation
used in the fractional circuitry. This will improve the phase
noise while sacrificing performance on reference spurs.
When the bit is set to zero, the delay line circuit is in effect to
reduce reference spur.
2.6.6 RF_PWDN (RF_N[3])
This bit will asynchronously powerdown the RF PLL when set
to one. For normal operation, it should be set to zero.
2.6.7 Test (RF_N[2]-[0])
2.6.5 PCS (RF_N[4])
These bits are the internal factory testing only. They should
be set to zero for normal operation.
This bit will determine whether the RF PLL should operate in
PCS frequency range or cellular frequency range. When the
23
101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
www.national.com
SERIAL DATA INPUT TIMING
10136107
Notes: Parenthesis data indicates programmable reference
Test Conditions: e Serial Data Input Timing is tested us-
divider data.
ing a symmetricavem around VCC/2. The test waveform
has an edge rat6 V/with amplitudes of 1.84V @
VCC = 2.3V d 4.4V V= 5.5V.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
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24
101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
Physical Dimensions inches (millimeters) unless otherwise noted
LMe Drawing
OrdeX3305SLBX
NS Pber SLB24A
25
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:25
Notes
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101361 Version 3 Revision 5 Print Date/Time: 2009/04/28 20:23:26
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