LP38693SDX-ADJ/NOPB [NSC]
IC VREG 1.25 V-9 V ADJUSTABLE POSITIVE LDO REGULATOR, PDSO6, LLP-6, Adjustable Positive Single Output LDO Regulator;
| 型号： | LP38693SDX-ADJ/NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | IC VREG 1.25 V-9 V ADJUSTABLE POSITIVE LDO REGULATOR, PDSO6, LLP-6, Adjustable Positive Single Output LDO Regulator 光电二极管 输出元件 调节器 |
| 文件： | 总14页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 25, 2009
LP38691-ADJ
LP38693-ADJ
500mA Low Dropout CMOS Linear Regulators with
Adjustable Output
Stable with Ceramic Output Capacitors
General Description
Features
The LP38691/3-ADJ low dropout CMOS linear regulators pro-
vide 2.0% precision reference voltage, extremely low dropout
voltage (250mV @ 500mA load current, VOUT = 5V) and ex-
cellent AC performance utilizing ultra low ESR ceramic output
capacitors.
Output voltage range of 1.25V - 9V
■
■
■
■
■
■
■
■
2.0% adjust pin voltage accuracy (25°C)
Low dropout voltage: 250mV @ 500mA (typ, 5V out)
Wide input voltage range (2.7V to 10V)
Precision (trimmed) bandgap reference
The low thermal resistance of the LLP and SOT-223 pack-
ages allow the full operating current to be used even in high
ambient temperature environments.
Guaranteed specs for -40°C to +125°C
1µA off-state quiescent current
The use of a PMOS power transistor means that no DC base
drive current is required to bias it allowing ground pin current
to remain below 100 µA regardless of load current, input volt-
age, or operating temperature.
Thermal overload protection
Foldback current limiting
■
■
■
SOT-223 and 6-Lead LLP packages
Enable pin (LP38693-ADJ)
Dropout Voltage: 250 mV (typ) @ 500mA (typ. 5V out).
Ground Pin Current: 55 µA (typ) at full load.
Adjust Pin Voltage: 2.0% (25°C) accuracy.
Applications
Hard Disk Drives
■
■
■
■
Notebook Computers
Battery Powered Devices
Portable Instrumentation
Typical Application Circuits
20126801
20126802
VOUT = VADJ x (1 + R1/R2)
Note: *Minimum value required for stability.
© 2009 National Semiconductor Corporation
201268
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Connection Diagrams
20126803
SOT-223, Top View
LP38693MP-ADJ
20126804
20126805
6-Lead LLP, Bottom View
LP38691SD-ADJ
6-Lead LLP, Bottom View
LP38693SD-ADJ
Pin Descriptions
Pin
Description
VIN
This is the input supply voltage to the regulator. For LLP package devices, both VIN pins must be tied
together for full current operation (250mA maximum per pin).
GND
Circuit ground for the regulator. This is connected to the die through the lead frame, and also functions
as the heat sink when the large ground pad is soldered down to a copper plane.
VOUT
VEN
Regulated output voltage.
The enable pin allows the part to be turned ON and OFF by pulling this pin high or low.
ADJ
The adjust pin is used to set the regulated output voltage by connecting it to the external resistors
R1 and R2 (see Typical Application Circuit).
Ordering Information
Order Number
LP38691SD-ADJ
LP38693SD-ADJ
LP38693MP-ADJ
LP38691SDX-ADJ
LP38693SDX-ADJ
LP38693MPX-ADJ
Package Marking
Package Type
6-Lead LLP
6-Lead LLP
SOT-223
Package Drawing
SDE06A
Supplied As
L117B
L127B
LJUB
1000 Units Tape and Reel
1000 Units Tape and Reel
1000 Units Tape and Reel
4500 Units Tape and Reel
4500 Units Tape and Reel
2000 Units Tape and Reel
SDE06A
MP05A
L117B
L127B
LJUB
6-Lead LLP
6-Lead LLP
SOT-223
SDE06A
SDE06A
MP05A
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2
V(max) All pins (with respect to GND)
IOUT
-0.3V to 12V
Internally Limited
−40°C to +150°C
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Junction Temperature
Operating Ratings
Storage Temperature Range
Lead Temp. (Soldering, 5 seconds)
ESD Rating (Note 3)
−65°C to +150°C
260°C
2 kV
Internally Limited
VIN Supply Voltage
2.7V to 10V
Operating Junction
Temperature Range
−40°C to +125°C
Power Dissipation (Note 2)
Electrical Characteristics Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over
the full operating temperature range. Unless otherwise specified: VIN = VOUT + 1V, CIN = COUT = 10 µF, ILOAD = 10mA. Min/Max
limits are guaranteed through testing, statistical correlation, or design.
Symbol
Parameter
Conditions
Min
Typ (Note 4) Max
Units
VIN = 2.7V
1.225
1.25
1.275
VADJ
ADJ Pin Voltage
V
3.2V ≤ VIN ≤ 10V
100 µA < IL < 0.5A
1.200
1.25
1.300
Output Voltage Line Regulation
(Note 6)
ΔVO/ΔVIN
ΔVO/ΔIL
VO + 0.5V ≤ VIN ≤ 10V
0.03
1.8
0.1
5
%/V
%/A
IL = 25mA
Output Voltage Load Regulation
(Note 7)
1 mA < IL < 0.5A
VIN = VO + 1V
(VO = 2.5V)
IL = 0.1A
80
430
145
725
IL = 0.5A
(VO = 3.3V)
IL = 0.1A
65
330
110
550
VIN - VO
Dropout Voltage (Note 8)
mV
IL = 0.5A
(VO = 5V)
IL = 0.1A
IL = 0.5A
45
250
100
450
IQ
Quiescent Current
55
100
1
VIN ≤ 10V, IL = 100 µA - 0.5A
VEN ≤ 0.4V,
(LP38693-ADJ Only)
0.001
µA
IL(MIN)
IFB
Minimum Load Current
Foldback Current Limit
100
VIN - VO ≤ 4V
VIN - VO > 5V
VIN - VO < 4V
350
850
mA
dB
PSRR
TSD
Ripple Rejection
VIN = VO + 2V(DC), with 1V(p-p) /
120Hz Ripple
55
160
10
Thermal Shutdown Activation
(Junction Temp)
°C
nA
TSD (HYST)
IADJ
Thermal Shutdown Hysteresis
(Junction Temp)
ADJ Input Leakage Current
VADJ = 0 - 1.5V
VIN = 10V
-100
0.01
100
3
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Symbol
Parameter
Output Noise
Conditions
Min
Typ (Note 4) Max
Units
µV/
en
BW = 10Hz to 10kHz
VO = 3.3V
0.7
VO (LEAK)
VEN
Output Leakage Current
VO = VO(NOM) + 1V @ VIN = 10V
Output = OFF
0.5
2
µA
Enable Voltage (LP38693-ADJ
Only)
0.4
Output = ON, VIN = 4V
Output = ON, VIN = 6V
Output = ON, VIN = 10V
VEN = 0V or 10V, VIN = 10V
1.8
3.0
4.0
-1
V
IEN
Enable Pin Leakage (LP38693-
ADJ Only)
0.001
1
µA
Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not
apply when operating the device outside of its rated operating conditions.
Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used).
The junction-to-ambient thermal resistance (θJ-A) for the SOT-223 is approximately 125 °C/W for a PC board mounting with the device soldered down to minimum
copper area (less than 0.1 square inch). If one square inch of copper is used as a heat dissipator for the SOT-223, the θJ-A drops to approximately 70 °C/W. The
θ
J-A values for the LLP package are also dependent on trace area, copper thickness, and the number of thermal vias used (refer to application note AN-1187). If
power disspation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown.
Note 3: ESD is tested using the human body model which is a 100pF capacitor discharged through a 1.5k resistor into each pin.
Note 4: Typical numbers represent the most likely parametric norm for 25°C operation.
Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.
Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1mA to full load.
Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100mV of nominal value.
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4
Block Diagrams
20126806
FIGURE 1. LP38691-ADJ Functional Diagram (LLP)
20126807
FIGURE 2. LP38693-ADJ Functional Diagram (SOT-223, LLP)
5
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Typical Performance Characteristics Unless otherwise specified: TJ = 25°C, CIN = COUT = 10 µF, enable
pin is tied to VIN (LP38693-ADJ only), VO = 1.25V, VIN = 2.7V, IL = 10mA.
Noise vs Frequency
Noise vs Frequency
Ripple Rejection
Noise vs Frequency
Ripple Rejection
Ripple Rejection
20126836
20126835
20126817
20126837
20126819
20126821
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6
VREF vs Temperature
Line Transient Response
20126823
20126830
Line Transient Response
Line Transient Response
20126824
20126825
Line Transient Response
Line Transient Response
20126826
20126827
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Line Transient Response
Load Transient Response
Enable Voltage vs Temperature
Line Regulation vs Temperature
20126828
20126842
Load Transient Response
20126844
20126853
Load Regulation vs Temperature
20126854
20126855
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8
VOUT vs VIN , VOUT = 1.25V
VOUT vs VIN , VOUT = 1.80V
VOUT vs VEN, ON (LP38693 Only)
MIN VIN vs IOUT
20126858
20126860
20126862
20126859
VOUT vs VIN, Power-Up
20126861
VOUT vs VEN, OFF (LP38693 Only)
20126856
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Dropout Voltage vs IOUT
(VOUT = 1.8V)
20126857
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10
Capacitor Characteristics
CERAMIC
Application Hints
EXTERNAL CAPACITORS
For values of capacitance in the 10 to 100 µF range, ceramics
are usually larger and more costly than tantalums but give
superior AC performance for bypassing high frequency noise
because of very low ESR (typically less than 10 mΩ). How-
ever, some dielectric types do not have good capacitance
characteristics as a function of voltage and temperature.
Like any low-dropout regulator, external capacitors are re-
quired to assure stability. These capacitors must be correctly
selected for proper performance.
INPUT CAPACITOR: An input capacitor of at least 1µF is re-
quired (ceramic recommended). The capacitor must be lo-
cated not more than one centimeter from the input pin and
returned to a clean analog ground.
Z5U and Y5V dielectric ceramics have capacitance that drops
severely with applied voltage. A typical Z5U or Y5V capacitor
can lose 60% of its rated capacitance with half of the rated
voltage applied to it. The Z5U and Y5V also exhibit a severe
temperature effect, losing more than 50% of nominal capac-
itance at high and low limits of the temperature range.
OUTPUT CAPACITOR: An output capacitor is required for
loop stability. It must be located less than 1 centimeter from
the device and connected directly to the output and ground
pins using traces which have no other currents flowing
through them.
X7R and X5R dielectric ceramic capacitors are strongly rec-
ommended if ceramics are used, as they typically maintain a
capacitance range within ±20% of nominal over full operating
ratings of temperature and voltage. Of course, they are typi-
cally larger and more costly than Z5U/Y5U types for a given
voltage and capacitance.
The minimum amount of output capacitance that can be used
for stable operation is 1µF. Ceramic capacitors are recom-
mended (the LP38691/3-ADJ was designed for use with ultra
low ESR capacitors). The LP38691/3-ADJ is stable with any
output capacitor ESR between zero and 100 Ohms.
SETTING THE OUTPUT VOLTAGE: The output voltage is
set using the external resistors R1 and R2 (see Typical Ap-
plication Circuit). The output voltage will be given by the
equation:
TANTALUM
Solid Tantalum capacitors have good temperature stability: a
high quality Tantalum will typically show a capacitance value
that varies less than 10-15% across the full temperature
range of -40°C to 125°C. ESR will vary only about 2X going
from the high to low temperature limits.
VOUT = VADJ x (1 + ( R1 / R2 ) )
Because the part has a minimum load current requirement of
100 µA, it is recommended that R2 always be 12k Ohms or
less to provide adequate loading. Even if a minimum load is
always provided by other means, it is not recommended that
very high value resistors be used for R1 and R2 because it
can make the ADJ node susceptible to noise pickup. A max-
imum Ohmic value of 100k is recommended for R2 to prevent
this from occurring.
The increasing ESR at lower temperatures can cause oscil-
lations when marginal quality capacitors are used (if the ESR
of the capacitor is near the upper limit of the stability range at
room temperature).
PCB LAYOUT
Good PC layout practices must be used or instability can be
induced because of ground loops and voltage drops. The in-
put and output capacitors must be directly connected to the
input, output, and ground pins of the regulator using traces
which do not have other currents flowing in them (Kelvin con-
nect).
ENABLE PIN (LP38693-ADJ only): The LP38693–ADJ has
an Enable pin (EN) which allows an external control signal to
turn the regulator output On and Off. The Enable On/Off
threshold has no hysteresis. The voltage signal must rise and
fall cleanly, and promptly, through the ON and OFF voltage
thresholds. The Enable pin has no internal pull-up or pull-
down to establish a default condition and, as a result, this pin
must be terminated either actively or passively. If the Enable
pin is driven from a source that actively pulls high and low, the
drive voltage should not be allowed to go below ground po-
tential or higher than VIN. If the application does not require
the Enable function, the pin should be connected directly to
the VIN pin.
The best way to do this is to lay out CIN and COUT near the
device with short traces to the VIN, VOUT, and ground pins. The
regulator ground pin should be connected to the external cir-
cuit ground so that the regulator and its capacitors have a
"single point ground".
It should be noted that stability problems have been seen in
applications where "vias" to an internal ground plane were
used at the ground points of the IC and the input and output
capacitors. This was caused by varying ground potentials at
these nodes resulting from current flowing through the ground
plane. Using a single point ground technique for the regulator
and it’s capacitors fixed the problem. Since high current flows
through the traces going into VIN and coming from VOUT
Kelvin connect the capacitor leads to these pins so there is
no voltage drop in series with the input and output capacitors.
FOLDBACK CURRENT LIMITING: Foldback current limiting
is built into the LP38691/3-ADJ which reduces the amount of
output current the part can deliver as the output voltage is
reduced. The amount of load current is dependent on the dif-
ferential voltage between VIN and VOUT. Typically, when this
differential voltage exceeds 5V, the load current will limit at
about 350 mA. When the VIN -VOUT differential is reduced be-
low 4V, load current is limited to about 850 mA.
,
RFI/EMI SUSCEPTIBILITY
SELECTING A CAPACITOR
RFI (radio frequency interference) and EMI (electromagnetic
interference) can degrade any integrated circuit’s perfor-
mance because of the small dimensions of the geometries
inside the device. In applications where circuit sources are
present which generate signals with significant high frequen-
cy energy content (> 1 MHz), care must be taken to ensure
that this does not affect the IC regulator.
It is important to note that capacitance tolerance and variation
with temperature must be taken into consideration when se-
lecting a capacitor so that the minimum required amount of
capacitance is provided over the full operating temperature
range.
If RFI/EMI noise is present on the input side of the regulator
(such as applications where the input source comes from the
11
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output of a switching regulator), good ceramic bypass capac-
itors must be used at the input pin of the IC.
power and ground planes do not radiate directly into adjacent
layers which carry analog power and ground.
If a load is connected to the IC output which switches at high
speed (such as a clock), the high-frequency current pulses
required by the load must be supplied by the capacitors on
the IC output. Since the bandwidth of the regulator loop is less
than 100 kHz, the control circuitry cannot respond to load
changes above that frequency. This means the effective out-
put impedance of the IC at frequencies above 100 kHz is
determined only by the output capacitor(s).
OUTPUT NOISE
Noise is specified in two ways- Spot Noise or Output
Noise density is the RMS sum of all noise sources, measured
at the regulator output, at a specific frequency (measured with
a 1Hz bandwidth). This type of noise is usually plotted on a
curve as a function of frequency. Total Output Noise or
Broad-Band Noise is the RMS sum of spot noise over a
specified bandwidth, usually several decades of frequencies.
In applications where the load is switching at high speed, the
output of the IC may need RF isolation from the load. It is
recommended that some inductance be placed between the
output capacitor and the load, and good RF bypass capacitors
be placed directly across the load.
Attention should be paid to the units of measurement. Spot
noise is measured in units µV/root-Hz or nV/root-Hz and total
output noise is measured in µV(rms)
The primary source of noise in low-dropout regulators is the
internal reference. Noise can be reduced in two ways: by in-
creasing the transistor area or by increasing the current drawn
by the internal reference. Increasing the area will decrease
the chance of fitting the die into a smaller package. Increasing
the current drawn by the internal reference increases the total
supply current (ground pin current).
PCB layout is also critical in high noise environments, since
RFI/EMI is easily radiated directly into PC traces. Noisy cir-
cuitry should be isolated from "clean" circuits where possible,
and grounded through a separate path. At MHz frequencies,
ground planes begin to look inductive and RFI/ EMI can cause
ground bounce across the ground plane. In multi-layer PCB
applications, care should be taken in layout so that noisy
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12
Physical Dimensions inches (millimeters) unless otherwise noted
6-lead, LLP Package
NS Package Number SDE06A
SOT-223 Package
NS Package Number MP05A
13
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