LP3905SDX-A3 [NSC]
Power Management Unit For Low Power Handheld Applications; 电源管理单元用于低功率手持式应用
| 型号： | LP3905SDX-A3 |
| 厂家： | 
National Semiconductor |
| 描述： | Power Management Unit For Low Power Handheld Applications |
| 文件： | 总15页 (文件大小：681K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2006
LP3905
Power Management Unit For Low Power Handheld
Applications
General Description
Key Specifications
Buck Regulators
LP3905 is
a multi-functional Power Management Unit,
optimized for low power handheld applications. This device
integrates two 600mA DC/DC buck regulators and two
150mA linear regulators. Fixed and adjustable buck output
versions are available. The LP3905 additionally features two
enable pins for the device output control and is offered in an
LLP package.
n Fixed and adjustable voltage options, range 1.0V to
3.3V *
n Up to 90% Efficiency
n Auto-switching PFM-PWM mode and fixed PWM mode
n 2MHz PWM fixed switching frequency (Typ)
n 600mA output current
n
4% output voltage accuracy over temp.
Features
n Internal softstart
n 2.2µH inductor, 10µF Input and 10µF output Caps
n Two buck regulators for powering high current processor
functions or peripheral devices
Linear Regulators
n Output options in the range 1.5V to 3.3V *
n 13.5µVrms output voltage noise
n Two linear regulators for powering internal processor
functions and I/Os
n One enable pin for Buck1 and Linear Regulators 1 & 2
n Separate enable pin for Buck2
@
n PSRR - 70dB 1kHz
n
3% output voltage accuracy over full line and load
regulation
n Thermal and current overload protection
n Small 14–Pin LLP package (4mm x 4mm x 0.8mm)
n 0mA to 150mA output current
n Cin = 1.0µF, Cout = 0.47µF for 100mA O/P
Cin = 1.0µF, Cout = 1.0µF for 150mA O/P
80mV Dropout voltage
Applications
n Baseband Processors
n Peripheral Processor (Video, Audio)
n I/O Power
* Fixed output voltage devices can be customized to fit
system requirements. Please contact National Semiconduc-
tor Sales Office.
n FPGA Power
Typical Application Circuit
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FIGURE 1. Typical Application Circuit – 14 Pin LLP Package
© 2006 National Semiconductor Corporation
DS201529
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Block Diagram
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FIGURE 2. Simplified Functional Diagram
Connection Diagram
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FIGURE 3. 14 Pin LLP Package
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2
Connection Diagram (Continued)
Pin Descriptions
Pin #
Name
Description
1
EN2
Enable Pin for Buck2
Ground Pin
2
TGND
LDO2
VIN2
3
LDO2 Output Pin
4
Input Power Terminal to LDO1 & 2
LDO1 Output Pin
5
LDO1
GND
6
LDO1 & 2 Ground Pin
Enable Pin for Buck1 and LDO1&2
Buck1 Feedback Pin
Buck1 Ground Pin
7
EN1
8
FB1
9
GND_B1
SW1
10
11
12
13
14
DAP
Buck1 Switch Pin
VIN1
Input Power Terminal to Buck1 & 2
Buck2 Switch Pin
SW2
GND_B2
FB2
Buck2 Ground Pin
Buck2 Feedback Pin
Die Attach Pad (DAP)
SGND
Package Marking Diagram
20152905
•
•
•
The physical placement of the package marking will vary from part to part.
Date Code - UZXYTT format. ’U’ - Wafer fab code; ’Z’ - assembly site code; ’XY’ 2 digit date code; ’TT’ die run code
See National Web site for more info - http://www.national.com/quality/marking_conventions.html
FIGURE 4. LP3905 14 Pin LLP Package Marking
NS package number SDA14B
Ordering Information
Buck 1 [V] Buck 2 [V] LDO 1 [V] LDO 2 [V]
Order Number
LP3905SD-00
Package Marking
Supplied As
1.2
1.875
2.8
2.8
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
1000 units, Tape-and-Reel
3905-00
LP3905SDX-00
LP3905SD-30
1.2 Fixed
PWM
1.875
Fixed
PWM
ADJ
2.8
2.8
3905-30
3905-A3
LP3905SDX-30
4500 units, Tape-and-Reel
ADJ
3.0
2.8
LP3905SD-A3
1000 units, Tape-and-Reel
4500 units, Tape-and-Reel
LP3905SDX-A3
3
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Absolute Maximum Ratings (Note 1)
Operating Ratings (Notes 1, 2)
VIN1 (Buck1&2 Input
Voltage),VIN2 (LDO1&2 Input
Voltage) (Note 7)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
3V to 5.5V
VIN1,VIN
2
−0.2V to 6.0V
(GND−0.2V) to
(VIN + 0.2V) to 6.0V
(max)
Recommended Load Current
(Buck)
0mA to 600 mA
FB1, FB2, EN1,EN2
Recommended Load Current
(LDO)
0mA to 100mA with
0.47uF O/P cap
0mA to 150mA with
1.0uF O/P cap
Continuous Power Dissipation
(Note 3)
Internally Limited
Junction Temperature (TJ-MAX
Storage Temperature Range
Maximum Lead Temperature
(Soldering, 10 sec.)
)
+150˚C
−65˚C to +150˚C
260˚C
Junction Temperature (TJ)
Range
−40˚C to +125˚C
Ambient Temperature (TA)
Range (Note 5)
−40˚C to +85˚C
ESD Rating (Note 4)
Human Body Model:
2.5kV
Thermal Properties
Junction-to-Ambient
37.3oC/W
Thermal Resistance (θJA
)
SDA14B package(Note 6)
General Electrical Characteristics (Notes 2, 8, 9)
Limits in standard typeface are for TJ = 25˚C. Limits in boldface type apply over the full junction temperature range (−40˚C ≤
TJ ≤ +125˚C). Unless otherwise noted, specifications apply to the LP3905 Typical Application Circuit (Figure. 1)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Login Input Thresholds
VIN
IQ
Input Voltage Range
3
5.5
V
Shutdown Supply Current
All Circuits OFF except for POR and
UVLO
6.5
10.0
µA
No load Supply Current (Note 15) LDO1 & 2 and Buck1 & 2 on
( PWM only versions ) LDO1 & 2
140
7
250
10.0
mA
and Buck1 & 2 on
VIH
VIL
IEN
Logic High Input
Logic Low Input
VIN = 3.0V to 5.5V
VIN = 3.0V to 5.5V
EN1/EN2 = 5.5V and VIN= 5.5V
EN1/EN2 = 0V and VIN= 5.5V
VIN Rising
1.2
2.1
V
V
0.4
8.5
0.1
3.1
Enable (EN1,2) Input Current
(Note 14)
5
0.001
2.7
µA
µA
V
VUVLO-R
Battery Under Voltage Lock-Out
TSHUTDOWN Thermal Shutdown (Note 15)
Temperature
160
20
˚C
Hysteresis
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4
General Electrical Characteristics (Notes 2, 8, 9) (Continued)
Buck Regulator Electrical Characteristics
Buck 1 & 2 have a current rating of Imax= 600mA. Unless otherwise specified, limits are set with VIN = VEN1/2 = 3.8V, VOUT
-
(Buck1)= Vnom1 , VOUT(Buck2)= Vnom2 and CIN= COUT=10µF. Limits in standard typeface are for TJ = 25˚C. Limits in boldface
type apply over the full junction temperature range (−40˚C ≤ TJ ≤ +125˚C). Unless otherwise noted, specifications apply to the
LP3905 Typical Application Circuit (Figure. 1) (Notes 2, 8)
Symbol
VFB
Parameter
Feedback Voltage
Condition
Min
-4
Typ
Max
+4
Units
%
(Note 16)
VOUT
Line Regulation
3.0V ≤ VIN ≤ 5.5V
0.045
%/V
IO = 1mA
Load Regulation
100 mA ≤ IO ≤ 600mA
VIN= VGS= 3.6V
0.002
380
250
1000
2
%/mA
mΩ
mΩ
mA
RDSON (P)
RDSON (N)
ILIM
Pin-Pin Resistance for PFET
Pin-Pin Resistance for NFET
Switch Peak Current Limit
Internal Oscillator Frequency
Efficiency
500
400
VIN= VGS= 3.6V (Note 15)
Open Loop
650
1220
FOSC
PWM Mode
MHz
%
η
IOUT = 5mA, PFM mode (Note 15)
IOUT = 300mA, PWM mode (Note 15)
88
90
LDO Regulator Electrical Characteristics
The linear regulators have a current rating of Imax= 150mA with COUT = 1.0µF. A 100mA rating applies with COUT = 0.47µF.
Unless otherwise specified, limits are set with VIN = 3.8V, VEN1/2 = 3.8V, CIN = 1µF, COUT = 0.47µF, IOUT = 1.0mA. Limits in
standard typeface are for TJ = 25˚C. Limits in boldface type apply over the full junction temperature range (−40˚C ≤ TJ ≤
+125˚C). Unless otherwise noted, specifications apply to the LP3905 Typical Application Circuit (Figure. 1)(Notes 2, 8)
Symbol
∆VOUT
Parameter
Output Voltage Tolerance
Line Regulation Error
Conditions
Over Full Line and Load Regulation
VIN = 3.8V to 5.5V,
IOUT = 1mA
Min
−3
Typ
Max
3
Units
%
0.05
%/V
Load Regulation Error
Load Current
IOUT = 1 mA to 100mA
(Notes 11, 15)
0.003
%/mA
mA
ILOAD
VDO
0
Dropout Voltage
IOUT = 100mA
80
150
500
mV
ISC
Short Circuit Current Limit
Maximum Output Current
Power Supply Rejection Ratio
(Note 15)
(Note 13)
300
mA
IOUT
PSRR
COUT = 1.0µF
150
mA
f = 100Hz, IOUT = 100mA
f = 1kHz, IOUT = 100mA
f = 10kHz, IOUT = 100mA
f = 50kHz, IOUT = 100mA
f = 100kHz, IOUT = 100mA
90
90
60
35
25
dB
en
Output Noise Voltage
(Note 15)
BW = 10Hz to
IOUT = 1mA
µVRMS
13.5
15.5
100kHz, VIN = 4.2V
Buck1 Turned ON
with ILOAD= 0mA,
Buck2 Turned OFF
IOUT = 100mA
5
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General Electrical Characteristics (Notes 2, 8, 9) (Continued)
LDO Regulator Electrical Characteristics (Continued)
The linear regulators have a current rating of Imax= 150mA with COUT = 1.0µF. A 100mA rating applies with COUT = 0.47µF.
Unless otherwise specified, limits are set with VIN = 3.8V, VEN1/2 = 3.8V, CIN = 1µF, COUT = 0.47µF, IOUT = 1.0mA. Limits in
standard typeface are for TJ = 25˚C. Limits in boldface type apply over the full junction temperature range (−40˚C ≤ TJ ≤
+125˚C). Unless otherwise noted, specifications apply to the LP3905 Typical Application Circuit (Figure. 1)(Notes 2, 8)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Transient Characteristics (Note 15)
∆VOUT
Line Transient (Note 15)
Load Transient (Note 15)
VIN = (VOUT(NOM) + 1.0V) to
(VOUT(NOM) + 1.6V) in 10µs, IOUT = 1
mA
6
mV
VIN = (VOUT(NOM) + 1.6V) to
(VOUT(NOM) + 1.0V) in 10µs, IOUT
1mA
=
6
IOUT = 1mA to 100mA in 10µs
IOUT = 100mA to 1mA in 10µs
IOUT = 1mA to 150mA in 10µs
COUT = 1.0µF
-70
30
mV
mV
-100
IOUT = 150mA to 1mA in 10µs
COUT = 1.0µF
35
20
Overshoot on Startup
(Note 15)
Electrical Characteristics Notes
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage.
Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. MIL-STD-883 3015.7
Note 5: In Applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have to be derated.
Maximum ambient temperature (T
) is dependent on the maximum operating junction temperature (T
), the maximum power dissipation of the device in
A-MAX
J-MAX
the application (P
) and the junction to ambient thermal resistance of the package (θ ) in the application, as given by the following equation:T
= T
−
D-MAX
JA
A-MAX
J-MAX
(θ x P
).
JA
D-MAX
Note 6: Junction to ambient thermal resistance is highly dependent on board layout, PCB material environmental conditions and applications. In applications where
high power dissipation exists, special care must be given to thermal dissipation issues in board design. The use of thermal vias under the pad may be required. For
more on these topics, please refer to the Application Note: AN-1187: Leadless leadframe Package (LLP).
Note 7: V
and V
should be tied together at all times for proper Power Up
IN2
IN1
Note 8: Min and Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 9: The parameters in the electrical characteristic table are tested at V = 3.8V unless otherwise specified. For performance over the input voltage range refer
IN
to datasheet curves.
Note 10: C , C
: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
OUT
IN
Note 11: The device maintains a stable, regulated output voltage without a load.
Note 12: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value.
Note 13: Short Circuit Current is measured with V
pulled to 0v and V worst case = 5,5V.
IN
OUT
Note 14: There is a 1 MΩ resistor between EN1,EN2 and ground on the device.
Note 15: This specification is guaranteed by design.
Note 16: For the adjustable version, feedback resistor values should be chosen for the divider network to ensure that at the desired output voltage the feedback
pin is at 0.5V. See Buck Converter Applications Information.
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Typical Application Circuit
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FIGURE 5. Typical Application Circuit For Adjustable Device
enabled, EN1 will turn on Buck1, LDO1 and LDO2. EN2 can
independently be used to enable Buck2. Figure 6 illustrates
the power UP/DOWN timing sequence of the LP3905 blocks
for VEN≥ VIH (min) (enable) and VEN≤VIL (max) (disable).
Both linear regulators have active pulldowns when the out-
puts are disabled.
Functional Description
POWER UP/DOWN PROCEDURE
The LP3905 Bucks and LDOs are powered UP/DOWN with
2 control pins, EN1 and EN2. In order for the enable pins to
operate, VIN1 and VIN2 should be set to a voltage level higher
than VUVLO_R (specified in electrical characteristic). Once
20152904
EN1 and EN2 can be controlled fully independently.
LDOs will be turned on only after Buck1 is powered up. LDOs are powered on simultaneously.
In case EN1 and EN2 are enabled at the same time, power up of Buck2 is delayed by 50µs in order to minimize the inrush current
from the battery.
When EN1 and EN2 are disabled, the relevant output voltages are turned off.
FIGURE 6. LP3905 Power UP/DOWN Timing Sequence
7
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Functional Description (Continued)
DC/DC BUCK REGULATORS
consumption and a longer battery life. Shutdown mode turns
off the device, offering the lowest current consumption . A
fixed mode device is also available which is fixed in PWM
mode for both low and high load currents.
The LP3905 Buck regulators are high efficiency step down
DC-DC switching converters used for delivering a constant
voltage from either a single Li-Ion or three cell NiMH/NiCd
battery to portable devices such as cell phones and PDAs.
Using a voltage mode architecture with synchronous rectifi-
cation, the Buck Regulators have the ability to deliver up to
600 mA depending on the input voltage, output voltage,
ambient temperature and the inductor chosen.
An adjustable voltage version is also avalable for which the
output voltage can be selected by using two external resis-
tors at each of the two buck outputs.
Additional features include soft-start, under voltage protec-
tion, current overload protection, and thermal shutdown pro-
tection.
There are three modes of operation depending on the cur-
rent required - PWM, PFM, and shutdown. The standard
device operates in PWM mode at load currents of approxi-
mately 80 mA or higher, having voltage tolerance of 4%
with 90% efficiency or better. Lighter load currents cause the
device to automatically switch into PFM for reduced current
The part uses an internal reference voltage of 0.5V. It is
recommended to keep the part in shutdown until the input
voltage is 3V or higher.
BUCK CONVERTER BLOCK DIAGRAM
20152918
FIGURE 7. Simplified Functional Diagram
CIRCUIT OPERATION
draws current from ground through the NFET to the output
filter capacitor and load, which ramps the inductor current
down with a slope of - VOUT/L.
The LP3905 Buck regulators operate as follows. During the
first portion of each switching cycle, the control block in the
LP3905 turns on the internal PFET switch. This allows cur-
rent to flow from the input through the inductor to the output
filter capacitor and load. The inductor limits the current to a
ramp with a slope of (VIN–VOUT)/L, by storing energy in a
magnetic field.
The output filter stores charge when the inductor current is
high, and releases it when inductor current is low, smoothing
the voltage across the load.
The output voltage is regulated by modulating the PFET
switch on time to control the average current sent to the load.
The effect is identical to sending a duty-cycle modulated
rectangular wave formed by the switch and synchronous
During the second portion of each cycle, the controller turns
the PFET switch off, blocking current flow from the input, and
then turns the NFET synchronous rectifier on. The inductor
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8
PFM OPERATION
Functional Description (Continued)
rectifier at the SW pin to a low-pass filter formed by the
inductor and output filter capacitor. The output voltage is
equal to the average voltage at the SW pin.
At very light loads, the converters enters PFM mode and
operate with reduced switching frequency and supply current
to maintain high efficiency.
The Bucks will automatically transition into PFM mode when
either of two conditions occurs for a duration of 32 or more
clock cycles:
PWM OPERATION
During PWM operation the converters operate as a voltage-
mode controllers with input voltage feed forward. This allows
the converters to achieve good load and line regulation. The
DC gain of the power stage is proportional to the input
voltage. To eliminate this dependence, feed forward in-
versely proportional to the input voltage is introduced.
A. The inductor current becomes discontinuous.
B. The peak PMOS switch current drops below the IMODE
level,
While in PWM (Pulse Width Modulation) mode, the output
voltage is regulated by switching at a constant frequency
and then modulating the energy per cycle to control power to
the load. At the beginning of each clock cycle the PFET
switch is turned on and the inductor current ramps up until
the comparator trips and the control logic turns off the switch.
The current limit comparator can also turn off the switch in
case the current limit of the PFET is exceeded. Then the
NFET switch is turned on and the inductor current ramps
down. The next cycle is initiated by the clock turning off the
NFET and turning on the PFET.
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20152922
FIGURE 9. Typical PFM Operation
During PFM operation, the converter positions the output
voltage slightly higher than the nominal output voltage during
PWM operation, allowing additional headroom for voltage
drop during a load transient from light to heavy load. The
PFM comparators sense the output voltage via the feedback
pin and control the switching of the output FETs such that the
output voltage ramps between 0.6% and 1.7% above the
nominal PWM output voltage. If the output voltage is below
the ‘high’ PFM comparator threshold, the PMOS power
switch is turned on. It remains on until the output voltage
reaches the ‘high’ PFM threshold or the peak current ex-
ceeds the IPFM level set for PFM mode. The typical peak
current in PFM mode is:
20152923
~
~
FIGURE 8. Typical PWM Operation
Internal Synchronous Rectification
While in PWM mode, if enabled, the Bucks use an internal
NFET as a synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rec-
tification provides a significant improvement in efficiency
whenever the output voltage is relatively low compared to
the voltage drop across an ordinary rectifier diode.
20152957
Once the PMOS power switch is turned off, the NMOS
power switch is turned on until the inductor current ramps to
zero. When the NMOS zero-current condition is detected,
the NMOS power switch is turned off. If the output voltage is
below the ‘high’ PFM comparator threshold ), the PMOS
switch is again turned on and the cycle is repeated until the
output reaches the desired level. Once the output reaches
the ‘high’ PFM threshold, the NMOS switch is turned on
briefly to ramp the inductor current to zero and then both
output switches are turned off and the part enters an ex-
tremely low power mode. Quiescent supply current during
this ‘sleep’ mode is 16µA (typ), which allows the part to
achieve high efficiencies under extremely light load condi-
tions. When the output drops below the ‘low’ PFM threshold,
Current Limiting
A current limit feature allows the LP3905 Bucks to protect
Internal and external components during overload condi-
tions. PWM mode implements current limiting using an inter-
nal comparator that trips at 1000 mA (typ). If the output is
shorted to ground the device enters a timed current limit
mode where the NFET is turned on for a longer duration until
the inductor current falls below a low threshold, ensuring
inductor current has more time to decay, thereby preventing
runaway.
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PWM mode. When VIN =2.8V the part transitions from PWM
Functional Description (Continued)
the cycle repeats to restore the output voltage (average
voltage in pfm mode) to ∼1.15% above the nominal PWM
output voltage.
~
to PFM mode at 35mA output current and from PFM to
~
PWM mode at 85mA , when VIN=3.6V, PWM to PFM tran-
~
sition happens at 50mA and PFM to PWM transition hap-
~
pens at 100mA, when VIN =4.5V, PWM to PFM transition
~
happens at 65mA and PFM to PWM transition happens at
If the load current should increase during PFM mode caus-
ing the output voltage to fall below the ‘low2’ PFM threshold,
the part will automatically transition into fixed-frequency
~
115mA.
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FIGURE 10. Operation in PFM Mode and Transfer to PWM Mode
SOFT START
high after Vin reaches 3V. Soft start is implemented by
increasing switch current limit in steps of 70mA, 140mA,
280mA and 1000mA (typ. switch current limit). The start-up
time thereby depends on the output capacitor and load
current demanded at start-up. Typical start-up times with
22µF output capacitor and 300mA load current is 400µs and
with 1mA load current its 275µs.
The LP3905 Buck Converters have a soft-start circuit that
limits in-rush current during start-up. Additionally, in case
EN1 and EN2 are enabled at the same time, a typical 500µs
delay between Buck1 and Buck2 Power Up prevents any
further Inrush current from the battery.
During start-up the switch current limit is increased in steps.
Soft start is activated only if EN goes from logic low to logic
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10
around 200kΩ to keep the current drawn through the resistor
network well below the 16µA quiescent current level (PFM
mode) but large enough that it is not susceptible to noise. If
R2 is 200kΩ and with VFB at 0.5V, the current through the
resistor feedback network will be 2.5µA.
Application Information
DC/DC CONVERTORS
Adjustable Buck - Output Voltage Selection
The formula for output voltage selection is
The buck converter output voltage of the adjustable version
device can be set via the selection of the external feedback
resistor network forming the output feedback between the
output voltage side of the Inductor and the FB pin and the FB
Pin and GND.
VOUT - output voltage (Volts)
VFB - feedback voltage (0.5V)
R1FB - feedback resistor from VOUT to FB
R2FB - feedback resistor from FB to GND
For any out voltage greater than or equal to 1.0V a zero
should be added around 45 kHz by the addition of a capaci-
tor C1. The formula for the calculation of C1 is:
20152958
Adjustable Buck Converter Components
For recommended component values see Table 1
VOUT will be adjusted to make the voltage at FB equal to
0.5V. The resistor from FB to ground (RFB2) should be
TABLE 1. Buck Component Configurations for Various Output Voltage Values
VOUT (V)
1.0
RFB1 (kΩ)
200
RFB2 (kΩ)
200
C1 (pF)
18
C2 (pF)
none
none
none
none
none
none
none
33
L (µH)
2.2
COUT (µF)
10
10
10
10
10
10
10
10
10
1.2
280
200
12
2.2
1.4
360
200
10
2.2
1.5
360
180
10
2.2
1.6
442
200
8.2
6.8
8.2
8.2
6.8
2.2
1.85
2.5
540
200
2.2
402
100
2.2
2.8
464
100
2.2
3.3
562
100
33
2.2
Buck Inductor Selection
•
•
•
IOUTMAX: maximum load current (600mA)
VIN: maximum input voltage in application
There are two main considerations when choosing an induc-
tor; the inductor should not saturate, and the inductor current
ripple is small enough to achieve the desired output voltage
ripple. Different saturation current rating specs are followed
by different manufacturers so attention must be given to
details. Saturation current ratings are typically specified at
25˚C so ratings at max ambient temperature of application
should be requested from manufacturer.
L : min inductor value including worst case tolerances
(30% drop can be considered for method 1)
•
•
f : minimum switching frequency (1.6Mhz)
VOUT: output voltage
Method 2:
A more conservative and recommended approach is to
choose an inductor that has saturation current rating greater
than the max current limit of 1220mA.
There are two methods to choose the inductor saturation
current rating.
A 2.2µH inductor with a saturation current rating of at least
1250mA is recommended for most applications.The induc-
tor’s resistance should be less than 0.3Ω for good efficiency.
For low-cost applications, an unshielded bobbin inductor
could be considered. For noise critical applications, a toroi-
dal or shielded-bobbin inductor should be used. A good
practice is to lay out the board with overlapping footprints of
both types for design flexibility. This allows substitution of a
low-noise shielded inductor, in the event that noise from
low-cost bobbin models is unacceptable.
Method 1:
The saturation current is greater than the sum of the maxi-
mum load current and the worst case average to peak
inductor current. This can be written as
•
IRIPPLE: average to peak inductor current
11
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Note that the output voltage ripple is dependent on the
inductor current ripple and the equivalent series resistance
of the output capacitor (RESR).
Application Information (Continued)
Buck DC/DC Convertor Input Capacitor Selection
A ceramic input capacitor of 10µF, 6.3V is sufficient for most
applications. Place the input capacitor as close as possible
to the VIN pin of the device. A larger value may be used for
improved input voltage filtering. Use X7R or X5R types, do
not use Y5V. DC bias characteristics of ceramic capacitors
must be considered when selecting case sizes like 0805 and
0603. The input filter capacitor supplies current to the PFET
switch of the LP3905 in the first half of each cycle and
reduces voltage ripple imposed on the input power source. A
ceramic capacitor’s low ESR provides the best noise filtering
of the input voltage spikes due to this rapidly changing
current. Select a capacitor with sufficient ripple current rat-
ing. The input current ripple can be calculated as:
The RESR is frequency dependent (as well as temperature
dependent); make sure the value used for calculations is at
the switching frequency of the part.
LINEAR REGULATORS
Capacitor Selection
The LP3955 is designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer: for
capacitance values in the range of 0.47µF to 10µF range,
ceramic capacitors are the smallest, least expensive and
have the lowest ESR values (which makes them best for
eliminating high frequency noise). The ESR of a typical
1µFceramic capacitor is in the range of 20mW to 40mW,
which easily meets the ESR requirement for stability by the
LP3955. For both input and output capacitors careful inter-
pretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change
greatly dependant on the conditions of operation and capaci-
tor type.
In particular the output capacitor selection should take ac-
count of all the capacitor parameters to ensure that the
specification is met within the application. Capacitance value
can vary with DC bias conditions as well as temperature and
frequency of operation. Capacitor values will also show
some decrease over time due to aging. The capacitor pa-
rameters are also dependant on the particular case size with
smaller sizes giving poorer performance figures in general.
As an example Figure 11 shows a typical graph showing a
comparison of capacitor case sizes in a Capacitance vs. DC
Bias plot. As shown in the graph, as a result of the DC Bias
condition the capacitance value may drop below the mini-
mum capacitance value given in the recommended capacitor
table (0.7µF in this case). Note that the graph shows the
capacitance out of spec for the 0402 case size capacitor at
higher bias voltages. It is therefore recommended that the
capacitor manufacturers’ specifications for the nominal value
capacitor are consulted for all conditions as some capacitor
sizes (e.g. 0402) may not be suitable in the actual applica-
tion.
DC/DC CONVERTOR OUTPUT CAPACITOR SELECTION
Use a 10µF, 6.3V ceramic capacitor. Use X7R or X5R types,
do not use Y5V. DC bias characteristics of ceramic capaci-
tors must be considered when selecting case sizes like 0805
and 0603. DC bias characteristics vary from manufacturer to
manufacturer and dc bias curves should be requested from
them as part of the capacitor selection process.
The output filter capacitor smoothes out current flow from the
inductor to the load, helps maintain a steady output voltage
during transient load changes and reduces output voltage
ripple. These capacitors must be selected with sufficient
capacitance and sufficiently low ESR to perform these func-
tions.
The output voltage ripple is caused by the charging and
discharging of the output capacitor and also due to its RESR
and can be calculated as:
Voltage peak-to-peak ripple due to capacitance can be ex-
pressed as follows
Voltage peak-to-peak ripple due to ESR can be expressed
as follows
VPP-ESR = (2 * IRIPPLE) * RESR
Because these two components are out of phase the rms
value can be used to get an approximate value of peak-to-
peak ripple.
Voltage peak-to-peak ripple, root mean squared can be ex-
pressed as follows
20152906
FIGURE 11. Capacitor Performance (DC Bias)
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12
be guaranteed by the manufacturer to have a surge current
rating sufficient for the application. There are no require-
ments for the ESR (Equivalent Series Resistance) on the
input capacitor, but tolerance and temperature coefficient
must be considered when selecting the capacitor to ensure
the capacitance will remain 1.0µF 30% over the entire
operating voltage and temperature range.
Application Information (Continued)
The ceramic capacitor’s capacitance can vary with tempera-
ture. The capacitor type X7R, which operates over a tem-
perature range of -55˚C to +125˚C, will only vary the capaci-
tance to within 15%. The capacitor type X5R has a similar
tolerance over a reduced temperature range of -55˚C to
+85˚C.
LDO Output Capacitor
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
1µF to 4.7µF range.
The LP3905 LDOs are designed specifically to work with
very small ceramic output capacitors. A ceramic capacitor
(dielectric types X5R or X7R) in the 0.47µF to 10µF range,
and with ESR between 5mΩ to 500mΩ, is suitable in the
application circuit. For this device the output capacitor
should be connected between the LDO1 and LDO2 pins and
a good ground connection and should be mounted within
1cm of the device.
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum
capacitor with an ESR value within the stable range, it would
have to be larger in capacitance (which means bigger and
more costly ) than a ceramic capacitor with the same ESR
value. It should also be noted that the ESR of a typical
tantalum will increase about 2:1 as the temperature goes
from 25˚C down to -40˚C, so some guard band must be
allowed.
The output capacitor must meet the requirement for the
minimum value of capacitance and also have an ESR value
that is within the range 5mΩ to 500mΩ for stability.
No-Load Stability
The LP3905 LDOs will remain stable and in regulation with
no external load.
LDO Input Capacitor
An input capacitor is required for stability. The input capacitor
should be at least equal to or greater than the output capaci-
tor. It is recommended that a 1µF capacitor be connected
between VIN2 input pin and ground (this capacitance value
may be increased without limit).
Enable Control
A 1MΩ pulldown resistor ties the EN1/2 input to ground, this
ensures that the device will remain off when the enable pin is
left open circuit. To ensure proper operation, the signal
source used to drive the EN1/2 input must be able to swing
above and below the specified turn-on/off voltage thresholds
listed in the Electrical Characteristics section under VIL and
VIH. EN1 can be used to turn ON Buck1 and LDO1/2. In this
case Buck1 will be turned on first. Once Buck1 is powered
up, after a typical 150µs delay LDO1/2 will be turned on
concurrently.
This capacitor must be located a distance of not more than
1cm from the input pin and returned to a clean analogue
ground. Any good quality ceramic, tantalum, or film capacitor
may be used at the input.
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge current when connected to a low-
impedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
13
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reduces ground-plane noise by preventing the switching
currents from circulating through the ground plane. It
also reduces ground bounce at the LP3905 by giving it a
low-impedance ground connection.
LP3905 Board Layout
Considerations
PC board layout is an important part of DC-DC converter
design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to
EMI, ground bounce, and resistive voltage loss in the traces.
These can send erroneous signals to the DC-DC converter
IC, resulting in poor regulation or instability.
4. Use wide traces between the power components and for
power connections to the DC-DC converter circuit. This
reduces voltage errors caused by resistive losses across
the traces.
5. Route noise sensitive traces, such as the voltage feed-
back path, away from noisy traces between the power
components. The voltage feedback trace must remain
close to the Buck circuits and should be direct but should
be routed opposite to noisy components. This reduces
EMI radiated onto the DC-DC converter’s own voltage
feedback trace. A good approach is to route the feed-
back trace on another layer and to have a ground plane
between the top layer and layer on which the feedback
trace is routed. In the same manner for the adjustable
part it is desired to have the feedback dividers on the
bottom layer.
Good layout for the LP3905 can be implemented by follow-
ing a few simple design rules.
1.
Place the Buck inductor and filter capacitors close
together and make the traces short. The traces between
these components carry relatively high switching cur-
rents and act as antennas. Following this rule reduces
radiated noise. Special care must be given to place the
input filter capacitor very close to the VIN and GND pin.
2. Arrange the components so that the switching current
loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor
through the LP3905 and inductor to the output filter
capacitor and back through ground, forming a current
loop. In the second half of each cycle, current is pulled
up from ground through the LP3905 by the inductor to
the output filter capacitor and then back through ground
forming a second current loop. Routing these loops so
the current curls in the same direction prevents mag-
netic field reversal between the two half-cycles and re-
duces radiated noise.
6. Place noise sensitive circuitry, such as radio IF blocks,
away from the DC-DC converter, CMOS digital blocks
and other noisy circuitry. Interference with noise-
sensitive circuitry in the system can be reduced through
distance.
In mobile phones, for example, a common practice is to
place the DC-DC converters on one corner of the board,
arrange the CMOS digital circuitry around it (since this also
generates noise), and then place sensitive preamplifiers and
IF stages on the diagonally opposing corner. Often, the
sensitive circuitry is shielded with a metal pan and power to
it is post-regulated to reduce conducted noise, using low-
dropout linear regulators.
3. Connect the ground pins of the Bucks and filter capaci-
tors together using generous component-side copper fill
as a pseudo-ground plane. Then, connect this to the
ground-plane (if one is used) with several vias. This
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14
Physical Dimensions inches (millimeters) unless otherwise noted
14 Pin LLP Package
NS Package Number SDA14B
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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(b) support or sustain life, and whose failure to perform when
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