LP3906SQDJXI [NSC]
IC 2 A DUAL SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, QCC24, 5 X 4 MM, 0.80 MM HEIGHT, LLP-24, Switching Regulator or Controller;
| 型号： | LP3906SQDJXI |
| 厂家： | 
National Semiconductor |
| 描述： | IC 2 A DUAL SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, QCC24, 5 X 4 MM, 0.80 MM HEIGHT, LLP-24, Switching Regulator or Controller 稳压器 |
| 文件： | 总38页 (文件大小：1998K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.DataSheet4U.com
September 2006
LP3906
Dual High-Current Step-Down DC/DC and Dual Linear
Regulator with I2C Compatible Interface
General Description
Features
n Compatible with advanced applications processors and
FPGAs
The LP3906 is a multi-function, programmable Power Man-
agement Unit, optimized for low power FPGAs, Microproces-
sors and DSPs. This device integrates two highly efficient
1.5A Step-Down DC/DC converters with dynamic voltage
management (DVM), two 300mA Linear Regulators and a
400kHz I2C compatible interface to allow a host controller
access to the internal control registers of the LP3906. The
LP3906 additionally features programmable power-on se-
quencing and is offered in a tiny 5 x 4 x 0.8mm LLP-24 pin
package.
n 2 LDOs for powering Internal processor functions and
I/Os
n High speed serial interface for independent control of
device functions and settings
n Precision internal reference
n Thermal overload protection
n Current overload protection
n 24-lead 5 x 4 x 0.8 mm LLP package
n Software Programmable Regulators
Key Specifications
Step-Down DC/DC Converter (Buck)
Applications
n 1.5A output current
n FPGA, DSP core power
n Applications processors
n Peripheral I/O power
n
Programmable Vout from:
— Buck1 : 0.8V–2.0V
— Buck2 : 1.0V–3.5V
n Up to 96% efficiency
n 2 MHz PWM switching frequency
n
3% output voltage accuracy
n Automatic soft start
Linear Regulators (LDO)
n Programmable VOUT of 1.0V–3.5V
n
3% output voltage accuracy
n 300 mA output currents
n 25 mV (typ) Dropout
© 2006 National Semiconductor Corporation
DS201978
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Typical Application Circuit
20197801
FIGURE 1. Typical Application Circuit
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(Continued)
20197863
* For information about how schottky diodes can reduce noise in high load, high Vin applications, refer to "Buck Output Ripple
Management" in the Application Notes section.
FIGURE 2. Typical Application Circuit
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Connection Diagram
20197802
* Refer to Package Marking in Ordering Information Table Below
FIGURE 3. 24-Lead LLP Package (Top View)
Note: The physical placement of the package marking will vary from part to part.
(*) UZXYTT format: ‘U’ – wafer fab code; ‘Z’ – assembly code; ’XY’ 2 digit date code; ‘TT” – die run code
See http://www.national.com/quality/marking_conventions.html for more information on marking information.
Ordering Information
Voltage Option Order Number
Package Type
NSC Package Package
Supplied As
Drawing
Marking
06-JXXI
06-JXXI
06-DJXI
06-DJXI
Voltage JXXI
Voltage JXXI
Voltage DJXI
Voltage DJXI
LP3906SQ JXXI
LP3906SQX JXXI
LP3906SQ DJXI
LP3906SQX DJXI
24 lead LLP
24 lead LLP
24 lead LLP
24 lead LLP
SQA024AG
SQA024AG
SQA024AG
SQA024AG
1000 tape & reel
4500 tape & reel
1000 tape & reel
4500 tape & reel
Default Voltage Options
Regulator
Version JXXI
Version DJXI
Default Voltages (V)
Default Voltages (V)
SW1
SW2
1.2
3.3
3.3
1.8
0.9
1.8
3.3
1.8
LDO1
LDO2
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Pin Descriptions
Pin
Pin Name
I/O
I
Type
PWR
PWR
G
Functional Description
Power in from either DC source or Battery to Buck 2
Buck2 switcher output pin
1
2
VIN2
SW2
O
G
G
G
O
I
3
GND_SW2
GND_C
GND_SW1
SW1
Buck2 NMOS Power Ground
4
G
Non switching core ground pin
5
G
Buck1 NMOS Power Ground
6
PWR
PWR
D
Buck1 switcher output pin
7
VIN1
Power in from either DC source or Battery to buck 1
I2C Data (Bidirectional)
I2C Clock
8
SDA
I/O
I
9
SCL
D
10
11
12
13
EN_T
I
D
Enable for preset power on sequence.
Buck1 input feedback terminal
FB1
I
A
AVDD
VINLDO1
I
PWR
PWR
Analog Power for Buck converters.
Power in from either DC source or Battery to input terminal of
LDO1
I
14
15
16
17
18
19
LDO1
ENLDO1
ENLDO2
GND_L
LDO2
O
I
PWR
D
LDO1 Output
LDO1 enable pin, a logic HIGH enables the LDO1
LDO2 enable pin, a logic HIGH enables the LDO2
LDO Ground
I
D
G
O
I
G
PWR
PWR
LDO2 Output
VINLDO2
Power in from either DC source or battery to input terminal to
LDO2
20
21
22
23
VinLDO12
FB2
I
I
I
I
PWR
A
Analog Power for Internal Functions (VREF, BIAS, I2C, Logic)
Buck2 input feedback terminal
ENSW1
SYNC
D
Enable Pin for Buck1 switcher, a logic HIGH enables Buck1
Frequency Synchronization pin which allows the user to
connect an external clock signal PLL to synchronize the PMIC
internal oscillator.
D
24
ENSW2
I
D
Enable Pin for Buck2 switcher, a logic HIGH enables Buck2
A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin
5
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings (Notes 1, 2, 7)
Bucks
VIN
2.7V to 5.5V
VEN
0 to (VIN + 0.3V)
−40˚C to +125˚C
VIN, SDA, SCL
−0.3V to +6V
0.3V
Junction Temperature (TJ) Range
GND to GND SLUG
Power Dissipation (PD_MAX
Ambient Temperature (TA) Range (Note 6) −40˚C to +85˚C
Thermal Properties (Notes 3, 5, 6)
)
(TA=85˚C, TMAX=125˚C, (Note 5))
1.43 W
150˚C
Junction-to-Ambient Thermal Resistance
Junction Temperature (TJ-MAX
Storage Temperature Range
)
(θJA)SQA024AG
28˚C/W
−65˚C to +150˚C
260˚C
Maximum Lead Temperature (Soldering)
ESD Ratings
Human Body Model (Note 4)
2 kV
Electrical Characteristics
General Electrical Characteristics (Notes 1, 2, 7, 13)
Unless otherwise noted, VIN = 3.6V, Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C.
Symbol
VPOR
Parameter
Power-On Reset Threshold
Thermal Shutdown Threshold
Themal Shutdown Hysteresis
Conditions
VDD Falling Edge
Min
Typ
1.9
160
20
Max
Units
V
TSD
˚C
TSDH
˚C
I2C Compatible Interface Electrical Specifications (Note 13)
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C
Symbol
FCLK
Parameter
Clock Frequency
Bus-Free Time Between Start and Stop (Note 13)
Conditions
Min
Typ
Max
Units
kHz
µs
400
tBF
1.3
0.6
1.3
0.6
0.6
0
tHOLD
tCLKLP
tCLKHP
tSU
Hold Time Repeated Start Condition
CLK Low Period
(Note 13)
(Note 13)
(Note 13)
(Note 13)
(Note 13)
(Note 13)
(Note 13)
(Note 13)
µs
µs
CLK High Period
µs
Set Up Time Repeated Start Condition
Data Hold time
µs
tDATAHLD
tDATASU
TSU
µs
Data Set Up Time
100
0.6
ns
Set Up Time for Start Condition
Maximum Pulse Width of Spikes that
Must be Suppressed by the Input Filter
of Both DATA & CLK Signals.
µs
TTRANS
50
ns
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Electrical Characteristics (Continued)
Low Drop Out Regulators, LDO1 and LDO2
Unless otherwise noted, VIN = 3.6, CIN = 1.0 µF, COUT = 0.47 µF. Typical values and limits appearing in normal type apply for
TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C.
(Notes 2, 7, 8, 9, 10, 11, 12)
Symbol
Parameter
Conditions
VINLDO1 and VINLDO2 PMOS
pins(Note 15)
Min
Typ
Max
5.5
Units
VIN
Operational Voltage Range
1.74
V
VOUT
Output Voltage Accuracy (Default VOUT
)
Load current = 1 mA
−3
3
%
Accuracy
∆VOUT
Line Regulation
VIN = (VOUT + 0.3V) to 5.0V,
(Note 12), Load Current = 1 mA
VIN = 3.6V,
0.15
0.011
%/V
Load Regulation
%/mA
mA
Load Current = 1 mA to IMAX
LDO1-2, VOUT = 0V
Load Current = 50 mA
(Note 10)
ISC
Short Circuit Current Limit
Dropout Voltage
500
25
VIN – VOUT
200
mV
PSRR
Power Supply Ripple Rejection
Supply Output Noise
F = 10 kHz, Load Current =
IMAX
45
dB
<
<
100 KHz
θn
10 Hz
F
80
40
µVrms
µA
IQ (Notes 11, Quiescent Current “On”
IOUT = 0 mA
IOUT = IMAX
14)
Quiescent Current “On”
Quiescent Current “Off”
Turn On Time
60
µA
EN is de-asserted(Note 16)
Start up from shut-down
Capacitance for stability
0˚C ≤ TJ ≤ 125˚C
0.03
300
µA
TON
µs
COUT
Output Capacitor
0.33
0.47
1.0
µF
−40˚C ≤ TJ ≤ 125˚C
ESR
0.68
5
µF
500
mΩ
Buck Converters SW1, SW2
Unless otherwise noted, VIN = 3.6, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2 µH ceramic. Typical values and limits appearing in
normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for opera-
tion, −40˚C to +125˚C. (Notes 2, 7, 8, 9, 14)
Symbol
VOUT
Parameter
Output Voltage Accuracy
Line Regulation
Conditions
Default VOUT
Min
Typ
Max
Units
%
−3
+3
<
<
2.7 VIN 5.5
0.089
%/V
IO =10 mA
<
<
Load Regulation
100 mA IO IMAX
Load Current = 250 mA
EN is de-asserted
0.0013
96
%/mA
%
Eff
Efficiency
ISHDN
fOSC
Shutdown Supply Current
Sync Mode Clock Frequency
0.01
2.0
µA
Synchronized from 13 MHz
system clock
MHz
Internal Oscillator Frequency
Peak Switching Current Limit
Quiescent Current “On”
Pin-Pin Resistance PFET
Pin-Pin Resistance NFET
Turn On Time
2.0
2.0
33
MHz
A
IPEAK
IQ (Note 14)
RDSON (P)
RDSON (N)
TON
No load PFM Mode
µA
mΩ
mΩ
µs
200
180
500
Start up from shut-down
Capacitance for stability
Capacitance for stability
CIN
Input Capacitor
10
10
µF
CO
Output Capacitor
µF
7
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Electrical Characteristics (Continued)
IO Electrical Characteristics
Unless otherwise noted: Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface
type apply over the entire junction temperature range for operation, TJ = 0˚C to +125˚C. (Note 13)
Limit
Symbol
Parameter
Conditions
Units
Min
1.2
Max
0.4
VIL
VIH
Input Low Level
Input High Level
V
V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T = 160˚C (typ.) and disengages at T
=
J
J
140˚C (typ.)
Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MILSTD - 883 3015.7)
Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T ) is dependent on the maximum operating junction temperature (T = 125˚C), the maximum power
A-MAX
J-MAX-OP
dissipation of the device in the application (P
), and the junction-to-ambient thermal resistance of the part/package in the application (θ ), as given by the
D-MAX
JA
following equation: T
= T
− (θ x P
). See applications section.
A-MAX
J-MAX-OP
JA
D-MAX
Note 6: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 8: C , C
: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
OUT
IN
Note 9: The device maintains a stable, regulated output voltage without a load.
Note 10: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value.
Note 11: Quiescent current is defined here as the difference in current between the input voltage source and the load at V
.
OUT
Note 12: V minimum for line regulation values is 1.8V.
IN
Note 13: This specification is guaranteed by design.
Note 14: The Iq can be defined as the standing current of the LP3906 when the I2C bus is active and all other power blocks have been disabled via the I2C bus,
or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two values can be used by the system designer
when the LP3906 is powered using a battery. If the user plans to use the HW enable pins to disable each block of the IC please contact the factory applications for
IQ details.
Note 15: Pins 13, 19 can operate from Vin min of 1.74 to a Vin max of 5.5V this rating is only for the series pass pmos power fet. It allows the system design to
use a lower voltage rating if the input voltage comes from a buck output.
Note 16: The Iq exhibits a higher current draw when the EN pin is de-asserted because the I2C buffer pins draw an additional 2µA
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Typical Performance Characteristics — LDO TA = 25˚C unless otherwise noted
Output Voltage Change vs Temperature (LDO1)
Vin = 4.3V, Vout = 3.3V, 100 mA load
Output Voltage Change vs Temperature (LDO2)
Vin = 4.3V, Vout = 1.8V, 100 mA load
20197835
20197836
Load Transient (LDO1)
Load Transient (LDO2)
3.6 Vin, 3.3 Vout, 0 – 100 mA load
3.6 Vin, 1.8 Vout, 0 – 100 mA load
20197837
20197838
Line Transient (LDO1)
Line Transient (LDO2)
3.6 - 4.5 Vin, 3.3 Vout, 150 mA load
3 – 4.2 Vin, 1.8 Vout, 150 mA load
20197839
20197840
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Typical Performance Characteristics — LDO TA = 25˚C unless otherwise noted (Continued)
Enable Start-up time (LDO1) )
0-3.6 Vin, 3.3 Vout, 1mA load
Enable Start-up time (LDO2)
0 – 3.6 Vin, 1.8 Vout, 1 mA load
20197841
20197842
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Typical Performance Characteristics — Buck TA = 25˚C unless otherwise noted
Output Voltage vs. Supply Voltage
(Vout = 1.0 V)
Shutdown Current vs. Temp
20197844
20197843
Output Voltage vs. Supply Voltage
(Vout = 1.8V)
Output Voltage vs. Supply Voltage
(Vout = 3.5V)
20197845
20197846
Buck 1 Efficiency vs Output Current
Buck 1 Efficiency vs Output Current
(Forced PWM Mode, Vout =1.2V, L= 2.2µH)
(Forced PWM Mode, Vout =2.0V, L= 2.2µH)
20197847
20197848
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Typical Performance Characteristics — Buck TA = 25˚C unless otherwise noted (Continued)
Buck 1 Efficiency vs Output Current
Buck 1 Efficiency vs Output Current
(PFM to PWM mode, Vout =1.2V, L= 2.2µH)
(PFM to PWM mode, Vout =2.0V, L= 2.2µH)
20197849
20197850
Buck 2 Efficiency vs Output Current
Buck 2 Efficiency vs Output Current
(Forced PWM Mode, Vout =1.8V, L= 2.2µH)
(Forced PWM Mode, Vout =3.3V, L= 2.2µH)
20197851
20197852
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Typical Performance Characteristics — Buck TA = 25˚C unless otherwise noted (Continued)
Buck 2 Efficiency vs Output Current
Buck 2 Efficiency vs Output Current
(PFM to PWM Mode, Vout =1.8V, L= 2.2µH)
(PFM to PWM Mode, Vout =3.3V, L= 2.2µH)
20197853
20197854
Load Transient Response
Vout = 1.2 (PWM Mode)
Mode Change by Load Transient
Vout = 1.2V (PWM to PFM)
20197855
20197856
Line Transient Response
Line Transient Response
Vin = 3 – 3.6 V, Vout = 1.2 V, 250 mA load
Vin = 3 – 3.6 V, Vout = 3.3 V, 250 mA load
20197858
20197857
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Typical Performance Characteristics — Buck TA = 25˚C unless otherwise noted (Continued)
Start up into PWM Mode
Vout = 1.8 V, 1.2 A load
Start up into PWM Mode
Vout = 3.3 V, 1.2 A load
20197859
20197860
Start up into PFM Mode
Vout = 1.8 V, 30 mA load
Start up into PFM Mode
Vout = 3.3 V, 30 mA load
20197861
20197862
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DC/DC Converters
OVERVIEW
The LP3906 supplies the various power needs of the application by means of two Linear Low Drop Regulators LDO1 and LDO2
and two Buck converters SW1 and SW2. The table here under lists the output characteristics of the various regulators.
SUPPLY SPECIFICATION
Output
IMAX
Supply
Load
VOUT Range(V)
Resolution (mV)
Maximum Output
Current (mA)
300
LDO1
LDO2
SW1
analog
analog
digital
digital
1.0 to 3.5
1.0 to 3.5
0.8 to 2.0
1.0 to 3.5
100
100
50
300
1500
SW2
100
1500
*For default values of the regulators, please consult Default Voltage Options Table page 3
LINEAR LOW DROP-OUT REGULATORS (LDOS)
The output voltages of both LDOs are register program-
mable. The default output voltages are factory programmed
during Final Test, which can be tailored to the specific needs
of the system designer.
LDO1 and LDO2 are identical linear regulators targeting
analog loads characterized by low noise requirements.
LDO1 and LDO2 are enabled through the ENLDO pin or
through the corresponding LDO1 or LDO2 control register.
20197822
NO-LOAD STABILITY
mable in steps of 100mV from 1.0V to 3.5V by programming
bits D4-0 in the LDO Control registers. Both LDO1 and LDO2
are enabled by applying a logic 1 to the ENLDO1 and
ENLDO2 pin. Enable/disable control is also provided through
enable bit of the LDO1 and LDO2 control registers. The
value of the enable LDO bit in the register is logic 1 by
default. The output voltage can be altered while the LDO is
enabled.
The LDOs will remain stable and in regulation with no exter-
nal load. This is an important consideration in some circuits,
for example CMOS RAM keep-alive applications.
LDO1 AND LDO2 CONTROL REGISTERS
LDO1 and LDO2 can be configured by means of the LDO1
and LDO2 control registers. The output voltage is program-
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The DC gain of the power stage is proportional to the input
voltage. To eliminate this dependence, feed forward voltage
inversely proportional to the input voltage is introduced.
SW1, SW2: Synchronous Step
Down Magnetic DC/DC Converters
FUNCTIONAL DESCRIPTION
INTERNAL SYNCHRONOUS RECTIFICATION
The LP3906 incorporates two high efficiency synchronous
switching buck regulators, SW1 and SW2 that deliver a
constant voltage from a single Li-Ion battery to the portable
system processors. Using a voltage mode architecture with
synchronous rectification, both bucks have the ability to
deliver up to 1500mA depending on the input voltage and
output voltage (voltage head room), and the inductor chosen
(maximum current capability).
While in PWM mode, the buck uses an internal NFET as a
synchronous rectifier to reduce rectifier forward voltage drop
and associated power loss. Synchronous rectification pro-
vides a significant improvement in efficiency whenever the
output voltage is relatively low compared to the voltage drop
across an ordinary rectifier diode.
CURRENT LIMITING
There are three modes of operation depending on the cur-
rent required - PWM, PFM, and shutdown. PWM mode
handles current loads of approximately 70mA or higher,
delivering voltage precision of +/-3% with 90% efficiency or
better. Lighter output current loads cause the device to au-
tomatically switch into PFM for reduced current consumption
(IQ = 15 µA typ.) and a longer battery life. The Standby
operating mode turns off the device, offering the lowest
current consumption. PWM or PFM mode is selected auto-
matically or PWM mode can be forced through the setting of
the buck control register.
A current limit feature allows the converter to protect itself
and external components during overload conditions. PWM
mode implements current limiting using an internal compara-
tor that trips at 2.0 A (typ). If the output is shorted to ground
the device enters a timed current limit mode where the NFET
is turned on for a longer duration until the inductor current
falls below a low threshold, ensuring inductor current has
more time to decay, thereby preventing runaway.
A current limit feature allows the buck to protect itself and
external components during overload conditions PWM mode
implements cycle-by-cycle current limiting using an internal
comparator that trips at 2000mA (typical).
Both SW1 and SW2 can operate up to a 100% duty cycle
(PMOS switch always on) for low drop out control of the
output voltage. In this way the output voltage will be con-
trolled down to the lowest possible input voltage.
PFM OPERATION
At very light loads, the converter enters PFM mode and
operates with reduced switching frequency and supply cur-
rent to maintain high efficiency.
Additional features include soft-start, under-voltage lock-out,
current overload protection, and thermal overload protection.
The part will automatically transition into PFM mode when
either of two conditions occurs for a duration of 32 or more
clock cycles:
CIRCUIT OPERATION DESCRIPTION
A buck converter contains a control block, a switching PFET
connected between input and output, a synchronous rectify-
ing NFET connected between the output and ground (BCK-
GND pin) and a feedback path. During the first portion of
each switching cycle, the control block turns on the internal
PFET switch. This allows current to flow from the input
through the inductor to the output filter capacitor and load.
The inductor limits the current to a ramp with a slope of
A. The inductor current becomes discontinuous
or
B. The peak PMOS switch current drops below the IMODE
level
During PFM operation, the converter positions the output
voltage slightly higher than the nominal output voltage during
PWM operation, allowing additional headroom for voltage
drop during a load transient from light to heavy load. The
PFM comparators sense the output voltage via the feedback
pin and control the switching of the output FETs such that the
output voltage ramps between 0.8% and 1.6% (typical)
above the nominal PWM output voltage. If the output voltage
is below the ‘high’ PFM comparator threshold, the PMOS
power switch is turned on. It remains on until the output
voltage exceeds the ‘high’ PFM threshold or the peak current
exceeds the IPFM level set for PFM mode. The typical peak
current in PFM mode is:
by storing energy in a magnetic field. During the second
portion of each cycle, the control block turns the PFET
switch off, blocking current flow from the input, and then
turns the NFET synchronous rectifier on. The inductor draws
current from ground through the NFET to the output filter
capacitor and load, which ramps the inductor current down
with a slope of
The output filter stores charge when the inductor current is
high, and releases it when low, smoothing the voltage across
the load.
Once the PMOS power switch is turned off, the NMOS
power switch is turned on until the inductor current ramps to
zero. When the NMOS zero-current condition is detected,
the NMOS power switch is turned off. If the output voltage is
below the ‘high’ PFM comparator threshold (see figure be-
low), the PMOS switch is again turned on and the cycle is
PWM OPERATION
During PWM operation the converter operates as a voltage-
mode controller with input voltage feed forward. This allows
the converter to achieve excellent load and line regulation.
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the internal state machine of the LP3906 following a
Power-On event that moves the operating mode to the Ac-
tive state. (see Power On Sequence). The SW1 and SW2
output voltages revert to default values when the power on
sequence has been completed. The default output voltage
for each buck converter is factory programmable. (See Ap-
plication Notes).
SW1, SW2: Synchronous Step
Down Magnetic DC/DC Converters
(Continued)
repeated until the output reaches the desired level. Once the
output reaches the ‘high’ PFM threshold, the NMOS switch is
turned on briefly to ramp the inductor current to zero and
then both output switches are turned off and the part enters
an extremely low power mode. Quiescent supply current
during this ‘sleep’ mode is less than 30 µA, which allows the
part to achieve high efficiencies under extremely light load
conditions. When the output drops below the ‘low’ PFM
threshold, the cycle repeats to restore the output voltage to
SW1, SW2 can be enabled/disabled through the corre-
sponding control register.
The Modulation mode PWM/PFM is by default automatic
and depends on the load as described above in the func-
tional description. The modulation mode can be overridden
by setting I2C bit to a logic 1 in the corresponding buck
control register, forcing the buck to operate in PWM mode
regardless of the load condition.
~
1.6% above the nominal PWM output voltage.
If the load current should increase during PFM mode (see
figure below) causing the output voltage to fall below the
‘low2’ PFM threshold, the part will automatically transition
into fixed-frequency PWM mode.
SW1, SW2 OPERATION
SW1 and SW2 have selectable output voltages ranging from
0.8V to 3.5V (typ.). Both SW1 and SW2 in the LP3906 are
I2C register controlled and are enabled by default through
20197803
SHUTDOWN MODE
to logic high after VIN reaches 2.8V. Soft start is imple-
mented by increasing switch current limit in steps of 213 mA,
425 mA, 850 mA and 1700 mA (typ. Switch current limit). The
start-up time thereby depends on the output capacitor and
load current demanded at start-up.
During shutdown the PFET switch, reference, control and
bias circuitry of the converters are turned off. The NFET
switch will be on in shutdown to discharge the output. When
the converter is enabled, soft start is activated. It is recom-
mended to disable the converter during the system power up
and under voltage conditions when the supply is less than
2.8V.
LOW DROPOUT OPERATION
The LP3906 can operate at 100% duty cycle (noswitching;
PMOS switch completely on) for low drop out support of the
output voltage. In this way the output voltage will be con-
trolled down to the lowest possible input voltage. When the
device operates near 100% duty cycle, output voltage ripple
is approximately 25 mV. The minimum input voltage needed
to support the output voltage is
SOFT START
The soft-start feature allows the power converter to gradually
reach the initial steady state operating point, thus reducing
start-up stresses and surges. The two LP3906 buck convert-
ers have a soft-start circuit that limits in-rush current during
start-up. During start-up the switch current limit is increased
in steps. Soft start is activated only if EN goes from logic low
17
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EN_T is edge triggered with rising edge signaling the chip to
power on. The EN_T input is deglitched and the default is set
at 1 ms. As shown in the next 2 diagrams, a rising EN_T
edge will start a power on sequence, while a falling EN_T
edge will start a shutdown sequence. If EN_T is high, tog-
gling the external enables of the regulators will have no
effect on the chip.
SW1, SW2: Synchronous Step
Down Magnetic DC/DC Converters
(Continued)
VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT
Load current
•
•
ILOAD
Drain to source resistance of
PFET switch in the triode region
Inductor resistance
RDSON, PFET
Default Power ON Sequence:
t1 (ms)
1.5
t2 (ms)
2.0
t3 (ms)
3
t4 (ms)
6
•
RINDUCTOR
FLEXIBLE POWER SEQUENCING OF MULTIPLE
POWER SUPPLIES
Note: LP3906 The default Power on delays can be reprogrammed at final
2
test or by using I C registers to 1, 1.5, 2, 3, 6, or 11 ms.
The LP3906 provides several options for power on sequenc-
ing. The two bucks can be individually controlled with
ENSW1 and ENSW2. The two LDOs can also be individually
controlled with ENLDO1 and ENLDO2.
The regulators can also be programmed through I2C to turn
on and off. By default, the I2C enables for the regulators are
ON.
The regulators are on following the pattern below:
Regulators on = (I2C enable) AND (External pin enable OR
EN_T high).
If the user desires a set power on sequence, all four enables
should be tied LOW so that the regulators don’t automati-
cally enable when power is supplied. The user can then
program the chip through I2C and raise EN_T from LOW to
HIGH to activate the power on sequencing.
POWER ON
EN_T assertion causes the LP3906 to emerge from Standby
mode to Full Operation mode at a preset timing sequence.
By default, the enables for the LDOs and Bucks are inter-
nally pulled up, which causes the part to turn ON automati-
cally. If the user wishes to have a preset timing sequence to
power on the regulators, the external regulator enables must
be tied LOW. Otherwise, simply tie the enables of each
specific regulator HIGH.
20197809
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LP3906 Default Power-Up Sequence
20197810
Power-On Timing Specification
Symbol
Description
Min
Typ
1.5
2
Max
Units
t1
Programmable Delay from EN_T assertion to VCC_Buck1 On
Programmable Delay from EN_T assertion to VCC_Buck2 On
Programmable Delay from EN_T assertion to VCC_LDO1 On
Programmable Delay from EN_T assertion to VCC_LDO2 On
ms
ms
ms
ms
t2
t3
t4
3
6
2
Note: LP3906 The default Power on delays can be reprogrammed at final test or I C to 1, 1.5, 2, 3, 6, or 11 ms.
19
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LP3906 Default Power-Off Sequence
20197811
Symbol
t1
Description
Min
Typ
1.5
2
Max
Units
ms
Programmable Delay from EN_T deassertion to VCC_Buck1 Off
Programmable Delay from EN_T deassertion to VCC_Buck2 Off
Programmable Delay from EN_T deassertion to VCC_LDO1 Off
Programmable Delay from EN_T deassertion to VCC_LDO2 Off
t2
t3
t4
ms
3
ms
6
ms
Note: LP3906 The default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or 10 ms. Default setting is the same as the on sequence.
VDD rises above the minimum operating voltage of the Logic
and the internal oscillator that clocks the Sequential Logic in
Power-On-Reset
The LP3906 is equipped with an internal Power-On-Reset
the Control section.
<
(“POR”) circuit that will reset the logic when VDD
This guarantees that the logic is properly initialized when
VPOR.
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20
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Signal timing specifications are according to the I2C bus
specification. The maximum bit rate is 400 kbit/s. See I2C
specification from Philips for further details.
I2C Compatible Serial Interface
I2C SIGNALS
The LP3906 features an I2C compatible serial interface,
using two dedicated pins: SCL and SDA for I2C clock and
data respectively. Both signals need a pull-up resistor ac-
cording to the I2C specification. The LP3906 interface is an
I2C slave that is clocked by the incoming SCL clock.
I2C DATA VALIDITY
The data on the SDA line must be stable during the HIGH
period of the clock signal (SCL), e.g.- the state of the data
line can only be changed when CLK is LOW.
20197816
I2C Signals: Data Validity
I2C START AND STOP CONDITIONS
always generates START and STOP bits. The I2C bus is
considered to be busy after START condition and free after
STOP condition. During data transmission, I2C master can
generate repeated START conditions. First START and re-
peated START conditions are equivalent, function-wise.
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as the SDA
signal transitioning from HIGH to LOW while the SCL line is
HIGH. STOP condition is defined as the SDA transitioning
from LOW to HIGH while the SCL is HIGH. The I2C master
20197817
START and STOP Conditions
TRANSFERRING DATA
eighth bit which is a data direction bit (R/W). Please note that
according to industry I2C standards for 7-bit addresses, the
MSB of an 8-bit address is removed, and communication
actually starts with the 7th most significant bit. For the eighth
bit (LSB), a “0” indicates a WRITE and a “1” indicates a
READ. The second byte selects the register to which the
data will be written. The third byte contains data to write to
the selected register.
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledged related clock pulse is generated by the mas-
ter. The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the 9th clock pulse, signifying acknowledge-
ment. A receiver which has been addressed must generate
an acknowledgement (“ACK”) after each byte has been re-
ceived.
LP3906 has a chip address of 60’h, which is factory
programmed.
After the START condition, the I2C master sends a chip
address. This address is seven bits long followed by an
20197818
I2C Chip Address
21
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I2C Compatible Serial Interface (Continued)
20197819
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = LP3906 chip address : 0x60
I2C Write Cycle
When a READ function is to be accomplished, a WRITE
function must precede the READ function, as shown in the
Read Cycle waveform.
20197824
I2C Read Cycle
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LP3906 Control Registers
Register Register
Read/Write
Register Description
Address
0x02
0x07
0x10
0x11
0x20
0x23
0x24
0x25
0x29
0x2A
0x2B
0x38
0x39
0x3A
Name
ICRA
R
Interrupt Status Register A
System Control 1 Register
SCR1
R/W
R/W
R
BKLDOEN
BKLDOSR
VCCR
Buck and LDO Output Voltage Enable Register
Buck and LDO Output Voltage Status Register
Voltage Change Control Register 1
Buck 1 Target Voltage 1 Register
Buck 1 Target Voltage 2 Register
Buck 1 Ramp Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
B1TV1
B1TV2
B1RC
B2TV1
Buck 2 Target Voltage 1 Register
Buck 2 Target Voltage 2 Register
Buck 2 Ramp Control
B2TV2
B2RC
BFCR
Buck Function Register
LDO1VCR
LDO2VCR
LDO1 Voltage control Registers
LDO2 Voltage control Registers
23
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LP3906 Control Registers (Continued)
INTERRUPT STATUS REGISTER (ISRA) 0X02
This register informs the user of the temperature status of the chip.
D7-2
—
D1
D0
Name
Access
Data
Temp 125˚C
R
—
—
—
>
Reserved
Status bit for thermal warning PMIC T 125˚C
Reserved
<
0 – PMIC Temp. 125˚C
>
1 – PMIC Temp. 125˚C
Reset
0
0
0
CONTROL 1 REGISTER (SCR1) 0X07
This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM and PWM mode
for the bucks, and also to select between an internal and external clock for the bucks.
The external LDO and SW enables should be pulled LOW to allow the blocks to sequence correctly through assertion of the EN_T
pin.
D7
—
—
D6-4
D3
—
—
D2
D1
D0
Name
Access
Data
EN_DLY
R/W
FPWM2
R/W
FPWM1
ECEN
R/W
R/W
Reserved Selects the preset
delay sequence from
EN_T assertion
Reserved Buck 2 PWM /PFM
Mode select
Buck 1 PWM /PFM
Mode select
External Buck Clock
Select
0 – Auto Switch PFM 0 – Auto Switch PFM 0 – Internal 2 MHz
- PWM operation - PWM operation Oscillator clock
(shown below)
1 – PWM Mode Only 1 – PWM Mode Only 1 – External 13 MHz
Oscillator clock
Reset
0
010
1
0
0
0
EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION
Delay (ms)
<
>
EN_DLY 2:0
Buck1
1
Buck2
LDO1
LDO2
000
001
010
011
100
101
110
111
1
1.5
2
1
2
3
1
3
2
1
6
1
2
1
1.5
1.5
1.5
1.5
3
6
2
1
2
6
1.5
2
2
1.5
11
2
3
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LP3906 Control Registers (Continued)
BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10
This register controls the enables for the Bucks and LDOs.
D7
D6
D5
D4
D3
D2
D1
D0
Name
Access
Data
—
LDO2EN
R/W
—
LDO1EN
R/W
—
BK2EN
R/W
—
BK1EN
R/W
—
—
—
—
Reserved
0 – Disable
1 – Enable
1
Reserved
0 – Disable
1 – Enable
1
Reserved
0 – Disable
1 – Enable
1
Reserved
0 – Disable
1 – Enable
1
Reset
0
1
0
0
BUCK AND LDO STATUS REGISTER (BKLDOSR) – 0X11
This register monitors whether the Bucks and LDOs meet the voltage output specifications.
D7
D6
D5
D4
D3
—
—
D2
D1
—
—
D0
Name BKS_OK
LDOS_OK
R
LDO2_OK
R
LDO1_OK
R
BK2_OK
R
BK1_OK
R
Access
Data
R
0 – Buck 1-2 0 – LDO 1-2 0 – LDO2 Not 0 – LDO1 Not Reserved 0 – Buck2 Not Reserved 0 – Buck1
Not Valid
1 – Bucks
Valid
Not Valid
1 – LDOs
Valid
Valid
1 – LDO2
Valid
0
Valid
1 – LDO1
Valid
0
Valid
Not Valid
1 – Buck1
Valid
1 – Buck2
Valid
Reset
0
0
0
0
0
0
BUCK VOLTAGE CHANGE CONTROL REGISTER 1 (VCCR) – 0X20
This register selects and controls the output target voltages for the buck regulators.
D7-6
—
D5
D4
D3-2
—
D1
D0
Name
Access
Data
B2VS
R/W
B2GO
R/W
B1VS
R/W
B1GO
R/W
—
—
Reserved
Buck2 Target Voltage Buck2 Voltage Ramp Reserved
Buck1 Target Voltage Buck1 Voltage Ramp
Select
CTRL
Select
CTRL
0 – B2VT1
1 – B2VT2
0 – Hold
0 – B1VT1
1 – B1VT2
0 – Hold
1 – Ramp to B2VS
1 – Ramp to B1VS
selection
0
selection
0
Reset 00
0
00
0
25
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LP3906 Control Registers (Continued)
BUCK 1 TARGET VOLTAGE 2 REGISTER (B1TV2) –
0X24
BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) –
0X23
This register allows the user to program the output target
voltage of Buck 1.
This register allows the user to program the output target
voltage of Buck 1.
D7-5
—
D4-0
BK1_VOUT2
D7-5
—
D4-0
BK1_VOUT1
Name
Access
Data
Name
Access
Data
—
R/W
—
R/W
Reserved
Buck1 Output Voltage (V)
Reserved
Buck1 Output Voltage (V)
5’h00
5’h01
5’h02
5’h03
5’h04
5’h05
5’h06
5’h07
5’h08
5’h09
5’h0A
5’h0B
5’h0C
5’h0D
5’h0E
5’h0F
5’h10
5’h11
Ext Ctrl
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.00
5’h00
5’h01
5’h02
5’h03
5’h04
5’h05
5’h06
5’h07
5’h08
5’h09
5’h0A
5’h0B
5’h0C
5’h0D
5’h0E
5’h0F
5’h10
5’h11
Ext Ctrl
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.00
5’h12
5’h13
5’h14
5’h15
5’h16
5’h17
5’h18
5’h19
5’h1A–5’h1F
5’h12
5’h13
5’h14
5’h15
5’h16
5’h17
5’h18
5’h19
5’h1A–5’h1F
Reset
000
Factory Programmed Default
Reset
000
Factory Programmed Default
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LP3906 Control Registers (Continued)
BUCK 1 RAMP CONTROL REGISTER (B1RC) - 0x25
This register allows the user to program the rate of change between the target voltages of Buck 1.
D7
- - - -
D6-4
- - - -
D3-0
B1RS
R/W
Name
Access
Data
- - - -
- - - -
Reserved
Reserved
Data Code
4h’0
Ramp Rate mV/us
Instant
4h’1
1
2
4h’2
4h’3
3
4h’4
4
4h’5
5
4h’6
6
4h’7
7
4h’8
8
4h’9
9
4h’A
10
10
4h’B - 4h’F
Reset
0
010
1000
27
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LP3906 Control Registers (Continued)
BUCK 2 TARGET VOLTAGE 2 REGISTER (B2TV2) –
0X2A
BUCK 2 TARGET VOLTAGE 1 REGISTER (B2TV1) –
0X29
This register allows the user to program the output target
voltage of Buck 2.
This register allows the user to program the output target
voltage of Buck 2.
D7-5
—
D4-0
BK2_VOUT2
D7-5
—
D4-0
BK2_VOUT1
Name
Access
Data
Name
Access
Data
—
R/W
—
R/W
Reserved
Buck2 Output Voltage (V)
Reserved
Buck2 Output Voltage (V)
5’h00
5’h01
5’h02
5’h03
5’h04
5’h05
5’h06
5’h07
5’h08
5’h09
5’h0A
5’h0B
5’h0C
5’h0D
5’h0E
5’h0F
5’h10
5’h11
Ext Ctrl
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.5
5’h00
5’h01
5’h02
5’h03
5’h04
5’h05
5’h06
5’h07
5’h08
5’h09
5’h0A
5’h0B
5’h0C
5’h0D
5’h0E
5’h0F
5’h10
5’h11
Ext Ctrl
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.5
5’h12
5’h13
5’h14
5’h15
5’h16
5’h17
5’h18
5’h19
5’h1A–5’h1F
5’h12
5’h13
5’h14
5’h15
5’h16
5’h17
5’h18
5’h19
5’h1A–5’h1F
Reset
000
Factory Programmed Default
Reset
000
Factory Programmed Default
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LP3906 Control Registers (Continued)
BUCK 2 RAMP CONTROL REGISTER (B2RC) - 0x2B
This register allows the user to program the rate of change between the target voltages of Buck 2
D7
- - - -
D6-4
- - - -
D3-0
B2RS
R/W
Name
Access
Data
- - - -
- - - -
Reserved
Reserved
Data Code
4h’0
Ramp Rate mV/us
Instant
4h’1
1
2
4h’2
4h’3
3
4h’4
4
4h’5
5
4h’6
6
4h’7
7
4h’8
8
4h’9
9
4h’A
10
10
4h’B - 4h’F
Reset
0
010
1000
29
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LP3906 Control Registers (Continued)
BUCK FUNCTION REGISTER (BFCR) – 0x38
This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less Electro-magnetic
Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the frequency ramps up and down,
centered at 2 MHz.
20197825
D7-2
—
D1
D0
Name
Access
Data
BK_SLOMOD
R/W
BK_SSEN
R/W
—
Reserved
Buck Spread Spectrum Modulation
0 – 10 kHz triangular wave
1 – 2 kHz triangular wave
1
Spread Spectrum Function Output
0 – Disabled
1 – Enabled
0
Reset
000010
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LP3906 Control Registers (Continued)
LDO2 CONTROL REGISTER (LDO2VCR) – 0X3A
LDO1 CONTROL REGISTER (LDO1VCR) – 0X39
This register allows the user to program the output target
voltage of LDO 2.
This register allows the user to program the output target
voltage of LDO 1.
D7-5
—
D4-0
LDO2_OUT
D7-5
—
D4-0
LDO1_OUT
Name
Access
Data
Name
Access
Data
—
R/W
—
R/W
Reserved
LDO2 Output voltage (V)
Reserved
LDO1 Output voltage (V)
5’h00
5’h01
5’h02
5’h03
5’h04
5’h05
5’h06
5’h07
5’h08
5’h09
5’h0A
5’h0B
5’h0C
5’h0D
5’h0E
5’h0F
5’h10
5’h11
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.5
5’h00
5’h01
5’h02
5’h03
5’h04
5’h05
5’h06
5’h07
5’h08
5’h09
5’h0A
5’h0B
5’h0C
5’h0D
5’h0E
5’h0F
5’h10
5’h11
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.5
5’h12
5’h13
5’h14
5’h15
5’h16
5’h17
5’h18
5’h19
5’h1A–5’h1F
5’h12
5’h13
5’h14
5’h15
5’h16
5’h17
5’h18
5’h19
5’h1A–5’h1F
Reset
000
Factory Programmed Default
Reset
000
Factory Programmed Default
31
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Method 2:
Application Notes
A more conservative and recommended approach is to
choose an inductor that has saturation current rating greater
than the maximum current limit of 2375 mA.
SYSTEM CLOCK INPUT (SYNC) PIN
Pin 23 of the chip allows for a system clock input in order to
synchronize the buck converters in PWM mode. This is
useful if the user wishes to force the bucks to work synchro-
nously with the system. Otherwise, the user should tie the
pin to GND and the bucks will operate on an internal 2 MHz
clock.
Given a peak-to-peak current ripple (IPP) the inductor needs
to be at least
The signal applied to the SYNC pin must be 13 MHz as per
application processor specifications, but we can be con-
tacted to modify that specification if so desired. Upon input-
ting the 13 MHz clock signal, the bucks will scale it down and
continue to run at 2 MHz based off the 13 MHz clock.
Inductor Value Unit Description
Notes
L
SW1,2 2.2 µH SW1,2 inductor D.C.R. 70 mΩ
External Capacitors
ANALOG POWER SIGNAL ROUTING
The regulators on the LP3906 require external capacitors for
regulator stability. These are specifically designed for por-
table applications requiring minimum board space and small-
est components. These capacitors must be correctly se-
lected for good performance.
All power inputs should be tied to the main VDD source (i.e.
battery), unless the user wishes to power it from another
source. (i.e. external LDO output).
The analog VDD inputs power the internal bias and error
amplifiers, so they should be tied to the main VDD. The
analog VDD inputs must have an input voltage between 2.7
and 5.5 V, as specified on pg. 6 of the datasheet.
LDO CAPACITOR SELECTION
Input Capacitor
The other VINs (VINLDO1, VINLDO2, VIN1, VIN2) can actually
have inputs lower than 2.7V, as long as it’s higher than the
programmed output (+0.3V, to be safe).
An input capacitor is required for stability. It is recommended
that a 1.0 µF capacitor be connected between the LDO input
pin and ground (this capacitance value may be increased
without limit).
The analog and digital grounds should be tied together
outside of the chip to reduce noise coupling.
This capacitor must be located a distance of not more than 1
cm from the input pin and returned to a clean analog ground.
Any good quality ceramic, tantalum, or film capacitor may be
used at the input.
COMPONENT SELECTION
Inductors for SW1 and SW2
There are two main considerations when choosing an induc-
tor; the inductor should not saturate and the inductor current
ripple is small enough to achieve the desired output voltage
ripple. Care should be taken when reviewing the different
saturation current ratings that are specified by different
manufacturers. Saturation current ratings are typically speci-
fied at 25oC, so ratings at maximum ambient temperature of
the application should be requested from the manufacturer.
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge currents when connected to a low imped-
ance source of power (like a battery or a very large capaci-
tor). If a tantalum capacitor is used at the input, it must be
guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series
Resistance) on the input capacitor, but tolerance and tem-
perature coefficient must be considered when selecting the
capacitor to ensure the capacitance will remain approxi-
mately 1.0 µF over the entire operating temperature range.
There are two methods to choose the inductor saturation
current rating:
Method 1:
The saturation current is greater than the sum of the maxi-
mum load current and the worst case average to peak
inductor current. This can be written as follows:
Output Capacitor
The LDOs on the LP3906 are designed specifically to work
with very small ceramic output capacitors. A 1.0 µF ceramic
capacitor (temperature types Z5U, Y5V or X7R) with ESR
between 5 mΩ to 500 mΩ, are suitable in the application
circuit.
It is also possible to use tantalum or film capacitors at the
device output, COUT (or VOUT), but these are not as attrac-
tive for reasons of size and cost.
The output capacitor must meet the requirement for the
minimum value of capacitance and also have an ESR value
that is within the range 5 mΩ to 500 mΩ for stability.
IRIPPLE
:
Average to peak inductor current
IOUTMAX: Maximum load current
VIN
:
Maximum input voltage to the buck
L:
Min inductor value including worse case toler-
ances (30% drop can be considered for method 1)
Capacitor Characteristics
The LDOs are designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer. For
capacitance values in the range of 0.47 µF to 4.7 µF, ceramic
capacitors are the smallest, least expensive and have the
lowest ESR values, thus making them best for eliminating
f:
Minimum switching frequency (1.6 MHz)
Buck Output voltage
VOUT
:
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32
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Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum
capacitor with an ESR value within the stable range, it would
have to be larger in capacitance (which means bigger and
more costly) than a ceramic capacitor with the same ESR
value. It should also be noted that the ESR of a typical
tantalum will increase about 2:1 as the temperature goes
from 25˚C down to −40˚C, so some guard band must be
allowed.
Application Notes (Continued)
high frequency noise. The ESR of a typical 1.0 µF ceramic
capacitor is in the range of 20 mΩ to 40 mΩ, which easily
meets the ESR requirement for stability for the LDOs.
For both input and output capacitors, careful interpretation of
the capacitor specification is required to ensure correct de-
vice operation. The capacitor value can change greatly, de-
pending on the operating conditions and capacitor type.
In particular, the output capacitor selection should take ac-
count of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance
can vary with DC bias conditions as well as temperature and
frequency of operation. Capacitor values will also show
some decrease over time due to aging. The capacitor pa-
rameters are also dependent on the particular case size,
with smaller sizes giving poorer performance figures in gen-
eral. As an example, the graph below shows a typical graph
comparing different capacitor case sizes in a Capacitance
vs. DC Bias plot.
Input Capacitor Selection for SW1 and SW2
A ceramic input capacitor of 10 µF, 6.3V is sufficient for the
magnetic dc/dc converters. Place the input capacitor as
close as possible to the input of the device. A large value
may be used for improved input voltage filtering. The recom-
mended capacitor types are X7R or X5R. Y5V type capaci-
tors should not be used. DC bias characteristics of ceramic
capacitors must be considered when selecting case sizes
like 0805 and 0603. The input filter capacitor supplies cur-
rent to the PFET switch of the dc/dc converter in the first half
of each cycle and reduces voltage ripple imposed on the
input power source. A ceramic capacitor’s low ESR (Equiva-
lent Series Resistance) provides the best noise filtering of
the input voltage spikes due to fast current transients. A
capacitor with sufficient ripple current rating should be se-
lected. The Input current ripple can be calculated as:
The worse case is when VIN = 2VOUT
20197828
Graph Showing a Typical Variation in Capacitance vs.
DC Bias
Output Capacitor Selection for SW1, SW2
A 10 µF, 6.3V ceramic capacitor should be used on the
output of the sw1 and sw2 magnetic dc/dc converters. The
input capacitor needs to be mounted as close as possible to
the input of the device. A large value may be used for
improved input voltage filtering. The recommended capacitor
types are X7R or X5R. Y5V type capacitors should not be
used. DC bias characteristics of ceramic capacitors must be
considered when selecting case sizes like 0805 and 0603.
DC bias characteristics vary from manufacturer to manufac-
turer and DC bias curves should be requested from them
and analyzed as part of the capacitor selection process.
As shown in the graph, increasing the DC Bias condition can
result in the capacitance value that falls below the minimum
value given in the recommended capacitor specifications
table. Note that the graph shows the capacitance out of spec
for the 0402 case size capacitor at higher bias voltages. It is
therefore recommended that the capacitor manufacturers’
specifications for the nominal value capacitor are consulted
for all conditions, as some capacitor sizes (e.g. 0402) may
not be suitable in the actual application.
The ceramic capacitor’s capacitance can vary with tempera-
ture. The capacitor type X7R, which operates over a tem-
perature range of −55˚C to +125˚C, will only vary the capaci-
tance to within 15%. The capacitor type X5R has a similar
tolerance over a reduced temperature range of −55˚C to
+85˚C. Many large value ceramic capacitors, larger than
1 µF are manufactured with Z5U or Y5V temperature char-
acteristics. Their capacitance can drop by more than 50% as
the temperature varies from 25˚C to 85˚C. Therefore X7R is
recommended over Z5U and Y5V in applications where the
ambient temperature will change significantly above or be-
low 25˚C.
The output filter capacitor of the magnetic dc/dc converter
smoothes out current flow from the inductor to the load,
helps maintain a steady output voltage during transient load
changes and reduces output voltage ripple. These capaci-
tors must be selected with sufficient capacitance and suffi-
ciently low ESD to perform these functions.
The output voltage ripple is caused by the charging and
discharging of the output capacitor and also due to its ESR
and can be calculated as follows:
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
0.47 µF to 4.7 µF range.
33
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∼1.8kΩ) are determined by the capacitance of the bus. Too
large of a resistor combined with a given bus capacitance
will result in a rise time that would violate the max. rise time
specification. A too small resistor will result in a contention
with the pull-down transistor on either slave(s) or master.
Application Notes (Continued)
Voltage peak-to-peak ripple due to ESR can be expressed
as follows:
VPP–ESR = 2 x IRIPPLE x RESR
Because the VPP-C and VPP-ESR are out of phase, the rms
value can be used to get an approximate value of the peak-
to-peak ripple:
Operation without I2C Interface
Operation of the LP3906 without the I2C interface is possible
if the system can operate with default values for the LDO and
Buck regulators. (Read below: Factory programmable op-
tions). The I2C-less system must rely on the correct default
output values of the LDO and Buck converters.
Note that the output voltage ripple is dependent on the
inductor current ripple and the equivalent series resistance
of the output capacitor (RESR). The RESR is frequency de-
pendent as well as temperature dependent. The RESR
should be calculated with the applicable switching frequency
and ambient temperature.
Factory Programmable Options
The following options are EPROM programmed during final
test of the LP3906. The system designer that needs specific
options is advised to contact the local National Semiconduc-
tor sales office.
Factory programmable options
Current value
code 010 (see
Control 1 register
section)
Min
Value
Recommended
Type
Capacitor
Unit Description
Enable delay for power on
LDO1 output Ceramic, 6.3V,
capacitor X5R
µF LDO2 output Ceramic, 6.3V,
CLDO1
CLDO2
CSW1
CSW2
0.47
0.47
µF
SW1 ramp speed
SW2 ramp speed
8 mV/µs
8 mV/µs
capacitor
µF SW1 output
capacitor
X5R
The I2C Chip ID address is offered as a metal mask option.
The current value equals 0x60.
10.0
10.0
Ceramic, 6.3V,
X5R
µF SW2 output
capacitor
Ceramic, 6.3V,
X5R
I2C Pullup Resistor
Both I2C_SDA and I2C_SCL terminals need to have pullup
resistors connected to VINLDO12 or to the power supply of
the I2C master. The values of the pull-up resistors (typ.
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34
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shows the operational area that may exhibit this increased
output ripple. If the application is expected to be operated in
the area of concern AND have a static load current of the
transition current value, the user can avoid the possible
noise increase by invoking the components’ “Force PWM
mode”.
Application Notes (Continued)
MODE BOUNCE
PFM-PWM transition at low load current.
To improve efficiency at lower load currents LP3906 buck
converters employ an automatically invoked PFM mode for
the low load operation. The PFM mode operates with a much
lower value quiescent current (IQ) than the PWM mode of
operation that is used in the higher load currents.
LP3906 Buck Converter
VOUT vs VIN Operating Range
during PFM-PWM-PPM Transition
As shown in the datasheet section about SW operation,
there is a DC voltage difference between the two modes of
operation, with Vout PFM being typically 1.2% higher than
Vout PWM. So there is a DC voltage level transition and
some associated dynamic perturbation at the mode transi-
tion point.
The transition between the two modes of operation has an
associated hysterisis in the transition current value, That is,
the transition point for increasing current (PFM to PWM) is at
a higher value that the decreasing current (PWM to PFM).
This hysterisis is to ensure that in the event that the load
current values equals the PFM PWM transition value, the
device will not make multiple transitions between modes;
this reduces the noise at this load by eliminating multiple
transitions between modes (also known as mode bounce).
Under some conditions of high Vin and Low Vout the hyster-
sis value is reduced and some amount of mode bounce can
occur. Under these conditions, the regulator still maintains
DC regulation, however the output ripple is more pro-
nounced. Refer to the attached Vout vs Vin chart below that
20197865
35
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Power dissipation of Buck1
PBuck1 = PIN – POUT
Application Notes (Continued)
High Vin-High Load Operation
=
VoutBuck1* IoutBuck1 * (1 -η1) / η1 [V*A]
η1 = efficiency of buck 1
Power dissipation of Buck2
Additional information is provided when the IC is operated at
extremes of Vin and regulator loads. These are described in
terms of the Junction temperature and, Buck output ripple
management.
PBuck2 = PIN – POUT
=
VoutBuck2 * IoutBuck2 * (1 - η2) / η2 [V*A]
η2 = efficiency of buck 2
η is the efficiency for the specific condition taken from effi-
ciency graphs.
Junction Temperature
The maximum junction temperature TJ-MAX-OP of 125oC of
the IC package.
The following equations demonstrate junction temperature
determination, ambient temperature TA-MAX and Total chip
power must be controlled to keep TJ below this maximum:
Buck Output Ripple Management
If Vin and ILoad increase, the output ripple associated with
the Buck Regulators also increases. The figure below shows
the safe operating area. To ensure operation in the area of
concern it is recommended that the system designer circum-
vents the output ripple issues to install schottky diodes on
the Bucks(s) that are expected to perform under these ex-
treme corner conditions.
TJ-MAX-OP = TA-MAX + (θJA) [ ˚C/ Watt] * (PD-MAX)
[Watts]
Total IC power dissipation PD-MAX is the sum of the indi-
vidual power dissipation of the four regulators plus a minor
amount for chip overhead. Chip overhead is Bias, TSD &
LDO analog.
(Schottky diodes are recommended to reduce the output
ripple if the system requirements include this shaded area of
PD-MAX = PLDO1 + PLD02 + PBUCK1 + PBUCK2 + (0.0001A *
Vin) [Watts].
>
>
operation. Vin 5.2 V and Iload 1.24 A)
Power dissipation of LDO1
PLDO1 = (VinLDO1- VoutLDO1) * IoutLDO1 [V*A]
Power dissipation of LDO2
PLDO2 = (VinLDO2 - VoutLDO2) * IoutLDO2 [V*A]
LP3906 Buck Converter
VIN vs ILOAD Operating Ranges
20197864
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36
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underneath the thermal land. Based on thermal analysis of
the LLP package, the junction-to-ambient thermal resistance
(θJA) can be improved by a factor of two when the die attach
pad of the LLP package is soldered directly onto the PCB
with thermal land and thermal vias, as opposed to an alter-
native with no direct soldering to a thermal land. Typical pitch
and outer diameter for thermal vias are 1.27mm and 0.33mm
respectively. Typical copper via barrel plating is 1oz, al-
though thicker copper may be used to further improve ther-
mal performance. The LP3906 die attach pad is connected
to the substrate of the IC and therefore, the thermal land and
vias on the PCB board need to be connected to ground
(GND pin).
Thermal Performance of the LLP
Package
The LP3906 is a monolithic device with integrated power
FETs. For that reason, it is important to pay special attention
to the thermal impedance of the LLP package and to the
PCB layout rules in order to maximize power dissipation of
the LLP package.
The LLP package is designed for enhanced thermal perfor-
mance and features an exposed die attach pad at the bottom
center of the package that creates a direct path to the PCB
for maximum power dissipation. Compared to the traditional
leaded packages where the die attach pad is embedded
inside the molding compound, the LLP reduces one layer in
the thermal path.
For more information on board layout techniques, refer to
Application Note AN–1187 “Leadless Lead frame Package
(LLP).” on http://www.national.com This application note also
discusses package handling, solder stencil and the assem-
bly process.
The thermal advantage of the LLP package is fully realized
only when the exposed die attach pad is soldered down to a
thermal land on the PCB board with thermal vias planted
37
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Physical Dimensions inches (millimeters) unless otherwise noted
5 X 4 X 0.8 mm 24-Pin LLP Package
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances
and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at:
www.national.com/quality/green.
Lead free products are RoHS compliant.
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Support Center
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Fax: +49 (0) 180-530 85 86
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Fax: 81-3-5639-7507
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