LP3963ESX-2.5/NOPB_技术文档

May 2003

LP3963/LP3966

3A Fast Ultra Low Dropout Linear Regulators

General Description

Features

n Ultra low dropout voltage

The LP3963/LP3966 series of fast ultra low-dropout linear

regulators operate from a +2.5V to +7.0V input supply. Wide

range of preset output voltage options are available. These

ultra low dropout linear regulators respond very quickly to

step changes in load which makes them suitable for low

voltage microprocessor applications. The LP3963/LP3966

are developed on a CMOS process which allows low quies-

cent current operation independent of output load current.

This CMOS process also allows the LP3963/LP3966 to op-

erate under extremely low dropout conditions.

n Low ground pin current

n Load regulation of 0.06%

n 15µA quiescent current in shutdown mode

n Guaranteed output current of 3A DC

n Available in TO-263 and TO-220 packages

n Output voltage accuracy 1.5%

n Error flag indicates output status (LP3963)

n Sense option improves load regulation (LP3966)

n Minimum output capacitor requirements

n Overtemperature/overcurrent protection

n −40˚C to +125˚C junction temperature range

Dropout Voltage: Ultra low dropout voltage; typically 80mV

at 300mA load current and 800mV at 3A load current.

Ground Pin Current: Typically 6mA at 3A load current.

Shutdown Mode: Typically 15µA quiescent current when

the shutdown pin is pulled low.

Applications

n Microprocessor power supplies

n GTL, GTL+, BTL, and SSTL bus terminators

n Power supplies for DSPs

n SCSI terminator

Error Flag: Error flag goes low when the output voltage

drops 10% below nominal value (for LP3963).

SENSE: Sense pin improves regulation at remote loads.

(For LP3966)

n Post regulators

n High efficiency linear regulators

n Battery chargers

Precision Output Voltage: Multiple output voltage options

are available ranging from 1.2V to 5.0V and adjustable

(LP3966), with a guaranteed accuracy of 1.5% at room

temperature, and 3.0% over all conditions (varying line,

load, and temperature).

n Other battery powered applications

Typical Application Circuits

10126701

*SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See applications

section for more information.

**

See Application Hints

DS101267

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Typical Application Circuits (Continued)

10126734

*SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See applications section

for more information.

**

See Application Hints

Block Diagram LP3963

10126703

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2

Block Diagram LP3966

10126729

Block Diagram LP3966-ADJ

10126735

Connection Diagrams

10126705

10126706

Top View

TO220-5 Package

Bent, Staggered Leads

TO263-5 Package

3

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Pin Description for TO220-5 and TO263-5 Packages

LP3963

LP3966

#

Name

SD

Function

Shutdown

Name

SD

Function

Shutdown

1

2

3

4

5

V_IN

Input Supply

Ground

V_IN

Input Supply

GND

V_OUT

ERROR

GND

Ground

Output Voltage

ERROR Flag

V_OUT

Output Voltage

Remote Sense

Pin/Output Adjust Pin

SENSE/ADJ

Ordering Information

10126731

Package Type Designator is "T" for TO220 package, and "S" for TO263 package.

TABLE 1. Package Marking and Ordering Information

Output

Voltage

5.0

Description

(Current, Option)

Package

Type

Order Number

LP3963ES-5.0

Package Marking

Supplied As:

Rail

3A, Error Flag

TO263-5

LP3963ES-5.0

LP3963ESX-5.0

LP3963ES-3.3

LP3963ES-2.5

LP3963ES-1.8

LP3966ES-5.0

LP3966ESX-5.0

LP3966ES-3.3

LP3966ES-2.5

LP3966ES-1.8

LP3966ES-ADJ

LP3963ET-5.0

LP3963ET-3.3

LP3963ET-2.5

LP3963ET-1.8

5.0

LP3963ESX-5.0

LP3963ES-3.3

LP3963ESX-3.3

LP3963ES-2.5

LP3963ESX-2.5

LP3963ES-1.8

LP3963ESX-1.8

LP3966ES-5.0

LP3966ESX-5.0

LP3966ES-3.3

LP3966ESX-3.3

LP3966ES-2.5

LP3966ESX-2.5

LP3966ES-1.8

LP3966ESX-1.8

LP3966ES-ADJ

LP3966ESX-ADJ

LP3963ET-5.0

LP3963ET-3.3

LP3963ET-2.5

LP3963ET-1.8

3A, Error Flag

3A, SENSE

3A, ADJ

TO263-5

TO220-5

Tape and Reel

Rail

3.3

Tape and Reel

Rail

2.5

Tape and Reel

Rail

1.8

Tape and Reel

Rail

5.0

Tape and Reel

Rail

3.3

Tape and Reel

Rail

2.5

Tape and Reel

Rail

1.8

Tape and Reel

Rail

ADJ

5.0

3A, ADJ

Tape and Reel

Rail

3A, Error Flag

3.3

Rail

2.5

Rail

1.8

Rail

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4

Ordering Information (Continued)

TABLE 1. Package Marking and Ordering Information (Continued)

Output

Voltage

5.0

Description

(Current, Option)

Package

Type

Order Number

LP3966ET-5.0

Package Marking

LP3966ET-5.0

LP3966ET-3.3

LP3966ET-2.5

LP3966ET-1.8

LP3966ET-ADJ

Supplied As:

Rail

3A, SENSE

TO220-5

3.3

LP3966ET-3.3

LP3966ET-2.5

LP3966ET-1.8

LP3966ET-ADJ

3A, SENSE

3A, ADJ

TO220-5

Rail

2.5

1.8

ADJ

5

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

I_OUT(Survival)

Short Circuit Protected

V_IN+0.3V

Maximum Voltage for ERROR

Maximum Voltage for SENSE Pin

V_OUT+0.3V

Storage Temperature Range

Lead Temperature

−65˚C to +150˚C

Operating Ratings

Input Supply Voltage (Operating),

(Note 12)

(Soldering, 5 sec.)

260˚C

2 kV

ESD Rating (Note 3)

Power Dissipation (Note 2)

Input Supply Voltage (Survival)

Shutdown Input Voltage

(Survival)

2.5V to 7.0V

Internally Limited

−0.3V to +7.5V

Shutdown Input Voltage

(Operating)

−0.3V to V_IN+0.3V

3A

Maximum Operating Current (DC)

Operating Junction Temp. Range

−0.3V to V_IN+0.3V

−0.3V to +7.5V

−40˚C to +125˚C

Output Voltage (Survival), (Note

6), (Note 7)

Electrical Characteristics

LP3963/LP3966

Limits in standard typeface are for T_J= 25˚C, and limits in boldface type apply over the full operating temperature range.

Unless otherwise specified: V_IN= V_O(NOM)+ 1.5V, I_L= 10 mA, C_OUT=33µF, V_SD= V_IN-0.3V.

Symbol

Parameter

Output Voltage

Conditions

Typ

(Note 4)

LP3963/6 (Note 5)

Units

Min

Max

<

V_OUT+1.5V V_IN7.0V

-1.5

+1.5

<

V_O

Tolerance

10 mA I_L3A

0

%

-3.0

+3.0

(Note 8)

Adjust Pin Voltage (ADJ

version)

10 mA ≤ I_L≤ 3A

V_OUT+1.5V ≤ V_IN≤ 7.0V

1.198

1.234

V_ADJ

1.216

V

1.180

1.253

<

∆V _OL

Output Voltage Line

Regulation (Note 8)

Output Voltage Load

Regulation

V_OUT+1.5V V_IN

0.02

0.06

0.01

%

7.0V

<

∆V_O/ ∆I_OUT

10 mA I_L3A

%

(Note 8)

V_IN- V_OUT

I_L= 300 mA

I_L= 3A

80

800

5

100

120

1000

1200

9

Dropout Voltage

(Note 10)

mV

I_L= 300 mA

I_L= 3A

10

Ground Pin Current In

Normal Operation Mode

I_GND

mA

µA

6

14

15

I_GND

Ground Pin Current In

Shutdown Mode

(Note 11)

V_SD≤ 0.2V

15

25

75

I_O(PK)

Peak Output Current

(Note 2)

4.5

5.5

4

A

3.5

SHORT CIRCUIT PROTECTION

I_SCShort Circuit Current

OVER TEMPERATURE PROTECTION

Tsh(t)

Shutdown Threshold

Thermal Shutdown

Hysteresis

165

10

˚C

Tsh(h)

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Electrical Characteristics

LP3963/LP3966 ^(Continued)

Limits in standard typeface are for T_J= 25˚C, and limits in boldface type apply over the full operating temperature range.

Unless otherwise specified: V_IN= V_O(NOM)+ 1.5V, I_L= 10 mA, C_OUT=33µF, V_SD= V_IN-0.3V.

Symbol

Parameter

Conditions

Typ

LP3963/6 (Note 5)

Units

(Note 4)

Min

Max

0.2

SHUTDOWN INPUT

Output = High

V_IN

0

V_IN–0.3

V_SDT

Shutdown Threshold

V

Output = Low

I_L= 3A

T_dOFF

Turn-off delay

Turn-on delay

SD Input Current

20

25

1

µs

nA

T_dON

I_L= 3A

I_SD

V_SD= V_IN

ERROR FLAG

V_T

V_TH

V_EF(Sat)

Td

Threshold

(Note 9)

10

5

2

16

8

%

Threshold Hysteresis

Error Flag Saturation

Flag Reset Delay

Error Flag Pin Leakage

Current

(Note 9)

I_sink= 100µA

0.02

1

0.1

V

µs

nA

I_lk

1

I_max

Error Flag Pin Sink

Current

V_Error= 0.5V

1

mA

dB

AC PARAMETERS

V_IN= V_OUT+ 1.5V

C_OUT= 100uF

60

40

V_OUT= 3.3V

PSRR

Ripple Rejection

V_IN= V_OUT+ 0.3V

C_OUT= 100uF

V_OUT= 3.3V

ρ_n(l/f

Output Noise Density

f = 120Hz

0.8

150

100

µV

BW = 10Hz – 100kHz

BW = 300Hz – 300kHz

Output Noise Voltage

(rms)

e_n

µV (rms)

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is

intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see Electrical Characteristics. The

guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed

test conditions.

Note 2: At elevated temperatures, devices must be derated based on package thermal resistance. The devices in TO220 package must be derated at θ = 50˚C/W

jA

2

(with 0.5in , 1oz. copper area), junction-to-ambient (with no heat sink). The devices in the TO263 surface-mount package must be derated at θ = 60˚C/W (with

jA

2

0.5in , 1oz. copper area), junction-to-ambient. See Application Hints.

Note 3: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 4: Typical numbers are at 25˚C and represent the most likely parametric norm.

Note 5: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control

(SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 6: If used in a dual-supply system where the regulator load is returned to a negative supply, the LP396X output must be diode-clamped to ground.

Note 7: The output PMOS structure contains a diode between the V and V

terminals. This diode is normally reverse biased. This diode will get forward biased

OUT

IN

if the voltage at the output terminal is forced to be higher than the voltage at the input terminal. This diode can typically withstand 200mA of DC current and 1Amp

of peak current.

Note 8: Output voltage line regulation is defined as the change in output voltage from the nominal value due to change in the input line voltage. Output voltage load

regulation is defined as the change in output voltage from the nominal value due to change in load current. The line and load regulation specification contains only

the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification.

Note 9: Error Flag threshold and hysteresis are specified as percentage of regulated output voltage. See Application Hints.

Note 10: Dropout voltage is defined as the minimum input to output differential voltage at which the output drops 2% below the nominal value. Dropout voltage

specification applies only to output voltages of 2.5V and above. For output voltages below 2.5V, the drop-out voltage is nothing but the input to output differential,

since the minimum input voltage is 2.5V.

Note 11: This specification has been tested for −40˚C ≤ T ≤ 85˚C since the temperature rise of the device is negligible under shutdown conditions.

J

Note 12: The minimum operating value for V is equal to either [V

+ V

] or 2.5V, whichever is greater.

DROPOUT

IN

OUT(NOM)

7

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Typical Performance Characteristics Unless otherwise specified, V_IN= V_O(NOM)+ 1.5V, V_OUT

=

2.5V, C_OUT= 33µF, I_OUT= 10mA, C_IN= 68µF, V_SD= V_IN, and T_A= 25˚C.

Drop-Out Voltage Vs Temperature for Different Load

Currents

Drop-Out Voltage Vs Temperature (I_L= 100mA, 1A, V_OUT

= 2.5V, Dropout at 50mV Down)

10126709

10126710

Ground Pin Current Vs Input Voltage (V_SD=V_IN

)

Ground Pin Current Vs Input Voltage (V_SD=100mV)

10126711

10126715

Ground Current Vs Temperature (V_SD=V_IN

)

Ground Current Vs Temperature (V_SD=0V)

10126718

10126712

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Typical Performance Characteristics Unless otherwise specified, V_IN= V_O(NOM)+ 1.5V, V_OUT= 2.5V,

C_OUT= 33µF, I_OUT= 10mA, C_IN= 68µF, V_SD= V_IN, and T_A= 25˚C. (Continued)

Ground Pin Current Vs Shutdown Pin Voltage

Input Voltage Vs Output Voltage

10126716

10126717

Output Noise Density, V_OUT= 2.5V

Output Noise Density, V_OUT= 5V

10126713

10126714

Load Transient Response

Ripple Rejection vs Frequency

10126737

10126738

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Typical Performance Characteristics Unless otherwise specified, V_IN= V_O(NOM)+ 1.5V, V_OUT= 2.5V,

C_OUT= 33µF, I_OUT= 10mA, C_IN= 68µF, V_SD= V_IN, and T_A= 25˚C. (Continued)

δV_OUTvs Temperature

Noise Density V_IN= 3.5V, V_OUT= 2.5V, I_L= 10 mA

10126739

10126740

Line Transient Response

10126741

10126742

Line Transient Response (I_OUT= 3.0A)

10126743

10126744

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Application Hints

V_INRESTRICTIONS FOR PROPER START-UP

because it forms a zero to provide phase lead which is

required for loop stability. The ESR must fall within the

specified range:

Because the LP396X devices use on-chip CMOS logic for

analog trimming of the output voltage, care must be taken

not to apply an input voltage which can allow this logic to

shift into random undefined logic states, as this can ad-

versely affect the regulated output voltage. This will most

likely occur if an input voltage between about 50mV and

200mV is applied to V_INfor a significant amount of time

(more than several seconds). To prevent misoperation, en-

sure that V_INis below 50mV before start-up is initiated. This

problem can occur in systems with a backup battery using

reverse-biased "blocking" diodes which may allow enough

leakage current to flow into the V_INnode to raise it’s voltage

slightly above ground when the main power is removed.

Using low leakage diodes or a resistive pull down can pre-

vent the voltage at V_INfrom rising above the sensitive

threshold. Large bulk capacitors connected to V_INmay also

cause a start-up problem if they do not discharge fully before

re-start is initiated (but only if V_INis allowed to fall below 1V).

A resistor connected across the capacitor will allow it to

discharge more quickly. It should be noted that the probabil-

ity of a "false start" caused by incorrect logic states is ex-

tremely low .

0.2Ω ≤ C_OUTESR ≤ 5Ω

The lower limit of 200 mΩ means that ceramic capacitors are

not suitable for use as LP3963/6 output capacitors (but can

be used on the input). Some ceramic capacitance can be

used on the output if the total equivalent ESR is in the stable

range: when using a 100 µF Tantalum as the output capaci-

tor, approximately 3 µF of ceramic capacitance can be ap-

plied before stability becomes marginal.

IMPORTANT: The output capacitor must meet the require-

ments for minimum amount of capacitance and also have an

appropriate ESR value over the full temperature range of the

application to assure stability (see Capacitor Characteristics

Section).

SELECTING A CAPACITOR

It is important to note that capacitance tolerance and varia-

tion with temperature must be taken into consideration when

selecting a capacitor so that the minimum required amount

of capacitance is provided over the full operating tempera-

ture range. In general, a good Tantalum capacitor will show

very little capacitance variation with temperature, but a ce-

ramic may not be as good (depending on dielectric type).

Aluminum electrolytics also typically have large temperature

variation of capacitance value.

EXTERNAL CAPACITORS

Like any low-dropout regulator, external capacitors are re-

quired to assure stability. these capacitors must be correctly

selected for proper performance.

Equally important to consider is a capacitor’s ESR change

with temperature: this is not an issue with ceramics, as their

ESR is extremely low. However, it is very important in Tan-

talum and aluminum electrolytic capacitors. Both show in-

creasing ESR at colder temperatures, but the increase in

aluminum electrolytic capacitors is so severe they may not

be feasible for some applications (see Capacitor Character-

istics Section).

INPUT CAPACITOR: The LP3963/6 requires a low source

impedance to maintain regulator stability because the inter-

nal bias circuitry is connected directly to V_IN. The input

capacitor must be located less than 1 cm from the LP3963/6

device and connected directly to the input and ground pins

using traces which have no other currents flowing through

them (see PCB Layout section).

The minimum allowable input capacitance for a given appli-

cation depends on the type of the capacitor and ESR

(equivalent series resistance). A lower ESR capacitor allows

the use of less capacitance, while higher ESR types (like

aluminum electrolytics) require more capacitance.

CAPACITOR CHARACTERISTICS

CERAMIC: For values of capacitance in the 10 to 100 µF

range, ceramics are usually larger and more costly than

tantalums but give superior AC performance for bypassing

high frequency noise because of very low ESR (typically less

than 10 mΩ). However, some dielectric types do not have

good capacitance characteristics as a function of voltage

and temperature.

The lowest value of input capacitance that can be used for

stable full-load operation is 68 µF (assuming it is a ceramic

or low-ESR Tantalum with ESR less than 100 mΩ).

To determine the minimum input capacitance amount and

ESR value, an approximation which should be used is:

Z5U and Y5V dielectric ceramics have capacitance that

drops severely with applied voltage. A typical Z5U or Y5V

capacitor can lose 60% of its rated capacitance with half of

the rated voltage applied to it. The Z5U and Y5V also exhibit

a severe temperature effect, losing more than 50% of nomi-

nal capacitance at high and low limits of the temperature

range.

C_INESR (mΩ) / C_IN(µF) ≤ 1.5

This shows that input capacitors with higher ESR values can

be used if sufficient total capacitance is provided. Capacitor

types (aluminum, ceramic, and tantalum) can be mixed in

parallel, but the total equivalent input capacitance/ESR must

be defined as above to assure stable operation.

X7R and X5R dielectric ceramic capacitors are strongly rec-

ommended if ceramics are used, as they typically maintain a

capacitance range within 20% of nominal over full operat-

ing ratings of temperature and voltage. Of course, they are

typically larger and more costly than Z5U/Y5U types for a

given voltage and capacitance.

IMPORTANT: The input capacitor must maintain its ESR and

capacitance in the "stable range" over the entire temperature

range of the application to assure stability (see Capacitor

Characteristics Section).

OUTPUT CAPACITOR: An output capacitor is also required

for loop stability. It must be located less than 1 cm from the

LP3963/6 device and connected directly to the output and

ground pins using traces which have no other currents flow-

ing through them (see PCB Layout section).

TANTALUM: Solid Tantalum capacitors are recommended

for use on the output because their typical ESR is very close

to the ideal value required for loop compensation. They also

work well as input capacitors if selected to meet the ESR

requirements previously listed.

The minimum value of the output capacitance that can be

used for stable full-load operation is 33 µF, but it may be

increased without limit. The output capacitor’s ESR is critical

11

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If RFI/EMI noise is present on the input side of the LP396X

regulator (such as applications where the input source

comes from the output of a switching regulator), good ce-

ramic bypass capacitors must be used at the input pin of the

LP396X.

Application Hints (Continued)

Tantalums also have good temperature stability: a good

quality Tantalum will typically show a capacitance value that

varies less than 10-15% across the full temperature range of

125˚C to −40˚C. ESR will vary only about 2X going from the

high to low temperature limits.

If a load is connected to the LP396X output which switches

at high speed (such as a clock), the high-frequency current

pulses required by the load must be supplied by the capaci-

tors on the LP396X output. Since the bandwidth of the

regulator loop is less than 100 kHz, the control circuitry

cannot respond to load changes above that frequency. The

means the effective output impedance of the LP396X at

frequencies above 100 kHz is determined only by the output

capacitor(s).

The increasing ESR at lower temperatures can cause oscil-

lations when marginal quality capacitors are used (if the ESR

of the capacitor is near the upper limit of the stability range at

room temperature).

ALUMINUM: This capacitor type offers the most capaci-

tance for the money. The disadvantages are that they are

larger in physical size, not widely available in surface mount,

and have poor AC performance (especially at higher fre-

quencies) due to higher ESR and ESL.

In applications where the load is switching at high speed, the

output of the LP396X may need RF isolation from the load. It

is recommended that some inductance be placed between

the LP396X output capacitor and the load, and good RF

bypass capacitors be placed directly across the load.

Compared by size, the ESR of an aluminum electrolytic is

higher than either Tantalum or ceramic, and it also varies

greatly with temperature. A typical aluminum electrolytic can

exhibit an ESR increase of as much as 50X when going from

25˚C down to −40˚C.

PCB layout is also critical in high noise environments, since

RFI/EMI is easily radiated directly into PC traces. Noisy

circuitry should be isolated from "clean" circuits where pos-

sible, and grounded through a separate path. At MHz fre-

quencies, ground planes begin to look inductive and RFI/

EMI can cause ground bounce across the ground plane.

It should also be noted that many aluminum electrolytics only

specify impedance at a frequency of 120 Hz, which indicates

they have poor high frequency performance. Only aluminum

electrolytics that have an impedance specified at a higher

frequency (between 20 kHz and 100 kHz) should be used for

the LP396X. Derating must be applied to the manufacturer’s

ESR specification, since it is typically only valid at room

temperature.

In multi-layer PCB applications, care should be taken in

layout so that noisy power and ground planes do not radiate

directly into adjacent layers which carry analog power and

ground.

Any applications using aluminum electrolytics should be

thoroughly tested at the lowest ambient operating tempera-

ture where ESR is maximum.

OUTPUT ADJUSTMENT

An adjustable output device has output voltage range of

1.215V to 5.1V. To obtain a desired output voltage, the

following equation can be used with R1 always a 10kΩ

resistor.

PCB LAYOUT

Good PC layout practices must be used or instability can be

induced because of ground loops and voltage drops. The

input and output capacitors must be directly connected to the

input, output, and ground pins of the LP3963/6 using traces

which do not have other currents flowing in them Kelvin

connect).

For output stability, C_Fmust be between 68pF and 100pF.

The best way to do this is to lay out C_INand C_OUTnear the

device with short traces to the V_IN, V_OUT, and ground pins.

The regulator ground pin should be connected to the exter-

nal circuit ground so that the regulator and its capacitors

have a "single point ground".

OUTPUT NOISE

Noise is specified in two ways-

Spot Noise or Output noise density is the RMS sum of all

noise sources, measured at the regulator output, at a spe-

cific frequency (measured with a 1Hz bandwidth). This type

of noise is usually plotted on a curve as a function of fre-

quency.

It should be noted that stability problems have been seen in

applications where "vias" to an internal ground plane were

used at the ground points of the LP3963/6 IC and the input

and output capacitors. This was caused by varying ground

potentials at these nodes resulting from current flowing

through the ground plane. Using a single point ground tech-

nique for the regulator and it’s capacitors fixed the problem.

Total output Noise or Broad-band noise is the RMS sum

of spot noise over a specified bandwidth, usually several

decades of frequencies.

Since high current flows through the traces going into V_IN

and coming from V_OUT, Kelvin connect the capacitor leads to

these pins so there is no voltage drop in series with the input

and output capacitors.

Attention should be paid to the units of measurement. Spot

√

noise is measured in units µV/ Hz or nV/ Hz and total output

noise is measured in µV(rms).

The primary source of noise in low-dropout regulators is the

internal reference. In CMOS regulators, noise has a low

frequency component and a high frequency component,

which depend strongly on the silicon area and quiescent

current. Noise can be reduced in two ways: by increasing the

transistor area or by increasing the current drawn by the

internal reference. Increasing the area will decrease the

chance of fitting the die into a smaller package. Increasing

the current drawn by the internal reference increases the

total supply current (ground pin current). Using an optimized

RFI/EMI SUSCEPTIBILITY

RFI (radio frequency interference) and EMI (electromagnetic

interference) can degrade any integrated circuit’s perfor-

mance because of the small dimensions of the geometries

inside the device. In applications where circuit sources are

present which generate signals with significant high fre-

>

quency energy content ( 1 MHz), care must be taken to

ensure that this does not affect the IC regulator.

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12

ERROR FLAG OPERATION

Application Hints (Continued)

The LP3963/LP3966 produces a logic low signal at the Error

Flag pin when the output drops out of regulation due to low

input voltage, current limiting, or thermal limiting. This flag

has a built in hysteresis. The timing diagram in Figure 1

shows the relationship between the ERROR flag and the

output voltage. In this example, the input voltage is changed

to demonstrate the functionality of the Error Flag.

trade-off of ground pin current and die size, LP3963/LP3966

achieves low noise performance and low quiescent current

operation.

The total output noise specification for LP3963/LP3966 is

presented in the Electrical Characteristics table. The Output

noise density at different frequencies is represented by a

curve under typical performance characteristics.

The internal Error flag comparator has an open drain output

stage. Hence, the ERROR pin should be pulled high through

a pull up resistor. Although the ERROR flag pin can sink

current of 1mA, this current is energy drain from the input

supply. Hence, the value of the pull up resistor should be in

the range of 10kΩ to 1MΩ. The ERROR pin must be

connected to ground if this function is not used. It should

also be noted that when the shutdown pin is pulled low, the

ERROR pin is forced to be invalid for reasons of saving

power in shutdown mode.

SHORT-CIRCUIT PROTECTION

The LP3963 and LP3966 is short circuit protected and in the

event of a peak over-current condition, the short-circuit con-

trol loop will rapidly drive the output PMOS pass element off.

Once the power pass element shuts down, the control loop

will rapidly cycle the output on and off until the average

power dissipation causes the thermal shutdown circuit to

respond to servo the on/off cycling to a lower frequency.

Please refer to the section on thermal information for power

dissipation calculations.

10126707

FIGURE 1. Error Flag Operation

SENSE PIN

tance. For example, in the case of a 3.3V output, if the trace

resistance is 100mΩ, the voltage at the remote load will be

3V with 3A of load current, I_LOAD. The LP3966 regulates the

voltage at the sense pin. Connecting the sense pin to the

remote load will provide regulation at the remote load, as

shown in Figure 2. If the sense option pin is not required, the

sense pin must be connected to the V_OUTpin.

In applications where the regulator output is not very close to

the load, LP3966 can provide better remote load regulation

using the SENSE pin. Figure 2 depicts the advantage of the

SENSE option. LP3963 regulates the voltage at the output

pin. Hence, the voltage at the remote load will be the regu-

lator output voltage minus the drop across the trace resis-

13

www.national.com

Application Hints (Continued)

10126708

FIGURE 2. Improving remote load regulation using LP3966

SHUTDOWN OPERATION

where I_GNDis the operating ground current of the device

(specified under Electrical Characteristics).

A CMOS Logic level signal at the shutdown ( SD) pin will

turn-off the regulator. Pin SD must be actively terminated

through a 10kΩ pull-up resistor for a proper operation. If this

pin is driven from a source that actively pulls high and low

(such as a CMOS rail to rail comparator), the pull-up resistor

is not required. This pin must be tied to Vin if not used.

The maximum allowable temperature rise (T_Rmax) depends

on the maximum ambient temperature (T_Amax) of the appli-

cation, and the maximum allowable junction temperature

(T_Jmax):

T_Rmax= T_Jmax− T_Amax

The maximum allowable value for junction to ambient Ther-

mal Resistance, θ_JA, can be calculated using the formula:

θ_JA= T_Rmax/ P_D

LP3963 and LP3966 are available in TO-220 and TO-263

packages. The thermal resistance depends on amount of

copper area or heat sink, and on air flow. If the maximum

allowable value of θ_JAcalculated above is ≥ 60 ˚C/W for

TO-220 package and ≥ 60 ˚C/W for TO-263 package no

heatsink is needed since the package can dissipate enough

heat to satisfy these requirements. If the value for allowable

θ_JAfalls below these limits, a heat sink is required.

DROPOUT VOLTAGE

The dropout voltage of a regulator is defined as the minimum

input-to-output differential required to stay within 2% of the

nominal output voltage. The LP3963/LP3966 use an internal

MOSFET with an Rds(on) of 240mΩ (typically). For CMOS

LDOs, the dropout voltage is the product of the load current

and the Rds(on) of the internal MOSFET.

REVERSE CURRENT PATH

The internal MOSFET in LP3963 and LP3966 has an inher-

ent parasitic diode. During normal operation, the input volt-

age is higher than the output voltage and the parasitic diode

is reverse biased. However, if the output is pulled above the

input in an application, then current flows from the output to

the input as the parasitic diode gets forward biased. The

output can be pulled above the input as long as the current

in the parasitic diode is limited to 200mA continuous and 1A

peak.

HEATSINKING TO-220 PACKAGE

The thermal resistance of a TO220 package can be reduced

by attaching it to a heat sink or a copper plane on a PC

board. If a copper plane is to be used, the values of θ_JAwill

be same as shown in next section for TO263 package.

The heatsink to be used in the application should have a

heatsink to ambient thermal resistance,

POWER DISSIPATION/HEATSINKING

θ_HA≤ θ_JA− θ_CH− θ_JC

.

LP3963 and LP3966 can deliver a continuous current of 3A

over the full operating temperature range. A heatsink may be

required depending on the maximum power dissipation and

maximum ambient temperature of the application. Under all

possible conditions, the junction temperature must be within

the range specified under operating conditions. The total

power dissipation of the device is given by:

In this equation, θ_CHis the thermal resistance from the case

to the surface of the heat sink and θ_JCis the thermal resis-

tance from the junction to the surface of the case. θ_JCis

about 3˚C/W for a TO220 package. The value for θ_CHde-

pends on method of attachment, insulator, etc. θ_CHvaries

between 1.5˚C/W to 2.5˚C/W. If the exact value is unknown,

2˚C/W can be assumed.

P_D= (V_IN−V_OUT)I_OUT+ (V_IN)I_GND

www.national.com

14

As shown in the figure, increasing the copper area beyond 1

square inch produces very little improvement. The minimum

value for θ_JAfor the TO-263 package mounted to a PCB is

32˚C/W.

Application Hints (Continued)

HEATSINKING TO-263 PACKAGE

The TO-263 package uses the copper plane on the PCB as

a heatsink. The tab of these packages are soldered to the

copper plane for heat sinking. Figure 3 shows a curve for the

Figure 4 shows the maximum allowable power dissipation

for TO-263 packages for different ambient temperatures,

assuming θ_JAis 35˚C/W and the maximum junction tempera-

ture is 125˚C.

θ

_JAof TO-263 package for different copper area sizes, using

a typical PCB with 1 ounce copper and no solder mask over

the copper area for heat sinking.

10126733

10126732

FIGURE 4. Maximum power dissipation vs ambient

temperature for TO-263 package

FIGURE 3. θ_JAvs Copper (1 Ounce) Area for TO-263

package

15

www.national.com

Physical Dimensions inches (millimeters)

unless otherwise noted

TO220 5-lead, Molded, Stagger Bend Package (TO220-5)

NS Package Number T05D

For Order Numbers, refer to the “Ordering Information” section of this document.

www.national.com

16

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

TO263 5-Lead, Molded, Surface Mount Package (TO263-5)

NS Package Number TS5B

For Order Numbers, refer to the “Ordering Information” section of this document.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Americas Customer

Support Center

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Europe Customer Support Center

Fax: +49 (0) 180-530 85 86

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Support Center

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Fax: 81-3-5639-7507

Email: new.feedback@nsc.com

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www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


型号：	LP3963ESX-2.5/NOPB
厂家：	National Semiconductor
描述：	IC VREG 2.5 V FIXED POSITIVE LDO REGULATOR, 1.2 V DROPOUT, PSSO5, PLASTIC, TO-263, 5 PIN, Fixed Positive Single Output LDO Regulator 稳压器
文件：	总17页 (文件大小：388K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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