LP3971 [NSC]
POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS; 电源管理单元用于高级应用处理器
| 型号： | LP3971 |
| 厂家： | 
National Semiconductor |
| 描述： | POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS |
| 文件： | 总42页 (文件大小：1373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2006
LP3971
Power Management Unit for Advanced Application
Processors
General Description
Features
n Compatible with advanced applications processors
requiring DVM (Dynamic Voltage Management)
n Three buck regulators for powering high current
processor functions or I/O’s
The LP3971 is a multi-function, programmable Power Man-
agement Unit, designed especially for advanced application
processors. The LP3971 is optimized for low power hand-
held applications and provides 6 low dropout, low noise
linear regulators, three DC/DC magnetic buck regulators, a
back-up battery charger and two GPIO’s. A high speed serial
interface is included to program individual regulator output
voltages as well as on/off control.
n 6 LDO’s for powering RTC, peripherals, and I/O’s
n Backup battery charger with automatic switch for
lithium-manganese coin cell batteries and Super
capacitors
n I2C compatible high speed serial interface
n Software control of regulator functions and settings
n Precision internal reference
Key Specifications
Buck Regulators
n Thermal overload protection
n Current overload protection
n Programmable VOUT from 0.8 to 3.3V
n Up to 95% efficiency
n Tiny 40-pin 5x5 mm LLP package
n Up to 1.6A output current
n
3% output voltage accuracy
Applications
LDO’s
n PDA phones
n Programmable VOUT of 1.0V–3.3V
n Smart phones
n Personal Media Players
n Digital cameras
n Application processors
— Intel Xscale
n
3% output voltage accuracy
n 150/300/370 mA output currents
— LDO RTC 30 mA
— LDO 1 300 mA
— LDO 2 150 mA
— LDO 3 150 mA
— Freescale
— LDO 4 150 mA
— Samsung
— LDO 5 370 mA
n 100 mV (typ) dropout
© 2006 National Semiconductor Corporation
DS201807
www.national.com
Simplified Application Circuit
20180701
Connection Diagrams and Package Mark Information
40-Pin Leadless Leadframe Package
NS Package Number SQF40A
20180702
Note: Circle marks pin 1 position.
www.national.com
2
Connection Diagrams and Package Mark Information (Continued)
Package Mark
20180704
Top View
Note: The actual physical placement of the package marking will vary from part to part. The package marking “UZYY” designates
the date code. “TT” is a NSC internal code for die traceability. Both will vary considerably. “LP3971SQF” identifies the device (part
number, option, etc.).
Ordering Information
Option
Order Number
LP3971SQ-A514
LP3971SQX-A514
LP3971SQ-B410
LP3971SQX-B410
Package Marking
71-A514
Supplied As
Default Voltage version – A**
Default Voltage version – A**
‘Default Voltage version - B
Default Voltage version - B
250 units, Tape-and-Reel
2500 units, Tape-and-Reel
250 units, Tape-and-Reel
2500 units, Tape-and-Reel
71-A514
71-B410
71-B410
** To be Released
20180705
Default VOUT Coding
Z
0
1
2
3
4
5
Default VOUT
1.3
1.8
2.5
2.8
3.0
3.3
3
www.national.com
Pin Descriptions
Pin #
Name
PWR_ON
nTEST_JIG
SPARE
I/O
I
Type
D
D
D
D
A
Description
1
CPU Wakeup input
CPU Wakeup input
CPU Wakeup input
CPU Wakeup output
Buck1 Feedback
2
I
3
I
4
EXT_WAKEUP
FB1
O
I
5
6
VIN
I
P
Battery Input (Internal circuitry and LDO1–3 power input)
LDO1 output
7
VOUT LDO1
VOUT LDO2
nRSTI
O
O
I
P
8
P
LDO2 output
9
D
G
A
Reset Input
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND1
G
O
O
O
I
Ground
VREF
Bypass Cap. for reference
LDO3 output
VOUT LDO3
VOUT LDO4
VIN LDO4
VIN BUBATT
VOUT LDO_RTC
nBATT_FLT
PGND2
P
P
LDO4 output
P
Input power for LDO4
Back Up Battery input
LDO_RTC output
I
P
O
O
G
O
I
P
D
G
P
Main Battery fault output
Buck2 NMOS Power Ground
Buck2 Output
SW2
VIN Buck2
SDA
P
Buck2 battery input
I2C Data
I2C Clock
I/O
I
D
D
A
SCL
FB2
I
Buck2 Feedback
nRSTO
O
O
I
D
P
Reset output
VOUT LDO5
VIN LDO5
VDDA
LDO5 output
P
Input power for LDO5
Analog Power
I
P
FB3
I
A
Buck3 Feedback
GPIO1/nCHG_EN
GPIO2
I/O
I/O
I
D
D
P
General Purpose I/O/Ext. backup battery charger enable
General Purpose I/O
Buck3 battery input
Buck3 Output
VIN Buck3
SW3
O
G
G
I
P
PGND3
G
G
D
D
D
G
P
Buck3 NMOS Power Ground
Bucks 1, 2 and 3 analog Ground
Bucks external clock input
High voltage domain enable
Low Voltage domain enable
Buck1 NMOS Power Ground
Buck1 Output
BGND1,2,3
SYNC
SYS_EN
PWR_EN
PGND1
I
I
G
O
I
SW1
VIN Buck1
P
Buck1 battery input
A: Analog Pin
D: Digital Pin
G: Ground Pin
P: Power Pin
I: Input Pin
I/O: Input/Output Pin
O: Output Pin
Note: In this document active low logic items are prefixed with a lowercase “n”
www.national.com
4
Applications Schematic Diagrams
Diagram 1 LDO 4 and LDO5 Connected To VBATTERY
20180706
See Application Hints for recommended external components and component selection
** NOTE: RTC LDO – In applications when Vbatt drops below 1.7V (ie. removing the main battery), system reset will be enabled. To void this situation, replace the
RTC LDO (pin 16) 1.0uF capacitor with a 10uF capacitor.
5
www.national.com
Applications Schematic Diagrams (Continued)
Diagram 2 LDO 4 and LDO5 Connected To 1.8V Supply
20180707
www.national.com
6
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Rating (Note 5)
Human Body Model
Machine Model
2 kV
200V
All Inputs
−0.3V to +6V
0.3V
Operating Ratings
VIN
GND to GND SLUG
Junction Temperature (TJ-MAX
Storage Temperature
Power Dissipation
2.7V to 5.5V
0 to (VIN + 0.3V)
−40˚C to +125˚C
−40˚C to +85˚C
)
150˚C
VEN
−65˚C to +150˚C
Junction Temperature (TJ)
Operating Temperature (TA)
Maximum Power Dissipation
(TA = 70˚C) (Notes 3, 4)
(TA = 70˚C) (Note 3)
Junction-to-Ambient Thermal
Resistance θJA (Note 3)
3.2W
2.2W
25˚C/W
260˚C
Maximum Lead Temp (Soldering)
General Electrical Characteristics Typical values and limits appearing in normal type apply for TJ
25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C.
(Notes 2, 6)
=
Symbol
Parameter
Conditions
Min
2.7
Typ
Max
5.5
Units
V
3
IN, VDDA, VIN Buck1, 2 and Battery Voltage
3.6
V
VINLDO4, VINLDO5
TSD
Power Supply for LDO 4 and 5
Thermal Shutdown (Note 14)
1.74
3.6
160
20
5.5
V
Temperature
Hysteresis
˚C
**No input supply should be higher then VDDA
Supply Specification (Notes 2, 6)
IMAX
Maximum Output
VOUT (Volts)
Supply
Range (V)
Resolution (mV)
N/A
Current (mA) (Note 14)
LDO_RTC
LDO1
Tracking (Note 10)
1.8 to 3.3
30 or 10
300
100
LDO2
1.8 to 3.3
100
150
LDO3
1.8 to 3.3
100
150
LDO4
1.0 to 3.3
50-600
50-600
50-600
50-600
50-600
150
LDO5
1.0 to 3.3
370
BUCK 1
BUCK 2
BUCK 3
0.8 to 3.3
1600
1600
1600
0.8 to 3.3
0.8 to 3.3
Defaults (Notes 2, 6)
‘A’ Version
Enable ‘A’
‘B’ Version
Enable ‘B’
…
Supply
LDO_RTC
LDO1
(V)
2.8
1.8
1.8
3.0
3.0
1.4
1.4
3.3
1.8
(V)
2.8
3.0
3.0
3.0
1.3
1.1
1.4
3.0
1.8
…
SYS_EN
SYS_EN
SYS_EN
SYS_EN
PWR_EN
PWR_EN
SYS_EN
SYS_EN
SYS_EN
SYS_EN
SYS_EN
PWR_EN
PWR_EN
PWR_EN
SYS_EN
SYS_EN
LDO2
LDO3
LDO4
LDO5
BUCK1
BUCK2
BUCK3
**Version-A LDO Tracking Disabled, Version-B LDO Tracking Enabled
7
www.national.com
LDO RTC
Unless otherwise noted, VIN = 3.6V, CIN = 1.0 µF, COUT = 0.47 µF, COUT (VRTC) = 1.0 µF ceramic. Typical values and limits
appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature
range for operation, −40˚C to +125˚C. (Notes 2, 6, 7) and (Note 10)
Symbol
VOUT
Parameter
Conditions
VIN Connected, Load Current =
1 mA
Min
Typ
Max
Units
Output Voltage Accuracy
2.632
2.8
2.968
V
Accuracy
∆VOUT
Line Regulation
Load Regulation
VIN = (VOUT nom + 1.0V) to 5.5V
(Note 11) Load Current = 1 mA
From Main Battery
0.15
0.05
0.5
%/V
Load Current = 1 mA to 30 mA
From Backup Battery
VIN = 3.0V
%/mA
Load Current = 1 mA to 10 mA
From Main Battery
ISC
Short Circuit Current Limit
Dropout Voltage
100
30
VIN = VOUT +0.3V to 5.5V
From Backup Battery
Load Current = 10 mA
mA
mV
VIN
-
375
VOUT
IQ_Max
TP1
Maximum Quiescent Current
RTC LDO Input Switched from
Main Battery to Backup Battery
RTC LDO Input Switched from
Backup Battery to Main Battery
Output Capacitor
IOUT = 0 mA
VIN Falling
30
µA
V
2.9
TP2
CO
VIN Rising
3.0
1.0
V
Capacitance for Stability
ESR
0.7
5
µF
500
mΩ
www.national.com
8
LDO 1 to 5
Unless otherwise noted, VIN = 3.6V, CIN = 1.0 µF, COUT = 0.47 µF, COUT (VRTC) = 1.0 µF ceramic. Typical values and limits
appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature
range for operation, −40˚C to +125˚C. (Notes 2, 6, 7, 10, 11, 15) and (Note 16).
Symbol
Parameter
Conditions
Min
−3
Typ
Max
3
Units
VOUT
Output Voltage Accuracy (Default
Load Current = 1 mA
%
Accuracy VOUT
)
∆VOUT
Line Regulation
VIN =3.1v to 5.0V, (Note 11) Load
Current = 1 mA
0.15
%/V
Load Regulation
VIN = 3.6V,
0.011
%/mA
Load Current = 1 mA to IMAX
LDO1–4, VOUT = 0V
ISC
Short Circuit Current Limit
Dropout Voltage
400
500
mA
mV
LDO5, VOUT = 0V
VIN
-
Load Current = 50 mA (Note 7)
150
VOUT
PSRR
IQ
Power Supply Ripple Rejection
Quiescent Current “On”
Quiescent Current “On”
Quiescent Current “Off”
Turn On Time
f = 10 kHz, Load Current = IMAX
IOUT = 0 mA
45
40
dB
µA
IOUT = IMAX
60
EN is de-asserted
Start up from Shut-down
Capacitance for Stability
0˚C ≤ TJ ≤ 125˚C
−40˚C ≤ TJ ≤ 125˚C
ESR
0.03
300
0.47
TON
µsec
µF
COUT
Output Capacitor
0.33
0.68
5
1.0
500
MΩ
Buck Converters SW1, SW2, SW3
Unless otherwise noted, VIN = 3.6V, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2 µH ceramic. Typical values and limits appearing in
normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for opera-
tion, −40˚C to +125˚C. (Notes 2, 6, 12) and (Note 13).
Symbol
VOUT
Eff
Parameter
Output Voltage Accuracy
Efficiency
Conditions
Default VOUT
Min
Typ
Max
Units
%
−3
+3
Load Current = 500 mA
EN is de-asserted
90
0.1
13
%
ISHDN
Shutdown Supply Current
Sync Mode Clock Frequency
µA
Synchronized from 13 MHz System
Clock
10.4
15.6
2.4
MHz
fOSC
IPEAK
IQ
Internal Oscillator Frequency
Peak Switching Current Limit
Quiescent Current “On”
2.0
2.1
21
MHz
A
No Load PFM Mode
No Load PWM Mode
µA
200
240
RDSON
(P)
Pin-Pin Resistance PFET
Pin-Pin Resistance NFET
mΩ
RDSON
(N)
150
500
mΩ
TON
CIN
Turn On Time
Start up from Shut-down
Capacitance for Stability
Capacitance for Stability
µsec
µF
Input Capacitor
Output Capacitor
8
8
CO
µF
9
www.national.com
Back-Up Charger Electrical Characteristics
Unless otherwise noted, VIN = VBATT = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits ap-
pearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Notes 2, 6) and
(Note 8).
Symbol
VIN
Parameter
Conditions
Voltage at VIN
Min
3.3
Typ
Max
5.5
Units
V
Operational Voltage Range
Backup Battery Charging Current
IOUT
VIN = 3.6V, Backup_Bat = 2.5V,
Backup Battery Charger Enabled
(Note 8)
190
µA
VOUT
Charger Termination Voltage
VIN = 5.0V Backup Battery Charger
Enabled. Programmable
2.91
3.1
9
V
Backup Battery Charger Short
Circuit Current
Backup_Bat = 0V, Backup Battery
Charger Enabled
mA
dB
PSRR
Power Supply Ripple Rejection
Ratio
IOUT ≤ 50 µA, VOUT = 3.15V
VOUT + 0.4 ≤ VBATT = VIN ≤ 5.0V
15
<
f
10 kHz
<
IQ
Quiescent Current
IOUT 50 µA
25
µA
µF
COUT
Output Capacitance
Output Capacitor ESR
0 µA ≤ IOUT ≤ 100 µA
0.1
5
500
MΩ
Logic Inputs and Outputs DC Operating Conditions (Note 2)
Logic Inputs (SYS_EN, PWR_EN, SYNC, nRSTI, PWR_ON, nTEST_JIG, SPARE and GPI’s)
Symbol
VIL
Parameter
Low Level Input Voltage
High Level Input Voltage
Conditions
Min
Max
0.5
Units
V
V
VIH
VRTC
−0.5V
−1
ILEAK
Input Leakage Current
+1
µA
Logic Outputs (nRSTO, EXT_WAKEUP and GPO’s)
Symbol Parameter
VOL Output Low Level
Conditions
Load = +0.2 mA = IOL Max
Load = −0.1 mA = IOL Max
Min
Max
0.5
Units
V
V
VOH
Output High Level
VRTC
−0.5V
ILEAK
Output Leakage Current
VON = VIN
+5
µA
Logic Output (nBATT_FLT)
Symbol Parameter
Conditions
Programmable via Serial Interface
Default = 2.8V
Min
2.4
Typ
Max
3.4
Units
nBATT_FLT Threshold Voltage
2.8
V
VOL
Output Low Level
Output High Level
Load = +0.4 mA = IOL Max
Load = −0.2 mA = IOH Max
0.5
+5
V
V
VOH
VRTC
−0.5V
ILEAK
Input Leakage Current
µA
www.national.com
10
I2C Compatible Serial Interface Electrical Specifications (SDA and SCL)
Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Notes 2, 6) and (Note 9)
Symbol
VIL
Parameter
Low Level Input Voltage
High Level Input Voltage
Low Level Output Voltage
Low Level Output Current
Clock Frequency
Conditions
Min
−0.5
0.7 VRTC
0
Typ
Max
Units
(Note 14)
(Note 14)
(Note 14)
0.3 VRTC
VRTC
V
VIH
VOL
0.2 VTRC
IOL
VOL = 0.4V (Note 14)
(Note 14)
3.0
mA
kHz
µs
FCLK
tBF
400
Bus-Free Time Between Start and Stop (Note 14)
1.3
0.6
1.3
0.6
0.6
0
tHOLD
tCLKLP
tCLKHP
tSU
Hold Time Repeated Start Condition
CLK Low Period
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
(Note 14)
µs
µs
CLK High Period
µs
Set Up Time Repeated Start Condition
µs
tDATAHLD Data Hold Time
µs
tCLKSU
TSU
Data Set Up Time
100
0.6
ns
Set Up Time for Start Condition
Maximum Pulse Width of Spikes that
Must be Suppressed by the Input Filter
of Both DATA & CLK Signals
µs
TTRANS
50
ns
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ ), as given by the
JA
following equation: TA-MAX = TJ-MAX-OP – (θ x PD-MAX).
JA
Note 4: Junction-to-ambient thermal resistance (θ ) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC
JA
standard JESD51–7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane on the board
is 50 mm x 50 mm. Thickness of copper layers are 36 µm/1.8 µm/18 µm/36 µm (1.5 oz/1 oz/1 oz/1.5 oz). Ambient temperature in simulation is 22˚C, still air. Power
dissipation is 1W. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation
exists, special care must be paid to thermal dissipation issues in board design. The value of θ of this product can vary significantly, depending on PCB material,
JA
layout, and environmental conditions. In applications where high maximum power dissipation exists (high V , high I
), special care must be paid to thermal
IN
OUT
dissipation issues. For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and
Power Dissipation section of this datasheet.
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7). The machine model is a 200 pF
capacitor discharged directly into each pin. (EAIJ)
Note 6: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are production
tested, guaranteed through statistical analysis or guaranteed by design. All limits at temperature extremes are guaranteed via correlation using standard Statistical
Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Note 7: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
2
Note 8: Back-up battery charging current is programmable via the I C compatible interface. Refer to the Application Section for more information.
2
Note 9: The I C signals behave like open-drain outputs and require an external pull-up resistor on the system module in the 2 kΩ to 20 kΩ range.
Note 10: LDO_RTC voltage can track LDO1 (I/O) Voltage. Refer to LP3971 Controls Section for more information.
Note 11: V minimum for line regulation values is 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5. Condition does not apply to input voltages below the minimum
IN
input operating voltage.
Note 12: The input voltage range recommended for ideal applications performance for the specified output voltages is given below:
<
<
OUT
V
IN
V
IN
= 2.7V to 5.5V for 0.80V
V
1.8V
+ 1V) to 5.5V for 1.8V ≤ V ≤ 3.3V
OUT
= (V
OUT
Note 13: Test condition: for V
less than 2.7V, V = 3.6V; for V
greater than or equal to 2.7V, V = V
+ 1V.
OUT
OUT
IN
OUT
IN
Note 14: This electrical specification is guaranteed by design.
Note 15: An increase in the load current results in a slight decrease in the output voltage and vice versa.
Note 16: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply
for input voltages below 2.7V for LDOs 1–3 and 1.8V for LDOs 4 and 5.
11
www.national.com
Input Test Signals
20180708
FIGURE 1. Line Transient Response Input Test Signal
20180709
FIGURE 2. PSRR Input Test Signal
www.national.com
12
Functional Block Diagram
20180710
13
www.national.com
Buck Converter Operation
DEVICE INFORMATION
The LP3971 includes three high efficiency step down DC-DC
switching buck converters. Using a voltage mode architec-
ture with synchronous rectification, the buck converters have
the ability to deliver up to 1600 mA depending on the input
voltage, output voltage, ambient temperature and the induc-
tor chosen. There are three modes of operation depending
on the current required - PWM, PFM, and shutdown. The
device operates in PWM mode at load currents of approxi-
mately 100 mA or higher, having voltage tolerance of 3%
with 95% efficiency or better. Lighter load currents cause the
device to automatically switch into PFM for reduced current
consumption. Shutdown mode turns off the device, offering
the lowest current consumption (IQ,
= 0.01 µA
SHUTDOWN
20180711
typ). Additional features include soft-start, under voltage pro-
tection, current overload protection, and thermal shutdown
protection. The part uses an internal reference voltage of
0.5V. It is recommended to keep the part in shutdown until
the input voltage is 2.8V or higher.
FIGURE 3. Typical PWM Operation
Internal Synchronous Rectification
CIRCUIT OPERATION
While in PWM mode, the converters uses an internal NFET
as a synchronous rectifier to reduce rectifier forward voltage
drop and associated power loss. Synchronous rectification
provides a significant improvement in efficiency whenever
the output voltage is relatively low compared to the voltage
drop across an ordinary rectifier diode.
The buck converter operates as follows. During the first
portion of each switching cycle, the control block turns on the
internal PFET switch. This allows current to flow from the
input through the inductor to the output filter capacitor and
load. The inductor limits the current to a ramp with a slope of
(VIN–VOUT)/L, by storing energy in a magnetic field.
Current Limiting
During the second portion of each cycle, the controller turns
the PFET switch off, blocking current flow from the input, and
then turns the NFET synchronous rectifier on. The inductor
draws current from ground through the NFET to the output
filter capacitor and load, which ramps the inductor current
down with a slope of - VOUT/L.
A current limit feature allows the converters to protect itself
and external components during overload conditions. PWM
mode implements current limiting using an internal compara-
tor that trips at 2.1A (typ). If the output is shorted to ground
the device enters a timed current limit mode where the NFET
is turned on for a longer duration until the inductor current
falls below a low threshold, ensuring inductor current has
more time to decay, thereby preventing runaway.
The output filter stores charge when the inductor current is
high, and releases it when inductor current is low, smoothing
the voltage across the load.
The output voltage is regulated by modulating the PFET
switch on time to control the average current sent to the load.
The effect is identical to sending a duty-cycle modulated
rectangular wave formed by the switch and synchronous
rectifier at the SW pin to a low-pass filter formed by the
inductor and output filter capacitor. The output voltage is
equal to the average voltage at the SW pin.
PFM OPERATION
At very light loads, the converter enters PFM mode and
operates with reduced switching frequency and supply cur-
rent to maintain high efficiency.
The part will automatically transition into PFM mode when
either of two conditions occurs for a duration of 32 or more
clock cycles:
A: The inductor current becomes discontinuous.
PWM OPERATION
B: The peak PMOS switch current drops below the IMODE
During PWM operation the converter operates as a voltage
mode controller with input voltage feed forward. This allows
the converter to achieve good load and line regulation. The
DC gain of the power stage is proportional to the input
voltage. To eliminate this dependence, feed forward in-
versely proportional to the input voltage is introduced.
<
level, (Typically IMODE 30 mA + VIN/42Ω).
While in PWM (Pulse Width Modulation) mode, the output
voltage is regulated by switching at a constant frequency
and then modulating the energy per cycle to control power to
the load. At the beginning of each clock cycle the PFET
switch is turned on and the inductor current ramps up until
the comparator trips and the control logic turns off the switch.
The current limit comparator can also turn off the switch in
case the current limit of the PFET is exceeded. Then the
NFET switch is turned on and the inductor current ramps
down. The next cycle is initiated by the clock turning off the
NFET and turning on the PFET.
www.national.com
14
nominal PWM output voltage. If the output voltage is below
the “high” PFM comparator threshold, the PMOS power
switch is turned on. It remains on until the output voltage
reaches the ‘high’ PFM threshold or the peak current ex-
ceeds the IPFM level set for PFM mode. The typical peak
current in PFM mode is: IPFM = 112 mA + VIN/27Ω. Once the
PMOS power switch is turned off, the NMOS power switch is
turned on until the inductor current ramps to zero. When the
NMOS zero-current condition is detected, the NMOS power
switch is turned off. If the output voltage is below the ‘high’
PFM comparator threshold (see Figure 5), the PMOS switch
is again turned on and the cycle is repeated until the output
reaches the desired level. Once the output reaches the ‘high’
PFM threshold, the NMOS switch is turned on briefly to ramp
the inductor current to zero and then both output switches
are turned off and the part enters an extremely low power
mode. Quiescent supply current during this ‘sleep’ mode is
16 µA (typ), which allows the part to achieve high efficiencies
under extremely light load conditions. When the output drops
below the ‘low’ PFM threshold, the cycle repeats to restore
the output voltage (average voltage in PFM mode) to
Buck Converter Operation (Continued)
20180712
FIGURE 4. Typical PFM Operation
<
1.15% above the nominal PWM output voltage. If the load
current should increase during PFM mode (see Figure 5)
causing the output voltage to fall below the ‘low2’ PFM
threshold, the part will automatically transition into fixed-
frequency PWM mode. Typically when VIN = 3.6V the part
transitions from PWM to PFM mode at 100 mA output
current.
During PFM operation, the converter positions the output
voltage slightly higher than the nominal output voltage during
PWM operation, allowing additional headroom for voltage
drop during a load transient from light to heavy load. The
PFM comparators sense the output voltage via the feedback
pin and control the switching of the output FETs such that the
<
<
output voltage ramps between 0.6% and 1.7% above the
20180713
FIGURE 5. Operation in PFM Mode and Transfer to PWM Mode
15
www.national.com
VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT
Buck Converter Operation (Continued)
SHUTDOWN MODE
•ILOAD
•RDSON, PFET
Load Current
Drain to source resistance of PFET
switch in the triode region
Inductor resistance
During shutdown the PFET switch, reference, control and
bias circuitry of the converters are turned off. The NFET
switch will be on in shutdown to discharge the output. When
the converter is enabled, soft start is activated. It is recom-
mended to disable the converter during the system power up
and undervoltage conditions when the supply is less than
2.8V.
•RINDUCTOR
BUCK CONVERTER EFFICIENCY
VIN (V)
3.6
VOUT (V)
1.4
IOUT (mA)
100
EFF(%)
85
SOFT START
3.6
1.4
500
89
The buck converter has a soft-start circuit that limits in-rush
current during start-up. During start-up the switch current
limit is increased in steps. Soft start is activated only if EN
goes from logic low to logic high after VIN reaches 2.8V. Soft
start is implemented by increasing switch current limit in
steps of 213 mA, 425 mA, 850 mA and 1700 mA (typ. Switch
current limit). The start-up time thereby depends on the
output capacitor and load current demanded at start-up.
Typical start-up times with 10 µF output capacitor and 1000
mA load current is 390 µs and with 1 mA load current its
295 µs.
3.6
1.4
1000
84
3.6
1.4
1500
78
VIN (V)
3.6
VOUT (V)
3.3
IOUT (mA)
100
EFF(%)
92
3.6
3.3
500
96
3.6
3.3
1000
93
3.6
3.3
1500
90
VIN (V)
3.6
VOUT (V)
1.8
IOUT (mA)
100
EFF(%)
85
LDO - LOW DROP OUT OPERATION
The LP3971 can operate at 100% duty cycle (no switching;
PMOS switch completely on) for low drop out support of the
output voltage. In this way the output voltage will be con-
trolled down to the lowest possible input voltage. When the
device operates near 100% duty cycle, output voltage ripple
is approximately 25 mV. The minimum input voltage needed
to support the output voltage is
3.6
1.8
500
91
3.6
1.8
1000
87
3.6
1.8
1500
82
I2C Compatible Interface
I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can
only be changed when CLK is LOW.
20180714
I2C START and STOP CONDITIONS
generates START and STOP bits. The I2C bus is considered
to be busy after START condition and free after STOP con-
dition. During data transmission, I2C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from
LOW to HIGH while SCL is HIGH. The I2C master always
www.national.com
16
I2C Compatible Interface (Continued)
20180715
TRANSFERRING DATA
After the START condition, a chip address is sent by the I2C
master. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LP3971 address
is 46h. For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to
which the data will be written. The third byte contains data to
write to the selected register.
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte of data has to be followed by an
acknowledge bit. The acknowledge related clock pulse is
generated by the master. The transmitter releases the SDA
line (HIGH) during the acknowledge clock pulse. The re-
ceiver must pull down the SDA line during the 9th clock
pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte
has been received.
I2C CHIP ADDRESS - 7h’34
MSB
ADR6
Bit7
0
ADR5
Bit6
1
ADR4
Bit5
1
ADR3
Bit4
0
ADR2
Bit3
1
ADR1
Bit2
0
ADR0
Bit1
0
R/W
Bit0
R/W
Write Cycle
20180716
When a READ function is to be accomplished, a WRITE function must precede the READ function as follows.
Read Cycle
20180717
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 34h (Chip Address)
17
www.national.com
2
I C Register Definitions
I2C CONTROL REGISTERS
Register
Address
8h’02
8h’07
8h’0B
8h’0E
8h’10
8h’11
8h’12
8h’13
8h’20
8h’23
8h’24
8h’25
8h’29
8h’2A
8h’2B
8h’32
8h’33
8h’34
8h’38
8h’39
8h’3A
8h’3B
Register
Name
Read/
Write
R
Register Description
ISR
Interrupt Status Register A
System Control Register 1
SCR1
R/W
R/W
R/W
R/W
R
BBCC
SCR2
Backup Battery Charger Control Register
System Control Register 2
BOVEN
BOVSR
LDOEN
LDOVS
VCC1
Buck Output Voltage Enable Register
Buck Output Voltage Status Register
LDO Output Voltage Enable Register
LDO Output Voltage Status Register
Voltage Change Control Register 1
Buck 1 Target Voltage 1 Register
Buck 1 Target Voltage 2 Register
Buck 1 Ramp Control
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
B1TV1
B1TV2
B1RC
B2TV1
B2TV2
B2RC
Buck 2 Target Voltage 1 Register
Buck 2 Target Voltage 2 Register
Buck 2 Voltage Ramp Control
B3TV1
B3TV2
B3RC
Buck 3 Target Voltage 1 Register
Buck 3 Target Voltage 2 Register
Buck 3 Voltage Ramp Control
BFR
Buck Function Register
L21VCR
L43VCR
L5VCR
LDO2 & 1 Voltage Control Registers
LDO4 & LDO3 Voltage Control Registers
LDO5 Voltage Control Registers
INTERRUPT STATUS REGISTER (ISR) 8h’02
Bit
7
T100
0
6
T125
0
5
GPI2
0
4
GPI1
0
3
WU3L
0
2
WUPS
0
1
WUPT
0
0
WUPS
0
Designation
Reset Value
INTERRUPT STATUS REGISTER (ISR) 8h’02 DEFINITIONS
Bit
7
Access
Name
-
Description
-
Reserved
Status bit for thermal warming PMIC T 125˚C
>
6
R
T125
<
0 = PMIC Temp. 125˚C
>
1 = PMIC Temp. 125˚C
5
4
3
2
R
R
R
R
GPI2
GPI1
Status bit for the input read in from GPIO 2 when set as Input
0 = GPI2 Logic Low
1 = GPI2 Logic High
Status bit for the input read in from GPIO 1 when set as Input
0 = GPI1 Logic Low
1 = GPI1 Logic High
WU3L
WUPS
PWR_ON Pin Long Pulse Wake Up Status
0 = 1 No wake up event
1 = Long pulse wake up event
PWR_ON Pin Short Pulse Wake Up Status
0 = No wake up event
1 = Short pulse wake up event
www.national.com
18
2
I C Register Definitions (Continued)
Bit
Access
Name
Description
1
R
WUPT
TEST_JIG Pin Wake Up Status
0 = No wake up event
1 = Wake up event
0
R
WUPS
SPARE Pin Wake Up Status
0 = No wake up event
1 = Wake up event
SYSTEM CONTROL REGISTER 1 (SCR1) 8h’07
Bit
7
BPSEN
0
6
Reserved
1
5
4
3
2
FPWM2
0
1
FPWM1
0
0
ECEN
0
Designation
SENDL
FPWM3
0
Reset Value
0
0
Note: Gray denotes EPROM programmable registers for default value.
SYSTEM CONTROL REGISTER 1 (SCR1) 8h’07 DEFINITIONS
Bit
Access
Name
Description
7
R/W
BPSEN
Bypass System enable safety Lock. Prevents activation of PWR_EN when SYS_EN is low.
0 = PWR_EN “AND” with SYS_EN signal
1 = PWR_EN independent of SYS_EN
6
-
-
Reserved
5:4
R/W
SENDL
Delay time for High Voltage Power Domains LDO2, LDO3, LDO4, Buck2, and Buck3 after
activation of SYS_EN. VCC_LDO1 has no delay.
Data Code
2h’0
Delay mS
0.0
Notes
Default for “B”
2h’1
0.5
2h’2
1.0
Default for “A”
2h’3
1.4
3
2
1
0
R/W
R/W
R/W
R/W
FPWM3
FPWM2
FPWM1
ECEN
Buck 3 PWM/PFM Mode Select
0 - Auto Switch between PFM and PWM operation
1 - PWM Mode Only will not switch to PFM
Buck 2 PWM/PFM Mode Select
0 - Auto Switch between PFM and PWM operation
1 - PWM Mode Only will not switch to PFM
Buck 1 PWM/PFM Mode Select
0 - Auto Switch between PFM and PWM operation
1 - PWM Mode Only will not switch to PFM
External Clock Select
0 = Internal Oscillator clock for Buck Converters
1 = External 13 MHz Oscillator clock for Buck Converters
19
www.national.com
2
I C Register Definitions (Continued)
BACKUP BATTERY CHARGER CONTROL REGISTER (BBCC) 8h’0B
Bit
7
NBUB
0
6
CNBFL
0
5
4
nBFLT
1
3
2
BUCEN
0
1
0
Designation
Reset Value
IBUC
0
0
0
1
BACKUP BATTERY CHARGER CONTROL REGISTER (BBCC) 8h’0B DEFINITIONS
Bit
Access
Name
Description
7
R/W
NBUB
No back-up battery default setting. Logic will not allow switch over to back-up battery.
0 = Back up Battery Enabled
1 = Back up Battery Disabled
6
R/W
R/W
CNBFL
BFLT
Control for nBATT_FLT output signal
0 = nBATT_FLT Enabled
1 = nBATT_FLT Disabled
5:3
nBATT_FLT monitors the battery voltage and can be set to the De-assert voltages listed
below.
Data Code
3h’00
Asserted
2.4
De-Asserted
2.6
2.8
3.0
3.2
3.4
3.6
3h’01
2.6
3h’02
2.8
3h’03
3.0
3h’04
3.2
3h’05
3.4
2
R/W
R/W
BUCEN
IBUC
Enables backup battery charger
0 = Back up Battery Charger Disabled
1 = Back up Battery Charger Enabled
Charger current setting for back-up battery
1:0
Data Code
2h’00
BU Charger I (µA)
260
190
325
390
2h’01
2h’02
2h’03
www.national.com
20
2
I C Register Definitions (Continued)
SYSTEM CONTROL REGISTER (SCR2) 8h’0E
Bit
7
6
5
4
WUP3_
sense
1
3
2
1
0
Designation
BBCS
SEB2
BPTR
GPIO2
GPIO1
Reset Value
1
0
0
0
0
0
0
SYSTEM CONTROL REGISTER (SCR2) 8h’0E DEFINITIONS
Bit
Access
Name
Description
7
R/W
BBCS
Sets GPIO1 as control input for Back Up battery charger
0 = Back Up battery Charger GPIO Disabled
1 = Back Up battery Charger GPIO Pin Enabled
6
5
R/W
R/W
R/W
R/W
SEB2
BPTR
PWR_EN soft Low voltage Supply Enabled OR’ed with PWR_EN Pin
0 = Low voltage Supply Output Enabled
1 = Low voltage Supply Output Disabled
Bypass RTC_LDO Output Voltage to LDO1 Output Voltage Tracking
0 = Disabled RTC_LDO1 Tracking enabled
1 = Enabled RTC-LDO1 Tracking disabled
Spare Wakeup control input
4
WUP3_
sense
0 = Active High
1 = Active Low
3:2
GPIO2
GPIO1
Configure direction and output sense of GPIO2 Pin
Data Code
2h’00
GPIO2
Hi-Z
2h’01
Output Low
Input
2h’02
2h’03
Output high
1:0
R/W
Configure direction and output sense of GPIO1 Pin
Data Code
2h’00
GPIO1
Hi-Z
2h’01
Output Low
Input
2h’02
2h’03
Output high
21
www.national.com
2
I C Register Definitions (Continued)
BUCKS OUTPUT VOLTAGE ENABLE REGISTER (BOVEN) 8h’10
Bit
7
Reserved
0
6
B2ENC
1
5
Reserved
0
4
B3EN
1
3
Reserved
0
2
B2EN
1
1
Reserved
0
0
B1EN
1
Designation
Reset Value
BUCKS ENABLE REGISTER (BOVEN) 8h’10 DEFINITIONS
Bit
7
Access
...
Name
...
Description
Reserved
6
R/W
B2ENC
Connects Buck 2 enable to SYS_EN or PWR_EN Logic Control pin
0 = Buck 2 enable connected to PWR_EN
1 = Buck 2 enable connected to SYS_EN
Reserved
5
4
...
...
R/W
B3EN
VCC_Buck3 Supply Output Enabled
0 = VCC_Buck3 Supply Output Disabled
1 = VCC_Buck3 Supply Output Enabled
Reserved
3
2
...
...
R/W
B2EN
VCC_Buck2 Supply Output Enabled
0 = VCC_Buck2 Supply Output Disabled
1 = VCC_Buck2 Supply Output Enabled
Reserved
1
0
...
...
R/W
B1EN
VCC_Buck1 Supply Output Enabled
0 = VCC_Buck2 Supply Output Disabled
1 = VCC_Buck2 Supply Output Enabled
BUCK STATUS REGISTER (BOVSR) 8h’11
Bit
7
BT_OK
0
6
Reserved
0
5
Reserved
0
4
B3_OK
0
3
Reserved
0
2
B2_OK
0
1
0
B1_OK
0
Designation
Reset Value
0
BUCK STATUS REGISTER (BOVSR) 8h’11 DEFINITIONS
Bit
Access
Name
Description
7
R
BT_OK
Buck 1–3 Supply Output Voltage Status
<
0 = (Buck 1–3) output voltage 90% Default value
>
1 = (Buck 1–3) output voltage 90% Default value
6:5
4
...
R
...
Reserved
B3_OK
Buck 3 Supply Output Voltage Status
<
0 = (Buck 3) output voltage 90% Default value
>
1 = (Buck 3) output voltage 90% Default value
3
2
...
R
...
Reserved
B2_OK
Buck 2 Supply Output Voltage Status
<
0 = (Buck 2) output voltage 90% Default value
>
1 = (Buck 2) output voltage 90% Default value
1
0
...
R
...
Reserved
B1_OK
Buck 1 Supply Output Voltage Status
<
0 = (Buck 1) output voltage 90% Default value
>
1 = (Buck 1) output voltage 90% Default value
www.national.com
22
2
I C Register Definitions (Continued)
LDO OUTPUT VOLTAGE ENABLE REGISTER (LDOEN) 8h’12
Bit
7
L5EC
0
6
L4EC
0
5
LDO5_EN
1
4
LDO4_EN
1
3
LDO3_EN
1
2
LDO2_EN
1
1
LDO1_EN
1
0
Reserved
0
Designation
Reset Value
LDO OUTPUT VOLTAGE ENABLE REGISTER (LDOEN) 8h’12 DEFINITIONS
Bit
Access
Name
Description
7
R/W
L5EC
Connects LDO5 enable to SYS_EN or PWR_EN Logic Control pin
0 = LDO 5 enable connected to PWR_EN
1 = LDO 5 enable connected to SYS_EN
Connects LDO4 enable to SYS_EN or PWR_EN Logic Control pin
0 = LDO 4 enable connected to PWR_EN
1 = LDO 4 enable connected to SYS_EN
LDO_5 Output Voltage Enable
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
...
L4EC
LDO5_EN
LDO4_EN
LDO3_EN
LDO2_EN
LDO1_EN
...
0 = LDO5 Supply Output Disabled
1 = LDO5 Supply Output Enabled
LDO_4 Output Voltage Enable
0 = LDO4 Supply Output Disabled
1 = LDO4 Supply Output Enabled
LDO_3 Output Voltage Enable
0 = LDO3 Supply Output Disabled
1 = LDO3 Supply Output Enabled
LDO_2 Output Voltage Enable
0 = LDO2 Supply Output Disabled
1 = LDO2 Supply Output Enabled
LDO_1 Output Voltage Enable
0 = LDO1 Supply Output Disabled
1 = LDO1 Supply Output Enabled
Reserved
LDO OUTPUT VOLTAGE STATUS REGISTER (LDOVS) 8h’13
Bit
7
LDOS_OK
0
6
N/A
0
5
LDO5_0K
0
4
LDO4_OK
0
3
LDO3_OK
0
2
LDO2_OK
0
1
LDO1_OK
0
0
N/A
0
Designation
Reset Value
LDO OUTPUT VOLTAGE STATUS REGISTER (LDOVS) 8h’13 DEFINITIONS
Bit
Access
Name
Description
7
R
LDO_OK
LDO 1–5 Supply Output Voltage Status
<
0 = (LDO 1–5) output voltage 90% of selected value
>
1 = (LDO 1–5) output voltage 90% of selected value
6
5
...
R
...
Reserved
LDO5_OK
LDO_5 Output Voltage Status
<
0 = (VCC_LDO5) output voltage 90% of selected value
>
1 = (VCC_LDO5) output voltage 90% of selected value
4
3
R
R
LDO4_OK
LDO3_OK
LDO_4 Output Voltage Status
<
>
0 = (VCC_LDO4) output voltage 90% of selected value
1 = (VCC_LDO4) output voltage 90% of selected value
LDO_3 Output Voltage Status
<
0 = (VCC_LDO3) output voltage 90% of selected value
>
1 = (VCC_LDO3) output voltage 90% of selected value
23
www.national.com
2
I C Register Definitions (Continued)
Bit
Access
Name
Description
2
R
LDO2_OK
LDO_2 Output Voltage Status
0 = (VCC_LDO2) output voltage 90% of selected value
<
>
1 = (VCC_LDO2) output voltage 90% of selected value
1
R
LDO1_OK
LDO_1 Output Voltage Status
<
0 = (VCC_LDO1) output voltage 90% of selected value
>
1 = (VCC_LDO1) output voltage 90% of selected value
0
...
...
Reserved
VOLTAGE CHANGE CONTROL REGISTER 1 (VCC1) 8h’20
Bit
7
B3VS
0
6
B3GO
0
5
B2VS
0
4
B2GO
0
3
2
1
B2VS
0
0
B2GO
0
Designation
Reset Value
Reserved
0
0
VOLTAGE CHANGE CONTROL REGISTER 1 (VCC1) 8h’20 DEFINITIONS
Bit
Access
Name
Description
7
R/W
B3VS
Buck 3 Target Voltage Select
0 = Buck 3 Output Voltage to B1TV1
1 = Buck 3 Output Voltage to B1TV2
Start Buck 3 Voltage Change
6
5
4
R/W
R/W
R/W
B3GO
B2VS
B2GO
0 = Hold Buck 3 Output Voltage at current level
1 = Ramp Buck 3 Output Voltage as selected by B3VS
Buck 2 Target Voltage Select
0 = Buck 2 Output Voltage to B2TV1
1 = Buck 2 Output Voltage to B2TV2
Start Buck 2 Voltage Change
0 = Hold Buck 2 Output Voltage at current level
1 = Ramp Buck 2 Output Voltage as selected by B2VS
Reserved
3:2
1
...
...
R/W
B1VS
Buck 1 Target Voltage Select
0 = Buck 2 Output Voltage to B1TV1
1 = Buck 2 Output Voltage to B1TV2
Start Buck 1 Voltage Change
0
R/W
B1GO
0 = Hold Buck 3 Output Voltage at current level
1 = Ramp Buck 3 Output Voltage as selected by B1VS
www.national.com
24
2
I C Register Definitions (Continued)
BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) 8h’23
Bit
7
6
Reserved
0
5
4
3
2
1
0
Designation
Reset Value
Buck 1 Output Voltage (B1OV)
0
0
0
1
1
0
1
BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) 8h’23 DEFINITIONS
Bit
7:5
4:0
Access
...
Name
...
Description
Reserved
Output Voltage
Data Code
5h’01
R/W
B1OV
(V)
Data Code
5h’0D
5h’0E
5h’0F
5h’11
(V)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.60
1.65
1.70
1.80
1.90
2.50
2.80
3.00
3.30
5h’02
5h’03
5h’04
5h’05
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’06
5h’07
5h’08
5h’09
5h’0A
5h’0B
5h’0C
BUCK1 TARGET VOLTAGE 2 REGISTER (B1TV2) 8h’24
Bit
7
6
Reserved
0
5
4
3
2
1
0
Designation
Reset Value
Buck 1 Output Voltage (B1OV)
0
0
0
1
1
0
1
BUCK1 TARGET VOLTAGE 2 REGISTER (B1TV2) 8h’24 DEFINITIONS
Bit
7:5
4:0
Access
...
Name
...
Description
Reserved
Output Voltage
Data Code
5h’01
R/W
B1OV
(V)
Data Code
5h’0D
5h’0E
5h’0F
5h’11
(V)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.60
1.65
1.70
1.80
1.90
2.50
2.80
3.00
3.30
5h’02
5h’03
5h’04
5h’05
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’06
5h’07
5h’08
5h’09
5h’0A
5h’0B
5h’0C
25
www.national.com
2
I C Register Definitions (Continued)
BUCK 1 VOLTAGE RAMP CONTROL REGISTER (B1RC) 8h’25
Bit
7
6
5
4
3
2
1
0
Designation
Reset Value
Reserved
Ramp Rate
0
0
0
0
1
0
1
0
BUCK 1 VOLTAGE RAMP CONTROL REGISTER (B1RC) 8h’25 DEFINITIONS
Bit
7:5
4:0
Access
...
Name
...
Description
Reserved
R/W
B1RS
DVM Ramp Speed
Ramp Rate
(mV/µs)
Data Code
4h’0
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A
Instant
1
2
3
4
5
6
7
8
9
10
BUCK 2 TARGET VOLTAGE 1 REGISTER (B2TV1) 8h’29
Bit
7
6
Reserved
0
5
4
3
2
1
0
Designation
Reset Value
Buck 2 Output Voltage (B2OV)
0
0
1
1
0
0
0
BUCK 2 TARGET VOLTAGE 1 REGISTER (B2TV1) 8h’29 DEFINITIONS
Bit
7:5
4:0
Access
...
Name
...
Description
Reserved
Output Voltage
Data Code
5h’01
R/W
B2OV
(V)
Data Code
5h’0D
5h’0E
5h’0F
5h’11
(V)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.60
1.65
1.70
1.80
1.90
2.50
2.80
3.00
3.30
5h’02
5h’03
5h’04
5h’05
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’06
5h’07
5h’08
5h’09
5h’0A
5h’0B
5h’0C
www.national.com
26
2
I C Register Definitions (Continued)
BUCK 2 TARGET VOLTAGE 2 REGISTER (B2TV2) 8h’2A
Bit
7
6
Reserved
0
5
4
3
2
1
0
Designation
Reset Value
Buck 2 Output Voltage (B2OV)
0
0
1
1
0
0
0
BUCK 2 TARGET VOLTAGE 2 REGISTER (B2TV2) 8h’2A DEFINITIONS
Bit
7:5
4:0
Access
...
Name
...
Description
Reserved
Output Voltage
Data Code
5h’01
R/W
B2OV
(V)
Data Code
5h’0D
5h’0E
5h’0F
5h’11
(V)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.60
1.65
1.70
1.80
1.90
2.50
2.80
3.00
3.30
5h’02
5h’03
5h’04
5h’05
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’06
5h’07
5h’08
5h’09
5h’0A
5h’0B
5h’0C
BUCK 2 VOLTAGE RAMP CONTROL REGISTER (B2RC) 8h’2B
Bit
7
6
5
4
3
2
1
0
Designation
Reset Value
Reserved
Ramp Rate
0
0
0
0
1
0
1
0
BUCK 2 VOLTAGE RAMP CONTROL REGISTER (B2RC) 8h’2B DEFINITIONS
Bit
7:5
4:0
Access
...
Name
...
Description
Reserved
R/W
B2RS
DVM Ramp Speed
Ramp Rate
(mV/µs)
Data Code
4h’0
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A
Instant
1
2
3
4
5
6
7
8
9
10
27
www.national.com
2
I C Register Definitions (Continued)
BUCK 3 TARGET VOLTAGE 1 REGISTER (B3TV1) 8h’32
Bit
7
6
Reserved
0
5
4
3
2
1
0
Designation
Reset Value
Buck 3 Output Voltage (B3OV)
0
0
1
0
1
0
0
BUCK 3 TARGET VOLTAGE 1 REGISTER (B3TV1) 8h’32 DEFINITIONS
Bit
7:5
4:0
Access
...
Name
...
Description
Reserved
Output Voltage
Data Code
5h’01
R/W
B3OV
(V)
Data Code
5h’0D
5h’0E
5h’0F
5h’11
(V)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.60
1.65
1.70
1.80
1.90
2.50
2.80
3.00
3.30
5h’02
5h’03
5h’04
5h’05
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’06
5h’07
5h’08
5h’09
5h’0A
5h’0B
5h’0C
BUCK 3 TARGET VOLTAGE 2 REGISTER (B3TV2) 8h’33
Bit
7
6
Reserved
0
5
4
3
2
1
0
Designation
Reset Value
Buck 2 Output Voltage (B2OV)
0
0
1
0
1
0
0
BUCK 3 TARGET VOLTAGE 2 REGISTER (B3TV2) 8h’33 DEFINITIONS
Bit
7:5
4:0
Access
...
Name
...
Description
Reserved
Output Voltage
Data Code
5h’01
R/W
B2OV
(V)
Data Code
5h’0D
5h’0E
5h’0F
5h’11
(V)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.60
1.65
1.70
1.80
1.90
2.50
2.80
3.00
3.30
5h’02
5h’03
5h’04
5h’05
5h’12
5h’13
5h’14
5h’15
5h’16
5h’17
5h’18
5h’19
5h’06
5h’07
5h’08
5h’09
5h’0A
5h’0B
5h’0C
www.national.com
28
2
I C Register Definitions (Continued)
BUCK 3 VOLTAGE RAMP CONTROL REGISTER (B3RC) 8h’34
Bit
7
6
5
4
3
2
1
0
Designation
Reset Value
Reserved
Ramp Rate
0
0
0
0
1
0
1
0
BUCK 2 VOLTAGE RAMP CONTROL REGISTER (B2RC) 8h’34 DEFINITIONS
Bit
7:5
4:0
Access
...
Name
...
Description
Reserved
R/W
B2RS
DVM Ramp Speed
Ramp Rate
(mV/µs)
Data Code
4h’0
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A
Instant
1
2
3
4
5
6
7
8
9
10
BUCK FUNCTION REGISTER (BFR) 8h’38
Bit
7
6
5
Reserved
0
4
3
2
1
0
Designation
Reset Value
SHBU
0
BK_SLOMOD
1
BK_SSEN
0
0
0
0
0
BUCK FUNCTION REGISTER (BFR) 8h’38 DEFINITIONS
Bit
Access
Name
...
Description
7:3
...
Reserved
SHBU
Shut down Back up battery to prevent battery drain during shipping
0 = Back up Battery Enabled
1 = Back up Battery Disabled
1
0
R
R
BK_SLOMOD Buck Spread Spectrum Modulation Buck 1–3
0 = 10 kHz triangular wave spread spectrum modulation
1 = 2 kHz triangular wave spread spectrum modulation
BK_SSEN
Spread spectrum function Buck 1–3
0 = SS Output Disabled
1 = SS Output Enabled
29
www.national.com
2
I C Register Definitions (Continued)
LDO2–LDO1 VOLTAGE CONTROL REGISTER (L21VCR) 8h’39
Bit
7
6
5
4
3
2
1
0
Designation
Reset Value
LDO 2 Output Voltage (L20V)
LDO 3 Output Voltage (L1OV)
1
1
0
0
1
1
0
0
LDO2–LDO1 VOLTAGE CONTROL REGISTER (L21VCR) 8h’39 DEFINITIONS
Bit
Access
Name
Description
Output Voltage
Data Code
4h’0
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A
4h’B
4h’C
4h’D
4h’E
4h’F
4h’0
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A
4h’B
4h’C
4h’D
4h’E
4h’F
7:4
R/W
L2OV
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3:0
R/W
L1OV
www.national.com
30
2
I C Register Definitions (Continued)
LDO4–LDO3 VOLTAGE CONTROL REGISTER (L21VCR) 8h’3A
Bit
7
6
5
4
3
2
1
0
Designation
Reset Value
LDO 4 Output Voltage (L4OV)
LDO 3 Output Voltage (L3OV)
0
1
1
0
1
1
0
0
LDO4–LDO3 VOLTAGE CONTROL REGISTER (L21VCR) 8h’3A DEFINITIONS
Bit
Access
Name
Description
Output Voltage
Data Code
4h’0
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A
4h’B
4h’C
4h’D
4h’E
4h’F
4h’0
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A
4h’B
4h’C
4h’D
4h’E
4h’F
7:4
R/W
L4OV
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.50
1.80
1.90
2.50
2.80
3.00
3.30
1.8
3:0
R/W
L3OV
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
31
www.national.com
2
I C Register Definitions (Continued)
VCC_LDO5 VOLTAGE CONTROL REGISTER (L5VCR) 8h’3B
Bit
7
6
5
4
3
2
1
0
Designation
Reset Value
Reserved
LDO 5 Output Voltage (L5OV)
0
0
0
0
0
0
1
0
VCC_LDO5 VOLTAGE CONTROL REGISTER (L5VCR) 8h’3B DEFINITIONS
Bit
Access
Name
Description
7:5
...
...
Reserved
Data Code
Output Voltage
4:0
R/W
B1OV
4h’0
4h’1
4h’2
4h’3
4h’4
4h’5
4h’6
4h’7
4h’8
4h’9
4h’A
4h’B
4h’C
4h’D
4h’E
4h’F
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.50
1.80
1.90
2.50
2.80
3.00
3.30
Serial interface register selection codes (Bold face voltages are default values).
Register Programming Examples
Example 1. Setting register 8h’12 value to 8h’3E’ will enable LDOs 1–5.
Example 2. Setting register 8h’39 to 8h’CC’ will set LDOs 1 and 2 to 3.0V. These voltages will appear at the LDO outputs if the
corresponding LDO has been enabled. Programming a voltage value to a LDO, which is off, will affect the LDO output voltage
after the LDO is enabled. Enabling and programming the output voltage are separate operations.
www.national.com
32
2
I C Register Definitions (Continued)
I2C DVM TIMING FOR VCC APPS (Buck 1)
20180718
LP3971 Controls
DIGITAL INTERFACE CONTROL SIGNALS
Signal
SYS_EN
Definition
Active State
High
Signal Direction
Input
High Voltage Power Enable
PWR_EN
SCL
Low Voltage Power Enable
High
Input
Serial Bus Clock Line
Clock
Input
SDA
Serial Bus Data Line
Bidirectional
Input
nRSTI
Forces an Unconditional Hardware Reset
Forces an Unconditional Hardware Reset
Main Battery Removed or Discharged Indicator
Wakeup Input to CPU
Low
Low
nRSTO
Output
nBATT_FLT
PWR_ON
nTEST_JIG
SPARE
Low
Output
High
Low
Input
Wakeup Input to CPU
Input
Wakeup Input to CPU
High/Low*
High
-/Low
-
Input
EXT_WAKEUP
GPIO1/nCHG_EN
Wake-Up Output for Application Processor
General Purpose I/O/External Back-Up Battery Charger
General Purpose I/O
Output
Bidirectional/Input
Bidirectional
GPIO2
*
POWER DOMAIN ENABLES
LDO_RTC TRACKING (nIO_TRACK)
LP3971 has a tracking function (nIO_TRACK). When en-
abled, LDO_RTC voltage will track LDO1 voltage within 200
mV down to 2.8V when LDO1 is enabled. This function can
be switched on/off by BPTR (8h’0E) register bit.
PMU Output
LDO_RTC
LDO1
HW Enable
SW Enable
-
-
SYS_EN
LDO1_EN
LDO2_EN
LDO3_EN
LDO4_EN
LDO5_EN
B1_EN
LDO2
SYS_EN
LDO4, LDO5 AND BUCK 2 ENABLE SELECTION
(LDO4_ESEL, LDO5_ESEL AND BUCK2_ESEL)
LDO3
SYS_EN
LDO4
PWR_EN/SYS_EN
PWR_EN/SYS_EN
PWR_EN
LDO4, 5 and BUCK2 power domain enable is possible to
change between SYS_EN and PWR_EN by register bits.
LDO5
BUCK1
BUCK2
BUCK3
WAKE-UP FUNCTIONALITY (PWR_ON, nTEST_JIG,
SPARE AND EXT_WAKEUP)
SYS_EN/PWR_EN
SYS_EN
B2_EN
B3_EN
Three input pins can be used to assert wakeup output for 10
ms for application processor notification to wakeup. SPARE
input can be programmed through I2C compatible interface
33
www.national.com
de-bounce filtering. Furthermore PWR_ON have distinguish-
ing between short and long (∼1s) pulses (push button input).
LP3971 also has an internal Thermal Shutdown early warn-
ing that generates a wakeup to the system also. This is
generated usually at 125˚C.
LP3971 Controls (Continued)
to be active low or high (SPARE bit, Default is active low ‘1’).
A reason for wakeup event can be read through I2C compat-
ible interface also. Additionally wakeup inputs have 30 ms
20180719
BATTERY SWITCH AND BACK UP BATTERY CHARGER
WAKEUP Register Bits
Reason for WAKEUP
SPARE
When Back-Up battery is connected but main battery re-
moved or voltage too low, LP3971 uses Back-Up Battery for
generating LDO_RTC voltage. When Main Battery is avail-
able the battery switch changes main battery for LDO_RTC
voltage. When Main battery voltage is too low or removed
nBATT_FLT is asserted to system acknowledge. If no back
up battery exists, the battery switch to back up can be
switched off by nBU_BAT_EN bit. User can set the battery
fault determination voltage and battery charger termination
voltage via I2C compatible interface. Enabling of back up
battery charger can be done via serial interface
(nBAT_CHG_EN) or external charger enable pin
(nCHG_EN). Pin 29 is set as external charger enable input
by default.
WUP0
WUP1
WUP2
WUP3
TSD_EW
TEST_JIG
PWR_ON Short Pulse
PWR_ON Long Pulse
TSD Early Warning
INTERNAL THERMAL SHUTDOWN PROCEDURE
Thermal shutdown is build to generate early warning (typ.
125˚C) which triggers the EXT_WAKEUP for the processor
acknowledge. When
a thermal shutdown triggers (typ.
160˚C) the PMU will reset the system until the device cools
down.
www.national.com
34
input, output or hi-Z mode. Inputs value can be read via
serial interface (GPI1,2 bits). The pin 29 functionality needs
to be set to GPIO by serial interface register bit
nEXTCHGEN.
LP3971 Controls (Continued)
GENERAL PURPOSE I/O FUNCTIONALITY (GPIO1 AND
GPIO2)
LP3971 has 2 general purpose I/Os for system control. I2C
compatible interface will be used for setting any of the pins to
LP3971 GPIO Control Table
Controls
Port Function
Reg.
batmonchg
Function
< >
1
< >
0
GPIO1
GPIO1
nextchgen_sel
bucen
GPIO1
Input = 0
Input = 1
X
gpin 1
X
X
1
X
0
1
0
1
X
X
0
X
0
0
1
1
1
1
1
X
0
0
0
0
0
o
0
0
0
Enabled
Not Enabled
X
1
X
Enabled
X
X
X
X
HiZ
0
Input
0
>
Input (dig)-
Output = 0
Output= 1
0
< >
1
< >
0
GPIO2
GPIO2
Factory fm disabled
GPIO_tstiob
GPIO2
HiZ
gpin2
0
1
0
1
0
0
1
1
1
1
1
1
0
Input
0
>
Input (dig)-
Output = 0
Output = 1
0
The LP3971 Back Up Charger can be enabled/disabled by
two separate mechanisms. They are; 1) A dedicated control
register bit named BUCEN (Register 0B Bit 2) and 2) GPIO1
input Pin 29, when configured for charger control.
bit is asserted (Default state), GPIO1 is charger control.
When this bit is de-asserted, charger enable is deter-
mined only by the state of control register bit BUCEN.
•
One additional feature of the charger enable is when the
main battery voltage Vin (Pin 6) is less than the back up
battery voltage Vin BUBATT (Pin 15), The charger will
automatically disable regardless of the input received
from BUCEN or GPIO1.
Description of this operation is as follows:
•
In the default state, the BUCEN bit is not asserted, and
GPIO1 is configured as charger control. High level ap-
plied to GPIO1 will disable the back up charger, Low level
applied to GPIO1 will enable the back up charger. There
is an internal pull up that will disable the back up charger
if GPIO1 is “open”.
REGULATED VOLTAGES OK
All the power domains have own register bit (x_OK) that
processor can read via serial interface to be sure that en-
abled powers are OK (regulating). Note that these read only
bits are only valid when regulators are settled (avoid reading
these bits during voltage change or power up).
•
•
If BUCEN bit is asserted with GPIO1 configured for
charger control, the back up charger will always be en-
abled, and GPIO1 input will have no effect.
Configuration of GPIO1 charger function is via control
register bit named BBCS (Register 0E Bit 7). When this
35
www.national.com
enables can be changed for further flexibility. Please note
that LDO1 is recommended to be used for I/Os if RTC
voltage need to track I/O voltage. Also LDO4 and LDO5 has
an own VIN pin which can be driven from a buck regulator for
higher system efficiency.
Application Note
TYPICAL CONNECTION DIAGRAMS
LP3971 is flexible for different system configurations. Differ-
ent power domains can be selected based on current and
voltage needs. Additionally Buck2 LDO4 and lDO5 default
Typical Application Diagram with Advanced Applications Processor Version “A”
20180720
www.national.com
36
Application Note (Continued)
Typical Application Diagram with PXA27x Advanced Applications Processor Version “B”
20180721
LP3971 & PXA27x START-UP
timer set to 125 mS.
6. The LP3971 enables the high-voltage power supplies.
Initial Cold Start Power On Sequence
-LDO1 power for VCC_MVT, BG, OSC13M and PLL
enabled first, followed by others if delay is on.
1. The Back up battery is connected to the PMU, power is
applied to the back-up battery pin, the RTC_LDO turns
7. Countdown timer expires; the Applications processor
asserts PWR_EN (ext. pin or I2C) to enable the low-
voltage power supplies. The processor starts the count-
down timer set to 125 mS period.
on and supplies
a stable output voltage to the
VCC_BATT pin of the Applications processor (initiating
the power-on reset event) with nRSTO asserted from the
LP3971 to the processor.
8. The Applications processor asserts PWR_EN (ext. pin or
I2C), the LP3971 enables the low-voltage regulators.
2. The Applications processor waits for the de-assertion of
nBATT_FLT to indicate system power (VIN) is available.
9. Countdown timer expires; If enabled power domains are
OK (I2C read) the power up sequence continues by
enabling the processors 13 MHz oscillator and PLL’s.
3. IF system power (Vbat) is avaliable, the LP3971 de-
asserts nBATT_FLT.
4. nRSTO de-asserts after a minimum of 50 mS.
10. The Applications processor begins the execution of
code.
5. The Applications processor asserts SYS_EN, the
LP3971 enables the system high-voltage power sup-
plies. The Applications processor starts its countdown
37
www.national.com
Application Note (Continued)
Code Start Power on Timing
20180722
POWER-ON TIMING
Symbol
Description
Min
Typ
Max
Units
mS
t1
t3
t4
t5
Delay from VCC_RTC assertion to nRSTO de-assertion
Delay from nRST de-assertion to SYS_EN assertion
Delay from SYS_EN assertion to PWR_EN assertion
Delay from PWR_EN assertion to nRSTO de-assertion
50
10
mS
125
125
mS
mS
LP3971 & PXA27x RESET SEQUENCE
Hardware Reset Sequence
plies. The Applications processor starts its countdown
timer set to 125 mS.
5. The LP3971 enables the high-voltage power supplies.
Hardware reset initiates when the nRSTI signal is asserted
(low). Upon assertion of nRST the processor enters hard-
ware reset state. The LP3971 holds the nRST low long
enough (50ms typ.) to allow the processor time to initiate the
reset state.
6. Countdown timer expires; the Applications processor
asserts PWR_EN to enable the low-voltage power sup-
plies. The processor starts the countdown timer set to
125 mS period.
7. The Applications processor asserts PWR_EN, the
LP3971 enables the low-voltage regulators.
Reset Sequence
8. Countdown timer expires; If enabled power domains are
OK (I2C read) the power up sequence continues by
enabling the processors 13 MHz oscillator and PLL’s.
1. nRSTI is asserted
2. If VBATT is above the set point the PMIC de-asserts
nBATT_FLT to indicate system power (VIN) is available.
9. The Applications processor begins the execution of
code.
3. nRSTO is asserted and will de-asserts after a minimum
of 50 mS.
4. The Applications processor asserts SYS_EN, the
LP3971 enables the system high-voltage power sup-
www.national.com
38
For both input and output capacitors, careful interpretation of
the capacitor specification is required to ensure correct de-
vice operation. The capacitor value can change greatly, de-
pending on the operating conditions and capacitor type.
Application Hints
LDO CONSIDERATIONS
External Capacitors
In particular, the output capacitor selection should take ac-
count of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance
can vary with DC bias conditions as well as temperature and
frequency of operation. Capacitor values will also show
some decrease over time due to aging. The capacitor pa-
rameters are also dependant on the particular case size,
with smaller sizes giving poorer performance figures in gen-
eral. As an example, Figure 6 shows a typical graph com-
paring different capacitor case sizes in a Capacitance vs. DC
Bias plot. As shown in the graph, increasing the DC Bias
condition can result in the capacitance value falling below
the minimum value given in the recommended capacitor
specifications table. Note that the graph shows the capaci-
tance out of spec for the 0402 case size capacitor at higher
bias voltages. It is therefore recommended that the capacitor
manufacturers’ specifications for the nominal value capacitor
are consulted for all conditions, as some capacitor sizes
(e.g. 0402) may not be suitable in the actual application.
The LP3971’s regulators require external capacitors for
regulator stability. These are specifically designed for por-
table applications requiring minimum board space and small-
est components. These capacitors must be correctly se-
lected for good performance.
Input Capacitor
An input capacitor is required for stability. It is recommended
that a 1.0 µF capacitor be connected between the LDO input
pin and ground (this capacitance value may be increased
without limit).
This capacitor must be located a distance of not more than 1
cm from the input pin and returned to a clean analogue
ground. Any good quality ceramic, tantalum, or film capacitor
may be used at the input.
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge current when connected to a low imped-
ance source of power (like a battery or a very large capaci-
tor). If a tantalum capacitor is used at the input, it must be
guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series
Resistance) on the input capacitor, but tolerance and tem-
perature coefficient must be considered when selecting the
capacitor to ensure the capacitance will remain approxi-
mately 1.0 µF over the entire operating temperature range.
Output Capacitor
The LDO’s are designed specifically to work with very small
ceramic output capacitors. A 1.0 µF ceramic capacitor (tem-
perature types Z5U, Y5V or X7R) with ESR between 5 mΩ to
500 mΩ, are suitable in the application circuit.
For this device the output capacitor should be connected
between the VOUT pin and ground.
It is also possible to use tantalum or film capacitors at the
device output, COUT (or VOUT), but these are not as attrac-
tive for reasons of size and cost (see the section Capacitor
Characteristics).
20180723
FIGURE 6. Graph Showing a Typical Variation in
Capacitance vs. DC Bias
The output capacitor must meet the requirement for the
minimum value of capacitance and also have an ESR value
that is within the range 5 mΩ to 500 mΩ for stability.
The ceramic capacitor’s capacitance can vary with tempera-
ture. The capacitor type X7R, which operates over a tem-
perature range of −55˚C to +125˚C, will only vary the capaci-
tance to within 15%. The capacitor type X5R has a similar
tolerance over a reduced temperature range of −55˚C to
+85˚C. Many large value ceramic capacitors, larger than
1 µF are manufactured with Z5U or Y5V temperature char-
acteristics. Their capacitance can drop by more than 50% as
the temperature varies from 25˚C to 85˚C. Therefore X7R is
recommended over Z5U and Y5V in applications where the
ambient temperature will change significantly above or be-
low 25˚C.
No-Load Stability
The LDO’s will remain stable and in regulation with no ex-
ternal load. This is an important consideration in some cir-
cuits, for example CMOS RAM keep-alive applications.
Capacitor Characteristics
The LDO’s are designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer. For
capacitance values in the range of 0.47 µF to 4.7 µF, ceramic
capacitors are the smallest, least expensive and have the
lowest ESR values, thus making them best for eliminating
high frequency noise. The ESR of a typical 1.0 µF ceramic
capacitor is in the range of 20 mΩ to 40 mΩ, which easily
meets the ESR requirement for stability for the LDO’s.
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
0.47 µF to 4.7 µF range.
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum
capacitor with an ESR value within the stable range, it would
39
www.national.com
Method 2:
Application Hints (Continued)
A more conservative and recommended approach is to
choose an inductor that has saturation current rating greater
than the max current limit of 2.1A.
have to be larger in capacitance (which means bigger and
more costly) than a ceramic capacitor with the same ESR
value. It should also be noted that the ESR of a typical
tantalum will increase about 2:1 as the temperature goes
from 25˚C down to −40˚C, so some guard band must be
allowed.
A 2.2 µH inductor with a saturation current rating of at least
1150 mA is recommended for most applications. The induc-
tor’s resistance should be less than 0.3Ω for good efficiency.
Table 1 lists suggested inductors and suppliers. For low-cost
applications, an unshielded bobbin inductor could be consid-
ered. For noise critical applications, a toroidal or shielded
bobbin inductor should be used. A good practice is to lay out
the board with overlapping footprints of both types for design
flexibility. This allows substitution of a low-noise shielded
inductor, in the event that noise from low-cost bobbin models
is unacceptable.
BUCK CONSIDERATIONS
Inductor Selection
There are two main considerations when choosing an induc-
tor; the inductor should not saturate, and the inductor current
ripple is small enough to achieve the desired output voltage
ripple. Different saturation current rating specs are followed
by different manufacturers so attention must be given to
details. Saturation current ratings are typically specified at
25˚C so ratings at max ambient temperature of application
should be requested from manufacturer.
INPUT CAPACITOR SELECTION
A ceramic input capacitor of 10 µF, 6.3V is sufficient for most
applications. Place the input capacitor as close as possible
to the VIN pin of the device. A larger value may be used for
improved input voltage filtering. Use X7R or X5R types, do
not use Y5V. DC bias characteristics of ceramic capacitors
must be considered when selecting case sizes like 0805 and
0603. The input filter capacitor supplies current to the PFET
switch of the converter in the first half of each cycle and
reduces voltage ripple imposed on the input power source. A
ceramic capacitor’s low ESR provides the best noise filtering
of the input voltage spikes due to this rapidly changing
current. Select a capacitor with sufficient ripple current rat-
ing. The input current ripple can be calculated as:
There are two methods to choose the inductor saturation
current rating.
Method 1:
The saturation current is greater than the sum of the maxi-
mum load current and the worst case average to peak
inductor current. This can be written as
•
•
•
•
IRIPPLE: Average to peak inductor current
IOUTMAX: Maximum load current (1500 mA)
VIN: Maximum input voltage in application
L: Min inductor value including worst case tolerances
(30% drop can be considered for method 1)
The worst case is when VIN = 2 * VOUT
•
•
f: Minimum switching frequency (1.6 MHz)
VOUT: Output voltage
TABLE 1. Suggested Suppliers
Dimensions LxWxH (mm)
Vendor
Toko
D.C.R (Max)
70 mΩ
2.8 x 3.0 x 1.2
3.0 x 3.0 x 1.2
3.76 x 4.2 x 1.8
4.45 x 6.6 x 2.92
3.3 x 3.3 x 1.4
Toko
160 mΩ
70 mΩ
Coilcraft
Coilcraft
Coilcraft
70 mΩ
200 mΩ
OUTPUT CAPACITOR SELECTION
The output voltage ripple is caused by the charging and
discharging of the output capacitor and also due to its ESR
and can be calculated as:
Use a 10 µF, 6.3V ceramic capacitor. Use X7R or X5R types,
do not use Y5V. DC bias characteristics of ceramic capaci-
tors must be considered when selecting case sizes like 0805
and 0603. DC bias characteristics vary from manufacturer to
manufacturer and dc bias curves should be requested from
them as part of the capacitor selection process. The output
filter capacitor smoothes out current flow from the inductor to
the load, helps maintain a steady output voltage during
transient load changes and reduces output voltage ripple.
These capacitors must be selected with sufficient capaci-
tance and sufficiently low ESR to perform these functions.
Voltage peak-to-peak ripple due to capacitance can be ex-
pressed as follows
Voltage peak-to-peak ripple due to ESR can be expressed
as follows
VPP-ESR = (2 * IRIPPLE) * RESR
www.national.com
40
Note that the output voltage ripple is dependent on the
inductor current ripple and the equivalent series resistance
of the output capacitor (RESR).
Application Hints (Continued)
Because these two components are out of phase the rms
value can be used to get an approximate value of peak-to-
peak ripple.
The RESR is frequency dependent (as well as temperature
dependent); make sure the value used for calculations is at
the switching frequency of the part.
Voltage peak-to-peak ripple, root mean squared can be ex-
pressed as follows
TABLE 2. Suggested Capacitor and their Suppliers
Type Vendor Voltage
Model
Case Size
Inch (mm)
10 µF
GRM21BR60J106K
JMK212BJ106K
Ceramic, X5R
Murata
6.3V
6.3V
6.3V
0805 (2012)
0805 (2012)
0805 (2012)
Ceramic, X5R
Ceramic, X5R
Taiyo-Yuden
TDK
C2012X5R0J106K
per fill as a pseudo-ground plane. Then, connect this to
the ground-plane (if one is used) with several vias. This
reduces ground-plane noise by preventing the switching
currents from circulating through the ground plane. It
also reduces ground bounce at the converter by giving it
a low-impedance ground connection.
Board Layout Considerations
PC board layout is an important part of DC-DC converter
design. Poor board layout can disrupt the performance of a
DC-DC converter and surrounding circuitry by contributing to
EMI, ground bounce, and resistive voltage loss in the traces.
These can send erroneous signals to the DC-DC converter
IC, resulting in poor regulation or instability.
4. Use wide traces between the power components and for
power connections to the DC-DC converter circuit. This
reduces voltage errors caused by resistive losses across
the traces.
Good layout for the converters can be implemented by fol-
lowing a few simple design rules.
1. Place the converters, inductor and filter capacitors close
together and make the traces short. The traces between
these components carry relatively high switching cur-
rents and act as antennas. Following this rule reduces
radiated noise. Special care must be given to place the
input filter capacitor very close to the VIN and GND pin.
5. Route noise sensitive traces, such as the voltage feed-
back path, away from noisy traces between the power
components. The voltage feedback trace must remain
close to the converter circuit and should be direct but
should be routed opposite to noisy components. This
reduces EMI radiated onto the DC-DC converter’s own
voltage feedback trace. A good approach is to route the
feedback trace on another layer and to have a ground
plane between the top layer and layer on which the
feedback trace is routed. In the same manner for the
adjustable part it is desired to have the feedback divid-
ers on the bottom layer.
2. Arrange the components so that the switching current
loops curl in the same direction. During the first half of
each cycle, current flows from the input filter capacitor
through the converter and inductor to the output filter
capacitor and back through ground, forming a current
loop. In the second half of each cycle, current is pulled
up from ground through the converter by the inductor to
the output filter capacitor and then back through ground
forming a second current loop. Routing these loops so
the current curls in the same direction prevents mag-
netic field reversal between the two half-cycles and re-
duces radiated noise.
6. Place noise sensitive circuitry, such as radio RF blocks,
away from the DC-DC converter, CMOS digital blocks
and other noisy circuitry. Interference with noise-
sensitive circuitry in the system can be reduced through
distance.
3. Connect the ground pins of the converter and filter ca-
pacitors together using generous component-side cop-
41
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
40-Pin LLP
NS Drawing SQF40A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
Leadfree products are RoHS compliant.
National Semiconductor
Americas Customer
Support Center
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
National Semiconductor
Asia Pacific Customer
Support Center
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
www.national.com
相关型号：
LP3971SQ-B510
IC 3-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC40, 5 X 5 MM, LLP-40, Power Management Circuit
NSC
©2020 ICPDF网 联系我们和版权申明