LP3987 [NSC]
Micropower micro SMD 150 mA Ultra Low-Dropout CMOS Voltage Regulators with sleep MODE; 微微型SMD 150毫安超低压差CMOS电压稳压器，带有睡眠模式
| 型号： | LP3987 |
| 厂家： | 
National Semiconductor |
| 描述： | Micropower micro SMD 150 mA Ultra Low-Dropout CMOS Voltage Regulators with sleep MODE |
| 文件： | 总17页 (文件大小：530K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2003
LP3987
Micropower micro SMD 150 mA Ultra Low-Dropout
CMOS Voltage Regulators with sleep MODE
General Description
Features
n Miniature 5-I/O micro SMD package
The LP3987 is a 150mA fixed output voltage regulator with
very low dropout voltage designed specially to meet require-
ments of battery-powered applications. The additional sleep
MODE feature will reduce current consumption during
standby operation to prolong the usage of battery.
n Stable with ceramic and high quality tantalum output
capacitors
n Logic controlled enable
n Thermal Shutdown and short-circuit current limit
Dropout Voltage: 100mV maximum dropout with 150mA
load.
Key Specifications
Shutdown: Less than 1µA quiescent current.
n 2.7 to 6.0V input range
Sleep Mode: Typically 14µA quiescent current during sleep
MODE to reduce battery consumption.
n Guaranteed 150 mA output current
n 1µA quiescent current on shutdown
n 100 mV maximum dropout with 150 mA load
n 50dB PSRR at 10KHz
Enhanced Stability: The LP3987 is stable with minimum
1µF 20% low ESR ceramic output capacitor as low as 5mΩ
and high quality tantalum capacitors.
n Sleep MODE features
The LP3987 is available in thin and thick 5 Bump micro SMD
package. Performance is specified for −40˚C to 125˚C.
n Over temperature & over current protection
n −40˚C to +125˚C junction temperature range for
operation
This device is available with output voltage options of 2.6V,
2.8V, & 2.85V. For other voltage options, please contact
National Semiconductor Corporation.
Applications
n CDMA cellular handsets
n Wideband CDMA cellular handsets
n GSM cellular handsets
n Portable information appliances
n µP/DSP Power Supplies
n Digital Cameras
n SRAM Backup
Typical Application Circuit
20022201
© 2003 National Semiconductor Corporation
DS200222
www.national.com
Block Diagram
LP3987
20022202
Connection Diagram
20022271
Top View
5 I/O micro SMD Package
See NS Package Number BPA05/TLA05/BLA05
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2
Pin Descriptions
Name
micro SMD*
Function
Enable Input Logic, Enable High
Common Ground
VEN
GND
VOUT
VIN
A1
B2
C1
C3
A3
Output voltage of the LDO
Input voltage of the LDO
Power Mode Control, Active = 1, Sleep
Mode = 0
MODE
* The pin numbering scheme for the micro SMD package was revised in April, 2002 to conform to JEDEC standard. Only the pin numbers
were revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering
scheme had VEN as pin 1, GND as pin 2, VOUT as pin 3, VIN as pin 4, and MODE as pin 5.
Ordering Information
BP refers to a 0.170mm bump size with package height of 0.9mm
Output
Voltage (V)
2.85*
LP3987 Supplied as 250
Units, Tape and Reel
LP3987 Supplied as 3000
Units, Tape and Reel
LP3987IBPX-2.85
Grade
STD
LP3987IBP-2.85
* Please contact National Semiconductor for availability
BL refers to a 0.300mm bump size with package height of 0.9mm
Output
Voltage (V)
2.85
LP3987 Supplied as 250
Units, Tape and Reel
LP3987 Supplied as 3000
Units, Tape and Reel
LP3987IBLX-2.85
Grade
STD
LP3987IBL-2.85
* Please contact National Semiconductor for availability
TL refers to a 0.300mm bump size with package height of 0.6mm
Output
Voltage (V)
2.5
LP3987 Supplied as 250
Units, Tape and Reel
LP3987ITL-2.5
LP3987 Supplied as 3000
Units, Tape and Reel
LP3987ITLX-2.5
Grade
STD
STD
STD
STD
STD
2.6
LP3987ITL-2.6
LP3987ITLX-2.6
2.8
LP3987ITL-2.8
LP3987ITLX-2.8
2.85
LP3987ITL-2.85
LP3987ITL-3.0
LP3987ITLX-2.85
LP3987ITLX-3.0
3.0*
* Please contact National Semiconductor for availability
3
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Absolute Maximum Ratings (Notes 1,
2)
ESD (Note 4)
Human Body Model
2KV
Machine Model
200V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Maximum Power Dissipation (Note 3)
θJA (micro SMD small bump)
255˚C/W
VIN
−0.3 to 6.5V
−0.3 to 6.5V
V
EN, VMODE
Operating Ratings (Notes 1, 2)
VOUT
−0.3V to(V
+
IN
VIN
VOUT+ 200mV to 6V
0.3V) ≤ 6.5
V
EN, VMODE
0 to 6.0V
Storage Temperature
−65˚C to +150˚C
Junction Temperature
−40˚C to +125˚C
392mW at 25˚C
Maximum Power Dissipation (Note 3)
Electrical Characteristics
Unless otherwise specified: VEN = 1.8V, MODE = 1.8V, VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF. Typical
values and limits appearing in standard typeface are for TJ = 25˚C. Limits appearing in boldface type apply over the entire
junction temperature range for operation, −40˚C to +125˚C. (Note 10) (Note 11)
Limit
Symbol
Parameter
Conditions
IOUT = 1mA, 25˚C
Typ
Units
Min
-2
Max
2
Output Voltage
Tolerance
% of
VOUT(nom)
IOUT = 1mA
−3
3
Line Regulation Error
VIN = (VOUT(nom) + 0.5V) to
6.0V,
−0.1
0.1
%/V
∆VOUT
IOUT = 1 mA
Load Regulation Error
Dropout Voltage
(Note 6)
IOUT = 1mA to 150 mA
IOUT = 1mA
0.0004
0.002
2
%/mA
mV
0.4
60
IOUT = 150mA
100
+100
∆VOUT(SLEEP) Output Voltage
difference at MODE =
MODE = 0V, (Note 7)
-150
mV
0V
Transient
Response
Line Transient
Response (Note 5)
MODE = 1.8V, ILOAD
=
21
mVpp
mVpk
100mA, TRISE = TFALL
10µS,
=
VIN = 600mV
AC Square
P-P
wave, (Note 8)
Load Transient
MODE = 1.8V, COUT = 4.7µF,
TRISE = TFALL = 100nS,
VIN = 3.1V, 3.6V, 4.2V, (Notes
9, 12)
100
Response (Note 5)
VIN = VOUT(nom) + 1V, MODE
50
10
<
= 1.8V, f = 10 kHz,
IOUT = 1mA
Power Supply Rejection
Ratio (Note 5)
PSRR
dB
µA
VIN = VOUT(nom) + 1V, MODE
<
= 0V, f = 10 kHz,
IOUT = 1mA
IQ(ON)
Quiescent Current
MODE = 1.8V, IOUT = 0mA,
VIN = 4.2V
85
120
200
MODE = 1.8V, IOUT = 150mA,
VIN = 4.2V
160
IQ(OFF)
Quiescent Current
Current in Standby
Mode
ENABLE = 0V, VIN = 4.2V
MODE = 0V, IOUT = 50µA, VIN
= 4.2V
1
3
µA
µA
IQ(SLEEP)
14
21
ISC
Short Circuit Current
Limit (Note 5)
Output Grounded
600
mA
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4
Electrical Characteristics (Continued)
Unless otherwise specified: VEN = 1.8V, MODE = 1.8V, VIN = VOUT(nom) + 0.5V, CIN = 1 µF, IOUT = 1mA, COUT = 1 µF. Typical
values and limits appearing in standard typeface are for TJ = 25˚C. Limits appearing in boldface type apply over the entire
junction temperature range for operation, −40˚C to +125˚C. (Note 10) (Note 11)
Limit
Symbol
Parameter
Conditions
Output Grounded
Typ
Units
Min
150
3
Max
43
ISC(SLEEP)
Short Circuit Current in
Sleep MODE
28
mA
IOUT(ON)
Maximum Output
Current at MODE =
1.8V
MODE = 1.8V
MODE = 0V
mA
IOUT(SLEEP)
en
Maximum Output
Current at MODE = 0V
Output Noise Voltage,
(Note 5)
mA
BW = 10 Hz to 100 kHz,
COUT = 1µF
70
µVrms
TSHUTDOWN
Shutdown Temperature
(Note 5)
Sleep MODE = 1.8V
155
˚C
Logic Control Characteristics
IEN
VIL
VIH
Maximum Input Current
VEN = 0 and VIN= 6.0V
VIN = 3.05 to 6V
0.015
µA
V
at EN
Logic Low Input
Threshold
0.5
0.5
Logic High Input
Threshold
VIN = 3.05 to 6V
1.2
1.2
V
Logic Low Input
Threshold
VIN = 3.05 to 6V
VMODE_L
VMODE_H
IMODE
V
V
Logic High Input
Threshold
VIN = 3.05 to 6V
Maximum Input Current
at VMODE
VMODE = 0 and VIN = 6.0V
µA
0.015
170
0.5
Timing Characteristics
Turn on Time (On
MODE = 1.8V, COUT = 4.7µF
MODE = 0V, COUT = 4.7µF
250
5
TON
µs
Mode), (Notes 5, 13)
Turn on Time (Sleep
Mode), (Note 5), (Note
14)
TSLEEP
ms
Sleep to On Mode
Settle Time, (Note 5),
(Note 15)
COUT = 4.7µF, Enable = 1.8V
300
TMODE
µs
200
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula:
PD = (TJ - TA)/θJA
,
Where T is the junction temperature, T is the ambient temperature, and θ is the junction-to-ambient thermal resistance. For instant, if V in target application
J
A
JA
IN
*
is 4.2V and worse case current consumption is 90mA. Therefore P
= (4.2-2.7) 0.09 =135mW. With P
is 135mW, T
is 125˚C
MAX_DISSIPATION
MAX_DISSIPATION
Jmax
and worse case ambient temperature (TA ) in target application is 85˚C, θ = (125-85)/0.135 = 296˚C/W.
JA
Note 4: The human body model is 100pF discharged through 1.5kΩ.
Note 5: This electrical specification is guaranteed by design.
5
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Electrical Characteristics (Continued)
Note 6: Dropout voltage is defined as the input to output voltage differential at which the output voltage falls to 100mV below the nominal output voltage. V less
IN
than minimum operating voltage may be used for test purposes.
Note 7: On/Sleep Mode voltage tolerance and current capability requirement.
20022205
Note 8: Line Transient response requirement:
20022206
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6
Electrical Characteristics (Continued)
Note 9: Load Transient response requirement:
20022207
Note 10: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with T = 25˚C. All hot and cold limits
J
are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Note 11: The nominal output voltage, which is labeled V
, is the output voltage measured with the input 0.5V above V
OUT(nom)
and a 1mA load.
OUT(nom)
Note 12: During transient recovery, output voltage should not be oscillating.
Note 13: T
Note 14: T
Note 15: T
is measured from rising edge of Enable with MODE = 1.8V to when V
reaches 95% of final value.
OUT
ON
is measured from rising edge of Enable with MODE = 0V to when V
reaches 95% of final value.
OUT
SLEEP
MODE
is measured from rising edge of MODE with ENABLE = 1.8V to time before full current capability.
7
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Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN
= VOUT(nom) + 0.5V, TA = 25˚C, Enable pin is tied to VIN, MODE = 1.8V.
@
@
Ground Current TA = 40˚C
Ground Current TA = 25˚C
20022228
20022226
@
Ground Current TA = 85˚C
Dropout Voltage vs Load Current
20022227
20022229
Ripple Rejection (VIN = VOUT(nom) + 1V,
CIN = COUT = 1µF, IL = 1mA)
Ripple Rejection (CIN = COUT = 1µF, IL = 1mA)
20022208
20022209
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Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN
=
VOUT(nom) + 0.5V, TA = 25˚C, Enable pin is tied to VIN, MODE = 1.8V. (Continued)
@
@
TSLEEP MODE = 0V, COUT = 1µF,
TSLEEP MODE = 0V, COUT = 1µF,
IL = 1mA
IL = 1mA
20022213
20022215
20022217
20022214
20022216
20022218
@
@
TON MODE = 1.8V, COUT = 1µF,
TON MODE = 1.8V, COUT = 1µF,
IL = 150mA
IL = 150mA
@
@
TSLEEP MODE = 0V, COUT = 4.7µF,
TSLEEP MODE = 0V, COUT = 4.7µF,
IL = 1mA
IL = 1mA
9
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Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN
=
VOUT(nom) + 0.5V, TA = 25˚C, Enable pin is tied to VIN, MODE = 1.8V. (Continued)
@
@
TON MODE = 1.8V, COUT = 4.7µF,
TON MODE = 1.8V, COUT = 4.7µF,
IL = 150mA
IL = 150mA
20022219
20022220
@
@
TMODE Measurement VIN = 3.05V
TMODE Measurement VIN = 3.6V
20022225
20022224
@
TMODE Measurement VIN = 4.2V
Output Short Circuit Current
20022222
20022223
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Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN
=
VOUT(nom) + 0.5V, TA = 25˚C, Enable pin is tied to VIN, MODE = 1.8V. (Continued)
@
Load Transient Response VIN = 3.1V
Output Short Circuit Current
20022221
20022273
@
@
Load Transient Response VIN = 3.6V
Load Transient Response VIN = 3.35V
20022230
20022231
@
@
Load Transient Response VIN = 4.2V
Load Transient Response VIN = 3.1V, COUT = 1µF
20022232
20022272
11
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Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN
=
VOUT(nom) + 0.5V, TA = 25˚C, Enable pin is tied to VIN, MODE = 1.8V. (Continued)
@
@
Load Transient Response VIN = 3.35V, COUT = 1µF
Load Transient Response VIN = 4.2V, COUT = 1µF
20022233
20022234
@
Load Transient Response VIN = 3.6V, COUT = 1µF
Output Voltage Change vs Temperature
20022235
20022236
Line Transient Response
Line Transient Response
20022265
20022266
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Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1 µF Ceramic, VIN
=
VOUT(nom) + 0.5V, TA = 25˚C, Enable pin is tied to VIN, MODE = 1.8V. (Continued)
Line Transient Response
Line Transient Response
20022267
20022268
Line Transient Response
Line Transient Response
20022269
20022270
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Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
1µF to 4.7µF range.
Application Hints
EXTERNAL CAPACITORS
Like any low-dropout regulator, the LP3987 requires external
capacitors for regulator stability. The LP3987 is specifically
designed for portable applications requiring minimum board
space and smallest components. These capacitors must be
correctly selected for good performance.
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum
capacitor with an ESR value within the stable range, it would
have to be larger in capacitance (which means bigger and
more costly ) than a ceramic capacitor with the same ESR
value. It should also be noted that the ESR of a typical
tantalum will increase about 2:1 as the temperature goes
from 25˚C down to −40˚C, so some guard band must be
allowed.
INPUT CAPACITOR
An input capacitance of ) 1µF is required between the
LP3987 input pin and ground (the amount of the capacitance
may be increased without limit).
This capacitor must be located a distance of not more than
1cm from the input pin and returned to a clean analog
ground. Any good quality ceramic, tantalum, or film capacitor
may be used at the input.
ON/OFF INPUT OPERATION
The LP3987 is turned off by pulling the VEN pin low, and
turned on by pulling it high. If this feature is not used, the VEN
pin should be tied to VIN to keep the regulator output on at all
time. To assure proper operation, the signal source used to
drive the VEN input must be able to swing above and below
the specified turn-on/off voltage thresholds listed in the Elec-
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge current when connected to a low-
impedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
be guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
trical Characteristics section under VIL and VIH
.
MODE OPERATION
There are no requirements for the ESR on the input capaci-
tor, but tolerance and temperature coefficient must be con-
sidered when selecting the capacitor to ensure the capaci-
tance will be ) 1µF over the entire operating temperature
range.
The LP3987 enters sleep mode by pulling MODE = 0V
externally to reduce current during standby operation. During
sleep mode, LP3987 consumes only 14µA of quiescent cur-
rent and supplies up to 3mA of current. The device returns to
active mode by pulling MODE = 1.8V. If this function is not
OUTPUT CAPACITOR
used, the MODE pin should be tied to VIN
.
The LP3987 is designed specifically to work with very small
ceramic output capacitors. A ceramic capacitor (dielectric
types Z5U, Y5V or X7R) in 1 to 4.7 µF range with 5mΩ to
500mΩ ESR range is suitable in the LP3987 application
circuit.
THERMAL PROTECTION
The LP3987 has internal thermal protection circuitry to dis-
able the internal pass transistor if the junction temperature
exceeds 125˚C to allow the device to cool down. The pass
transistor will turn on when temperature falls below the maxi-
mum operating junction temperature of 125˚C. This feature
is designed to protect the device in the event of fault condi-
tions. For normal operation, it is suggested to limit the device
junction temperature to less than 125˚C.
It may also be possible to use tantalum or film capacitors at
the output, but these are not as attractive for reasons of size
and cost (see next section Capacitor Characteristics).
The output capacitor must meet the requirement for mini-
mum amount of capacitance and also have an ESR (Equiva-
lent Series Resistance) value which is within a stable range
(5 mΩ to 500 mΩ).
MICRO SMD MOUNTING
The micro SMD package requires specific mounting tech-
niques which are detailed in National Semiconductor Appli-
cation Note (AN-1112). Referring to the section Surface
Mount Technology (SMT) Assembly Considerations, it
should be noted that the pad style which must be used with
the 5 pin package is NSMD (non-solder mask defined) type.
NO-LOAD STABILITY
The LP3987 will remain stable and in regulation with no
external load. This is specially important in CMOS RAM
keep-alive applications.
For best results during assembly, alignment ordinals on the
PC board may be used to facilitate placement of the micro
SMD device.
CAPACITOR CHARACTERISTICS
The LP3987 is designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer: for
capacitance values in the range of 1µF to 4.7µF range,
ceramic capacitors are the smallest, least expensive and
have the lowest ESR values (which makes them best for
eliminating high frequency noise). The ESR of a typical 1µF
ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which
easily meets the ESR requirement for stability by the
LP3987. The ceramic capacitor’s capacitance can vary with
temperature. Most large value ceramic capacitors () 2.2µF)
are manufactured with Z5U or Y5V temperature characteris-
tics, which results in the capacitance dropping by more than
50% as the temperature goes from 25˚C to 85˚C.
MICRO SMD LIGHT SENSITIVITY
Exposing the micro SMD device to direct sunlight will cause
misoperation of the device. Light sources such as Halogen
lamps can effect electrical performance if brought near to the
device. The wavelengths which have most detrimental effect
are reds and infra-reds, which means that the fluorescent
lighting used inside most buildings has very little effect on
performance. A micro SMD test board was brought to within
1cm of a fluorescent desk lamp and the effect on the regu-
lated output voltage was negligible, showing a deviation of
less than 0.1% from nominal.
A better choice for temperature coefficient in a ceramic
capacitor is X7R, which holds the capacitance within 15%.
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14
Physical Dimensions inches (millimeters) unless otherwise noted
micro SMD, 5 Bump, Package (TLA05)
NS Package Number TLA05ADA
The dimensions for X1, X2 and X3 are given as:
X1 = 1.006 +/− 0.03mm
X2 = 1.438 +/− 0.03mm
X3 = 0.600 +/− 0.075mm
15
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
micro SMD, 5 Bump, Package (BLA05)
NS Package Number BLA05ADC
The dimensions for X1, X2 and X3 are given as:
X1 = 1.006 +/− 0.03mm
X2 = 1.438 +/− 0.03mm
X3 = 0.995 +/− 0.10mm
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16
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
micro SMD, 5 Bump, Package (BPA05)
NS Package Number BPA05CMC
The dimensions for X1, X2 and X3 are given as:
X1 = 0.828 +/− 0.03mm
X2 = 1.387 +/− 0.03mm
X3 = 0.900 +/− 0.10mm
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Support Center
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Fax: +49 (0) 180-530 85 86
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