LP5951MFX-2.0 [NSC]
Micropower, 150mA Low-Dropout CMOS Voltage Regulator; 微器，150mA低压降CMOS电压稳压器
| 型号： | LP5951MFX-2.0 |
| 厂家： | 
National Semiconductor |
| 描述： | Micropower, 150mA Low-Dropout CMOS Voltage Regulator |
| 文件： | 总10页 (文件大小：606K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2006
LP5951
Micropower, 150mA Low-Dropout CMOS Voltage
Regulator
General Description
Features
n Excellent line transient response: 2mV typ.
n Excellent PSRR: -60dB at 1kHz typ.
n Low quiescent current of 29µA typ.
n 1.8 to 5.5V input voltage range
n Small SOT23-5 package
The LP5951 regulator is designed to meet the requirements
of portable, battery-powered systems providing a regulated
output voltage and low quiescent current. When switched to
shutdown mode via a logic signal at the Enable pin, the
power consumption is reduced to virtually zero.
The LP5951 is designed to be stable with small 1µF/1.5µF
ceramic capacitors.
n Fast turn-on time of 30µs typ.
<
n Typ. 1nA quiescent current in shutdown
The LP5951 also features internal protection against short-
circuit currents and over-temperature conditions.
n Guaranteed 150mA output current
n Output voltage range: 1.3V to 3.3V
Performance is specified for a -40˚C to 125˚C temperature
range.
n Logic controlled enable 0.4V/0.9V
n Good load transient response of 50mVpp typ.
n Thermal-overload and short-circuit protection
n -40˚C to +125˚C junction temperature range
The device is currently available in SOT23-5 package and
will be available in SC70-5 package soon.
The device is available in fixed output voltages in the range
of 1.3V to 3.3V. For availability, please contact your local
NSC sales office.
Applications
n General purpose
Typical Application Circuit
20136201
© 2006 National Semiconductor Corporation
DS201362
www.national.com
Connection Diagram
5-Lead Small Outline Package
SOT23-5 (MF)
20136202
Top View
See NS Package Number MF05A
Pin Descriptions
Pin
Number
Pin Name
VIN
Description
1
2
3
Input Voltage. Input range: 1.8V to 5.5V
GND
EN
Ground
Enable pin logic input: Low = shutdown, High = normal operation. This pin should not be left
floating.
4
5
NC
No internal connection
Regulated output voltage
VOUT
Order Information
For 5-Lead Small Outline Package SOT23-5 (MF)
Output
Voltage (V)
LP5951 Supplied as 1000 Units,
Tape and Reel
LP5951MF-1.3
LP5951MF-1.3
LP5951MF-1.5
LP5951MF-1.5
LP5951MF-1.8
LP5951MF-1.8
LP5951MF-2.0
LP5951MF-2.0
LP5951MF-2.5
LP5951MF-2.5
LP5951MF-2.8
LP5951MF-2.8
LP5951MF-3.0
LP5951MF-3.0
LP5951MF-3.3
LP5951MF-3.3
LP5951 Supplied as 3000 Units,
Tape and Reel
Package
Flow Marking
LKRB
LP5951MFX-1.3
LP5951MFX-1.3
LP5951MFX-1.5
LP5951MFX-1.5
LP5951MFX-1.8
LP5951MFX-1.8
LP5951MFX-2.0
LP5951MFX-2.0
LP5951MFX-2.5
LP5951MFX-2.5
LP5951MFX-2.8
LP5951MFX-2.8
LP5951MFX-3.0
LP5951MFX-3.0
LP5951MFX-3.3
LP5951MFX-3.3
1.3
1.5
1.8
2.0
2.5
2.8
3.0
3.3
NOPB LKRB
LKAB
NOPB LKAB
LKBB
NOPB LKBB
LKCB
NOPB LKCB
LKEB
NOPB LKEB
LKFB
NOPB LKFB
LKGB
NOPB LKGB
LKHB
NOPB LKHB
Note: The package marking on the backside of the component designates the date code and a NSC internal code for die traceability. It will vary considerably.
SOT23-5: ZWTT
with: Z: 1 Digit Assembly Plant Code, W: 1 Digit Date Code, TT: 2 Digit Dierun Code
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2
Absolute Maximum Ratings (Notes 2,
1)
Operating Ratings (Notes 1, 2)
Input Voltage Range (VIN
)
1.8V to 5.5V
0 to (VIN + 0.3V)
-40˚C to + 125˚C
(Note 5)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VEN Input Voltage
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
VIN pin: Voltage to GND
EN pin: Voltage to GND
-0.3V to 6.5V
-0.3V to (VIN+0.3V)
with 5.5V max
Thermal Properties
Junction-to-Ambient Thermal
Resistance (θJA), (Note 6)
SOT23-5 Package:
Continuous Power
Dissipation(Note 3)
Internally Limited
150˚C
220˚C/W
Junction Temperature (TJ-MAX
Storage Temperature Range
Package Peak Reflow
Temperature (10-20 sec.)
Package Peak Reflow
)
-65˚C to + 150˚C
240˚C
260˚C
Temperature (Pb-free, 10-20 sec.)
ESD Rating(Note 4)
Human Body Model:
Machine Model
2.0kV
200V
ESD Caution Notice
National Semiconductor recommends that all integrated circuits be handled with appropriate precautions. Failure to observe
proper ESD handling techniques can result in damage.
Electrical Characteristics(Notes 2, 7)
Typical values and limits appearing in standard typeface are for TA = 25˚C. Limits appearing in boldface type apply over
the full operating temperature range: -40˚C ≤ TJ ≤ +125˚C. Unless otherwise noted, VIN = VOUT(NOM) + 1V, CIN = 1µF, COUT
= 1µF, VEN = 0.9V.
Limit
Symbol
VIN
Parameter
Input Voltage
Condition
VIN ≥ VOUT(NOM) + VDO
IOUT = 1mA
Typ
Min
1.8
Max
5.5
2.0
3.5
Units
V
Output Voltage
Tolerance
-2.0
-3.5
%
-30˚C ≤ TJ ≤ +125˚C
VIN = VOUT(NOM) + 1V to 5.5V
IOUT = 1mA
%
∆VOUT
VDO
IQ
Line Regulation Error
0.1
-0.01
200
%/V
Load Regulation Error IOUT = 1mA to 150mA
Output Voltage Dropout IOUT = 150mA
%/mA
(Note 10)
VOUT ≥ 2.5V
250
350
55
70
1
mV
mV
µA
<
VOUT 2.5V
Quiescent Current
VEN = 0.9V, ILOAD = 0
VEN = 0.9V, ILOAD = 150mA
VEN = 0V
29
33
µA
0.005
400
µA
ISC
Output Current
(short circuit)
Power Supply
Rejection Ratio
VIN = VOUT(NOM) + 1V
150
mA
PSRR
Sine modulated VIN
f = 100Hz
60
60
dB
dB
f = 1kHz
f = 10kHz
50
dB
EN
Output Noise
BW = 10Hz - 100kHz
125
160
20
µVRMS
˚C
TSD
Thermal Shutdown
Temperature Hysteresis
˚C
3
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Electrical Characteristics(Notes 2, 7) (Continued)
Enable Control Characteristics
Limit
Symbol
IEN
Parameter
Conditions
Typical
Min
-1
Max
1
Units
Maximum Input Current 0V ≤ VEN ≤ VIN, VIN = 5.5V
µA
at VEN Input
VIL
VIH
Low Input Threshold
(shutdown)
VIN = 1.8..5.5V
VIN = 1.8..5.5V
0.4
V
V
High Input Threshold
(enable)
0.9
Transient Characteristics
Limit
Symbol
Parameter
Dynamic Line Transient VIN = VOUT(NOM) + 1V to
VOUT(NOM) + 1V + 0.6V in 30µs, no
Conditions
Typical
Min
Max
Units
∆VOUT
2
mV
load
∆VOUT
Dynamic Load
Transient
IOUT = 0mA to 150mA in 10µs
IOUT = 150mA to 0mA in 10µs
IOUT = 1mA to 150mA in 1µs
IOUT = 150mA to 1mA in 1µs
Nominal conditions
-30
20
-50
40
10
30
mV
mV
mV
mV
mV
µs
∆VOUT
Overshoot on Startup
Turn on time
TON
IOUT = 1mA
Output Capacitor, Recommended Specification
Limit(Note 8)
Symbol
Parameter
Conditions
Value
Min
Max
Units
Capacitance (Note 9)
IOUT = 150mA, VIN = 5.0V
<
VOUT 2.8V
1.0
1.5
0.7
1.1
0.003
47
47
µF
µF
Ω
COUT
Output Capacitance
VOUT ≥ 2.8V
ESR
0.300
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T = 160˚C (typ.) and disengages at T
=
J
J
140˚C (typ.).
Note 4: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged
directly into each pin. (MIL-STD-883 3015.7)
Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
) is dependent on the maximum operating junction temperature (T
= 125˚C), the maximum power
A-MAX
J-MAX-OP
dissipation of the device in the application (P
), and the junction-to ambient thermal resistance of the part/package in the application (θ ), as given by the
D-MAX
– (θ x
JA PD-MAX
JA
following equation: T
= T
).
A-MAX
J-MAX-OP
Note 6: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special attention must be paid to thermal dissipation issues in board design.
Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 8: Min and Max limits are guaranteed by design
Note 9: The capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be considered when selecting
a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor type is X7R. However, dependent on application, X5R,
Y5V, and Z5U can also be used. The shown minimum limit represents real minimum capacitance, including all tolerances and must be maintained over temperature
and dc bias voltage (See capacitor section in Applications Hints)
Note 10: Dropout voltage is defined as the input to output voltage differential at which the output voltage falls to 100mV below the nominal output voltage. This
specification does not apply for input voltages below 1.8V.
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4
Output Current Derating
Maximum Load Current vs VIN - VOUT, TA = 85˚C, VOUT = 1.5V, SOT23-5 Package
20136208
Block Diagram
20136205
5
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Typical Performance Characteristics Unless otherwise specified, CIN = 1µF ceramic, COUT = 1µF
ceramic, VIN = VOUT(NOM) + 1V, TA = 25˚C, Enable pin is tied to VIN
.
Load Transient Response
Load Transient Response
Line Transient Response
Enable Start-up Time
20136209
20136210
Line Transient Response
20136211
20136212
Enable Start-up Time
20136213
20136214
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6
Typical Performance Characteristics Unless otherwise specified, CIN = 1µF ceramic, COUT = 1µF
ceramic, VIN = VOUT(NOM) + 1V, TA = 25˚C, Enable pin is tied to VIN
. (Continued)
Output Voltage Change vs Temperature
Ground Current vs VIN
20136217
20136216
Power Supply Rejection Ratio
20136215
7
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OUTPUT CAPACITOR
Application Hints
The LP5951 is designed specifically to work with very small
ceramic output capacitors. The following ceramic capacitors
(dielectric types X7R, Z5U, or Y5V) are suitable as COUT in
the LP5951 application circuit:
POWER DISSIPATION AND DEVICE OPERATION
The permissible power dissipation for any package is a
measure of the capability of the device to pass heat from the
power source, the junctions of the IC, to the ultimate heat
sink, the ambient environment. Thus the power dissipation is
dependent on the ambient temperature and the thermal
resistance across the various interfaces between the die and
ambient air.
<
-VOUT 2.8V: 1.0µF
-VOUT ≥ 2.8V: 1.5µF
COUT can be increased up to 47µF, the ESR should be
between 3 mΩ to 500 mΩ.
This capacitor must be located a distance of not more than
1cm from the VOUT pin and returned to a clean analogue
ground.
As stated in (Note 5) in the electrical specification section,
the allowable power dissipation for the device in a given
package can be calculated using the equation:
It is also possible to use tantalum or film capacitors at the
device output, VOUT, but these are not as attractive for
reasons of size and cost (see the section Capacitor Charac-
teristics).
PD = (TJ(MAX) - TA) / θJA
With a θJA = 220˚C/W, the device in the SOT23-5 package
returns a value of 454 mW with a maximum junction tem-
perature of 125˚C at TA of 25˚C.
CAPACITOR CHARACTERISTICS
The LP5951 is designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer. For
capacitance values in the range of 1µF to 4.7µF, ceramic
capacitors are the smallest, least expensive and have the
lowest ESR values, thus making them best for eliminating
high frequency noise. The ESR of a typical 1µF ceramic
capacitor is in the range of 3mΩ to 40mΩ, which easily
meets the ESR requirement for stability for the LP5951.
The actual power dissipation across the device can be esti-
mated by the following equation:
PD ≈ (VIN - VOUT) * IOUT
This establishes the relationship between the power dissipa-
tion allowed due to thermal consideration, the voltage drop
across the device, and the continuous current capability of
the device. These two equations should be used to deter-
mine the optimum operating conditions for the device in the
application.
For both input and output capacitors, careful interpretation of
the capacitor specification is required to ensure correct de-
vice operation. The capacitor value can change greatly, de-
pending on the operating conditions and capacitor type.
In particular, the output capacitor selection should take ac-
count of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance
can vary with DC bias conditions as well as temperature and
frequency of operation. Capacitor values will also show
some decrease over time due to aging. The capacitor pa-
rameters are also dependant on the particular case size,
with smaller sizes giving poorer performance figures in gen-
eral. As an example, Figure 1 shows a typical graph com-
paring different capacitor case sizes in a Capacitance vs. DC
Bias plot. As shown in the graph, increasing the DC Bias
condition can result in the capacitance value falling below
the minimum value given in the recommended capacitor
specifications table (0.7/1.1µF in this case). Note that the
graph shows the capacitance out of spec for the 0402 case
size capacitor at higher bias voltages. It is therefore recom-
mended that the capacitor manufacturers’ specifications for
the nominal value capacitor are consulted for all conditions,
as some capacitor sizes (e.g. 0402) may not be suitable in
the actual application.
EXTERNAL CAPACITORS
As is common with most regulators, the LP5951 requires
external capacitors to ensure stable operation. The LP5951
is specifically designed for portable applications requiring
minimum board space and the smallest size components.
These capacitors must be correctly selected for good perfor-
mance.
INPUT CAPACITOR
An input capacitor is required for stability. It is recommended
that a 1.0µF capacitor be connected between the LP5951
input pin and ground (this capacitance value may be in-
creased without limit).
This capacitor must be located a distance of not more than 1
cm from the input pin and returned to a clean analogue
ground. Any good quality ceramic, tantalum, or film capacitor
may be used at the input.
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge current when connected to a low-
impedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
be guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series
Resistance) on the input capacitor, but tolerance and tem-
perature coefficient must be considered when selecting the
capacitor to ensure the capacitance will remain ≥0.7µF over
the entire operating temperature range.
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8
If the application does not require the Enable switching
feature, the VEN pin should be tied to VIN to keep the
regulator output permanently on.
Application Hints (Continued)
To ensure proper operation, the signal source used to drive
the VEN input must be able to swing above and below the
specified turn-on/off voltage thresholds listed in the Electrical
Characteristics section under Enable Control Characteris-
tics, VIL and VIH
.
FAST TURN OFF AND ON
The controlled switch-off feature of the device provides a fast
turn off by discharging the output capacitor via an internal
FET device. This discharge is current limited by the RDSon
of this switch.
Fast turn-on is guaranteed by an optimized architecture
allowing a very fast ramp of the output voltage to reach the
target voltage.
SHORT-CIRCUIT PROTECTION
The LP5951 is short circuit protected and in the event of a
peak over-current condition, the output current through the
PMOS will be limited.
20136206
FIGURE 1. Graph Showing A Typical Variation In
Capacitance vs DC Bias
If the over-current condition exists for a longer time, the
average power dissipation will increase depending on the
input to output voltage difference until the thermal shutdown
circuitry will turn off the PMOS.
The ceramic capacitor’s capacitance can vary with tempera-
ture. The capacitor type X7R, which operates over a tem-
perature range of -55˚C to +125˚C, will only vary the capaci-
tance to within 15%. The capacitor type X5R has a similar
tolerance over a reduced temperature range of -55˚C to
+85˚C. Many large value ceramic capacitors, larger than 1µF
are manufactured with Z5U or Y5V temperature characteris-
tics. Their capacitance can drop by more than 50% as the
temperature varies from 25˚C to 85˚C. Therefore X7R is
recommended over Z5U and Y5V in applications where the
ambient temperature will change significantly above or be-
low 25˚C.
Please refer to the section on thermal information for power
dissipation calculations.
THERMAL-OVERLOAD PROTECTION
Thermal-Overload Protection limits the total power dissipa-
tion in the LP5951. When the junction temperature exceeds
TJ = 160˚C typ., the shutdown logic is triggered and the
PMOS is turned off, allowing the device to cool down. After
the junction temperature dropped by 20˚C (temperature hys-
teresis), the PMOS is activated again. This results in a
pulsed output voltage during continuous thermal-overload
conditions.
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
1µF to 4.7µF range.
The Thermal-Overload Protection is designed to protect the
LP5951 in the event of a fault condition. For normal, continu-
ous operation, do not exceed the absolute maximum junc-
tion temperature rating of TJ = +150˚C (see Absolute Maxi-
mum Ratings).
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum
capacitor with an ESR value within the stable range, it would
have to be larger in capacitance (which means bigger and
more costly) than a ceramic capacitor with the same ESR
value. It should also be noted that the ESR of a typical
tantalum will increase about 2:1 as the temperature goes
from 25˚C down to -40˚C, so some guard band must be
allowed.
REVERSE CURRENT PATH
The internal MOSFET in LP5951 has an inherent parasitic
body diode. During normal operation, the input voltage is
higher than the output voltage and the parasitic diode is
reverse biased. However, if the output is pulled above the
input in an application, then current flows from the output to
the input as the parasitic diode gets forward biased. The
output can be pulled above the input as long as the current
in the parasitic diode is limited to 50mA.
NO-LOAD STABILITY
The LP5951 will remain stable and in regulation with no
external load. This is an important consideration in some
circuits, for example CMOS RAM keep-alive applications.
For currents above this limit an external Schottky diode must
be connected from VOUT to VIN (cathode on VIN, anode on
VOUT).
ENABLE OPERATION
The LP5951 may be switched ON or OFF by a logic input at
the Enable pin, VEN. A logic high at this pin will turn the
device on. When the enable pin is low, the regulator output is
off and the device typically consumes 5nA.
9
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Physical Dimensions inches (millimeters) unless otherwise noted
20136207
5-Lead Small Outline Package SOT23-5 (MF),
NS Package Number MF05A
For most accurate revision please refer to www.national.com/packaging/parts/
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
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