MM54C157J [NSC]
Quad 2-Input Multiplexers; 四2输入多路复用器
| 型号： | MM54C157J |
| 厂家： | 
National Semiconductor |
| 描述： | Quad 2-Input Multiplexers |
| 文件： | 总4页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1988
MM54C157/MM74C157 Quad 2-Input Multiplexers
General Description
Features
Y
Supply voltage range
3V to 15V
0.45 V (typ.)
These multiplexers are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and P-chan-
nel enhancement transistors. They consist of four 2-input
multiplexers with common select and enable inputs. When
the enable input is at logical ‘‘0’’ the four outputs assume
the values as selected from the inputs. When the enable
input is at logical ‘‘1’’, the outputs assume logical ‘‘0’’. Se-
lect decoding is done internally resulting in a single select
input only.
Y
High noise immunity
CC
Y
Low power
50 nW (typ.)
Y
Tenth power TTL compatible
Drive 2 LPTTL loads
Logic & Connection Diagrams
Dual-In-Line Package
TL/F/5894–2
Top View
Order Number MM54C157 or MM74C157
TL/F/5894–1
Guaranteed Noise Margin
as a Function of V
Truth Table
CC
Enable
Select
A
B
Output Y
1
0
0
0
0
X
0
0
1
1
X
0
1
X
X
X
X
X
0
1
0
0
1
0
1
74L Compatibility
TL/F/5894–4
TL/F/5894–3
C
1995 National Semiconductor Corporation
TL/F/5894
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b
a
65 C to 150 C
Storage Temperature Range
Maximum V Voltage
§
§
18V
CC
Power Dissipation (P )
D
Dual-In-Line
Small Outline
b
a
0.3V
Voltage at Any Pin
0.3V to V
CC
700 mW
500 mW
Operating Temperature Range
MM54C157
MM74C157
b
b
a
a
55 C to 125 C
§
§
40 C to 85 C
Operating V Range
CC
3V to 15V
§
§
Lead Temperature (Soldering, 10 sec.)
260 C
§
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
e
e
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
V
V
5V
3.5
8.0
V
V
IN(1)
CC
10V
CC
e
e
V
V
5V
1.5
2.0
V
V
IN(0)
CC
10V
CC
e
e
V
V
5V
4.5
9.0
V
V
OUT(1)
OUT(0)
CC
10V
CC
e
e
V
V
5V
0.5
1.0
V
V
CC
10V
CC
e
e
e
I
I
I
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Supply Current
V
CC
V
CC
V
CC
15V
15V
15V
0.005
1.0
mA
mA
mA
IN(1)
IN(0)
CC
b
b
1.0
0.005
0.05
60
CMOS TO TENTH POWER INTERFACE
e
e
b
b
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
54C
74C
V
4.5V
V
V
1.5
1.5
V
V
IN(1)
CC
CC
V
4.75V
CC
CC
e
e
54C
74C
V
V
4.5V
0.8
0.8
V
V
IN(0)
CC
4.75V
CC
e
e
e b
4.5V, I
O
54C
74C
V
V
360 mA
e b
2.4
2.4
V
V
OUT(1)
OUT(0)
CC
4.75V, I
360 mA
e
360 mA
CC
O
e
e
54C
74C
V
V
4.5V, I
0.4
0.4
V
V
CC
O
e
4.75V, I
360 mA
CC
O
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
e
CC
e
e
I
I
I
I
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
V
5V, V
IN(0)
0V
0V
SOURCE
SOURCE
SINK
b
1.75
mA
mA
mA
mA
e
T
25 C, V
§
A
OUT
e
e
0V
V
CC
10V, V
IN(0)
b
8.0
e
e
T
25 C, V
§
0V
A
OUT
e
e
e
V
T
5V, V
IN(1)
5V
V
CC
1.75
8.0
e
25 C, V
§
A
OUT
CC
e
e
10V
V
CC
10V, V
IN(1)
SINK
e
e
V
T
25 C, V
§
A
OUT
CC
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
2
e
e
50 pF, unless otherwise specified
AC Electrical Characteristics* T
25 C, C
§
A
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
e
e
t
t
t
, t
pd0 pd1
Propagation Delay from
Data to Output
V
V
5.0V
10V
150
70
250
110
ns
ns
CC
CC
e
e
, t
pd0 pd1
Propagation Delay from
Select to Output
V
V
5V
180
80
300
130
ns
ns
CC
10V
CC
e
e
, t
pd0 pd1
Propagation Delay from
Enable to Output
V
V
5V
180
80
300
130
ns
ns
CC
10V
CC
C
C
Input Capacitance
(Note 2)
(Note 3)
5
pF
pF
IN
Power Dissipation
Capacitance
PD
20
*AC Parameters are guaranteed by DC correlated testing.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics, Application Note
PD
AN-90.
3
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C157J or MM74C157J
NS Package Number J16A
Molded Dual-In-Line Package (N)
Order Number MM54C157N or MM74C157N
NS Package Number N16E
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to the user.
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support device or system whose failure to perform can
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