MM54C173 [NSC]
TRI-STATE Quad D Flip-Flop; TRI- STATE四D触发器
| 型号： | MM54C173 |
| 厂家： | 
National Semiconductor |
| 描述： | TRI-STATE Quad D Flip-Flop |
| 文件： | 总6页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1988
MM54C173/MM74C173 TRI-STATE Quad D Flip-Flop
É
Features
General Description
Y
Supply voltage range
3V to 15V
The MM54C173/MM74C173 TRI-STATE quad D flip-flop is
a monolithic complementary MOS (CMOS) integrated circuit
constructed with N- and P-channel enhancement transis-
tors. The four D-type flip-flops operate synchronously from a
common clock. The TRI-STATE output allows the device to
be used in bus-organized systems.
Y
Tenth power TTL compatible
Drive 2 LPTTL loads
Y
High noise immunity
0.45 V
CC
(typ.)
Y
Low power
Y
Medium speed operation
Y
High impedance TRI-STATE
The outputs are placed in the TRI-STATE mode when either
of the two output disable pins are in the logic ‘‘1’’ level. The
input disable allows the flip-flops to remain in their present
states without disrupting the clock. If either of the two input
disables are taken to a logic ‘‘1’’ level, the Q outputs are fed
back to the inputs and in this manner the flip-flops do not
change state.
Y
Input disable without gating the clock
Applications
Y
Y
Y
Y
Y
Y
Y
Y
Automotive
Alarm systems
Data terminals
Instrumentation
Medical electronics
Industrial electronics
Remote metering
Computers
Clearing is enabled by taking the input to a logic ‘’1’’ level.
Clocking occurs on the positive-going transition.
Connection Diagram
Dual-In-Line Package
TL/F/5898–2
Top View
Order Number MM54C173 or MM74C173
Truth Table
(Both Output Disables Low)
t
t
a
n
n
1
Data
Input
Data Input Disable
Output
Logic ‘‘1’’ on One or Both Inputs
Logic ‘‘0’’ on Both Inputs
Logic ‘‘0’’ on Both Inputs
X
1
0
Q
n
1
0
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/5898
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Maximum V Voltage
CC
18V
Power Dissipation (P )
D
Dual-In-Line
Small Outline
700 mW
500 mW
b
a
0.3V
Voltage at Any Pin
0.3V to V
CC
Operating Temperature Range
MM54C173
MM74C173
Operating V Range
CC
3V to 15V
b
b
a
a
55 C to 125 C
§
§
40 C to 85 C
Lead Temperature (Soldering, 10 seconds)
260 C
§
§
§
b
a
65 C to 150 C
Storage Temperature Range
§
§
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
e
e
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
V
V
5V
3.5
8.0
V
V
IN(1)
CC
10V
CC
e
e
V
V
5V
1.5
2.0
V
V
IN(0)
CC
10V
CC
e
e
V
V
5V
4.5
9.0
V
V
OUT(1)
OUT(0)
CC
10V
CC
e
e
V
V
5V
0.5
1.0
V
V
CC
10V
CC
e
I
I
I
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
V
15V
0.005
0.005
1.0
mA
mA
IN(1)
IN(0)
OZ
CC
b
1.0
1.0
e
e
e
e
Output Current in High
Impedance State
V
V
15V, V
15V, V
15V
0V
0.001
0.001
1.0
mA
mA
CC
O
b
CC
O
e
I
Supply Current
V
CC
15V
0.05
300
mA
CC
LOW POWER TTL/CMOS INTERFACE
e
e
b
b
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
54C, V
74C, V
4.5V
4.5V
V
V
1.5
1.5
V
V
IN(1)
CC
CC
CC
CC
e
e
54C, V
74C, V
4.5V
0.8
0.8
V
V
IN(0)
CC
4.75V
CC
e
e
e b
4.5V, I
O
54C, V
74C, V
360 mA
e b
2.4
2.4
V
V
OUT(1)
OUT(1)
CC
4.75V, I
360 mA
e
360 mA
CC
O
e
e
54C, V
74C, V
4.5V, I
0.4
0.4
V
V
CC
O
e
4.75V, I
360 mA
CC
O
t , t
pd0 pd1
Propagation Delay Time to
a Logical ‘‘0’’ or Logical
‘‘1’’ from Clock
e
e
50 pF,
V
T
5V, C
CC
L
500
ns
e
25 C
§
A
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
e
CC
e
e
I
I
I
I
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
V
5V, V
IN(0)
0V
0V
SOURCE
SOURCE
SINK
b
1.75
mA
mA
mA
mA
e
T
25 C, V
§
A
OUT
e
e
0V
V
CC
10V, V
IN(0)
b
8.0
e
e
T
25 C, V
§
0V
A
OUT
e
e
e
V
T
5V, V
IN(1)
5V
V
CC
1.75
8.0
e
25 C, V
§
A
OUT
CC
e
e
10V
V
CC
10V, V
IN(1)
SINK
e
e
V
T
25 C, V
§
A
OUT
CC
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
2
e
e
50 pF, unless otherwise noted
AC Electrical Characteristics* T
25 C, C
§
A
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
e
e
t
t
t
t
t
t
t
t
t
f
t
, t
pd0 pd1
Propagation Delay Time to a Logical ‘‘0’’
or Logical ‘‘1’’ from Clock to Output
V
5V
220
80
400
200
ns
ns
CC
V
CC
10V
e
e
Input Data Set-up Time
V
V
5V
40
15
80
30
ns
ns
S
H
S
H
CC
10V
CC
e
e
Input Data Hold Time
V
V
5V
0
0
0
0
ns
ns
CC
10V
CC
e
e
Input Disable Set-up Time, t
S DISS
V
V
5V
100
35
200
70
ns
ns
CC
10V
CC
e
e
Input Disable Hold Time, t
H DISS
V
V
5V
0
0
0
0
ns
ns
CC
10V
CC
e
e
e
10k
, t
1H 0H
Delay from Output Disable to High Impedance
State (from Logical ‘‘1’’ or Logical ‘‘0’’ Level)
V
V
5V, R
L
170
70
340
140
ns
ns
CC
e
10V, R
10k
CC
L
e
e
Delay from Output Disable to Logical ‘‘1’’
Level (from High Impedance State)
V
V
5V
170
70
340
140
ns
ns
H1
H0
CC
10V
CC
e
e
Delay from Output Disable to Logical ‘‘0’’
Level (from High Impedance State)
V
V
5V
170
70
340
140
ns
ns
CC
10V
CC
e
e
, t
pd0 pd1
Propagation Delay from Clear to Output
V
V
5V
240
90
490
180
ns
ns
CC
10V
CC
e
e
Maximum Clock Frequency
V
V
5V
3
4
MHz
MHz
MAX
W
CC
10V
7.0
12
CC
e
e
Minimum Clear Pulse Width
V
V
5V
150
70
ns
ns
CC
10V
CC
e
e
t , t
r f
Maximum Clock Rise and Fall Time
V
V
5V
10
5
ms
ms
CC
10V
CC
C
C
Input Capacitance
(Note 2)
(Note 3)
5
pF
IN
Power Dissipation Capacitance
PD
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guarantee.d Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note
PD
AN-90.
Switching Time Waveforms
TL/F/5898–3
3
Logic Diagram
TL/F/5898–1
4
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C173J or MM74C173J
NS Package Number J16A
5
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number MM54C173N or MM74C173N
NS Package Number N16E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
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Hong Kong Ltd.
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Japan Ltd.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
MM54C173W
IC CMOS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERAMIC, FP-16, FF/Latch
TI
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