MM54C193 [NSC]
Synchronous 4-Bit Up/Down Decade Counter; 同步4位向上/向下十进制计数器
| 型号： | MM54C193 |
| 厂家： | 
National Semiconductor |
| 描述： | Synchronous 4-Bit Up/Down Decade Counter |
| 文件： | 总6页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1988
MM54C192/MM74C192
Synchronous 4-Bit Up/Down Decade Counter
MM54C193/MM74C193
Synchronous 4-Bit Up/Down Binary Counter
General Description
Features
Y
High noise margin
1V guaranteed
Drive 2 LPTTL loads
3V to 15V
These up/down counters are monolithic complementary
MOS (CMOS) integrated circuits. The MM54C192 and
MM74C192 are BCD counters, while the MM54C193 and
MM74C193 are binary counters.
Y
Tenth power TTL compatible
Y
Wide supply range
Y
Carry and borrow outputs for N-bit cascading
Asynchronous clear
Y
Y
Counting up and counting down is performed by two count
inputs, one being held high while the other is clocked. The
outputs change on the positive-going transition of this clock.
High noise immunity
0.45 V (typ.)
CC
These counters feature preset inputs that are set when load
is a logical ‘‘0’’ and a clear which forces all outputs to ‘‘0’’
when it is at a logical ‘‘1’’. The counters also have carry and
borrow outputs so that they can be cascaded using no ex-
ternal circuitry.
Connection Diagram
Dual-In-Line Package
TL/F/5901–1
Top View
Order Number MM54C192, MM74C192,
MM54C193 or MM74C193
C
1995 National Semiconductor Corporation
TL/F/5901
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b
a
65 C to 150 C
Storage Temperature Range (T )
S
§
§
18V
Maximum V Voltage
CC
Power Dissipation (P )
D
Dual-In-Line
Small Outline
b
a
0.3V
Voltage at Any Pin
0.3V to V
CC
700 mW
500 mW
Operating Temperature Range (T )
A
b
b
a
55 C to 125 C
MM54C154
MM74C154
§
40 C to 85 C
§
Operating V Range
CC
3V to 15V
a
§
§
Lead Temperature (T )
A
(Soldering, 10 sec.)
260 C
§
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
e
e
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
V
V
5V
3.5
8.0
V
V
IN(1)
CC
10V
CC
e
e
V
V
5V
1.5
2.0
V
V
IN(0)
CC
10V
CC
e
e
e b
5V, I
O
V
V
10 mA
e b
4.5
9.0
V
V
OUT(1)
OUT(0)
CC
10V, I
10 mA
CC
O
e
e
e
V
V
5V, I
10 mA
0.5
1.0
V
V
CC
O
e
10V, I
10 mA
CC
O
e
e
e
e
I
I
I
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Supply Current
V
CC
V
CC
V
CC
15V, V
15V, V
15V
15V
0V
0.005
1.0
mA
mA
mA
IN(1)
IN(0)
CC
IN
IN
e
b
b
1.0
0.005
0.05
300
CMOS TO LPTTL INTERFACE
e
e
b
b
V
V
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
54C
74C
V
4.5V
V
V
1.5
1.5
V
V
IN(1)
CC
CC
V
4.75V
CC
CC
e
e
54C
74C
V
V
4.5V
0.8
0.8
V
V
IN(0)
CC
4.75V
CC
e
e
e b
4.5V, I
O
54C
74C
V
V
100 mA
e b
2.4
2.4
V
V
OUT(1)
OUT(0)
CC
4.75V, I
100 mA
e
360 mA
CC
O
e
e
54C
74C
V
V
4.5V, I
0.4
0.4
V
V
CC
O
e
4.75V, I
360 mA
CC
O
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
e
CC
e
e
I
I
I
I
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
V
5V, V
IN(0)
0V
0V
SOURCE
SOURCE
SINK
b
1.75
mA
mA
mA
mA
e
T
25 C, V
§
A
OUT
e
e
0V
V
CC
10V, V
IN(0)
b
8
e
e
T
25 C, V
§
0V
A
OUT
e
e
e
V
T
5V, V
IN(1)
5V
V
CC
1.75
8
e
25 C, V
§
A
OUT
CC
e
e
10V
V
CC
10V, V
IN(1)
SINK
e
e
V
T
25 C, V
§
A
OUT
CC
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
2
e
e
50 pF, unless otherwise noted
AC Electrical Characteristics* T
25 C, C
§
A
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
e
e
t
Propagation Delay Time to Q
from Count Up or Down
V
V
5V
250
100
400
160
ns
ns
pd
pd
pd
S
CC
10V
CC
e
e
t
t
t
t
t
t
t
f
Propagation Delay Time to Q
Borrow from Count Down
V
V
5V
120
50
200
80
ns
ns
CC
10V
CC
e
e
Propagation Delay Time to
Carry from Count Up
V
V
5V
120
50
200
80
ns
ns
CC
10V
CC
e
e
Time Prior to Load that Data
Must be Present
V
V
5V
100
30
160
50
ns
ns
CC
10V
CC
e
e
Minimum Clear Pulse Width
V
V
5V
300
120
480
190
ns
ns
W
W
CC
10V
CC
e
e
Minimum Load Pulse Width
V
V
5V
100
40
160
65
ns
ns
CC
10V
CC
e
e
, t
pd0 pd1
Propagation Delay Time to Q
from Load
V
V
5V
300
120
480
190
ns
ns
CC
10V
CC
e
e
Minimum Count Pulse Width
Maximum Count Frequency
Count Rise and Fall Time
V
V
5V
120
35
200
80
ns
ns
W
CC
10V
CC
e
e
V
V
5V
2.5
6
4
MHz
MHz
MAX
CC
10V
10
CC
e
e
t , t
r
V
V
5V
15
5
ms
ms
f
CC
10V
CC
C
C
Input Capacitance
(Note 2)
(Note 3)
5
pF
pF
IN
Power Dissipation Capacitance
100
PD
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics, Application Note
PD
AN-90.
Cascading Packages
Guaranteed Noise Margin
as a Function of V
CC
TL/F/5901–3
TL/F/5901–2
3
Timing Diagrams
MM54C192/MM74C192
TL/F/5901–4
Note 1: Clear ouptuts to zero.
Note 2: Load (preset) to binary thirteen.
Note 3: Count up to fourteen, fifteen, carry, zero, one and two.
Note 4: Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
MM54C193/MM74C193
TL/F/5901–5
Note 1: Clear ouptuts to zero.
Note 2: Load (preset) to BCD seven.
Note 3: Count up to eight, nine, carry, zero, one, and two.
Note 4: Count down to one, zero, borrow, nine, eight, and seven.
Note A: Clear overrides load, data, and count inputs.
Note B: When counting up, count down input must be high; when counting down, count-up input must be high.
4
Schematic Diagrams
MM54C192 Synchronous 4-Bit Up/Down Decade Counter
TL/F/5901–6
MM54C193 Synchronous 4-Bit Up/Down Binary Counter
TL/F/5901–7
5
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C192J, MM74C192J, MM54C193J or MM74C193J
NS Package Number J16A
Molded Dual-In-Line Package (N)
Order Number MM54C192N, MM74C192N, MM54C193N or MM74C193N
NS Package Number N16E
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