MM54C906 [NSC]
Hex Open Drain N, P-Channel Buffers; 十六开漏N， P沟道缓冲器
| 型号： | MM54C906 |
| 厂家： | 
National Semiconductor |
| 描述： | Hex Open Drain N, P-Channel Buffers |
| 文件： | 总4页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1988
MM54C906/MM74C906
Hex Open Drain N-Channel Buffers
MM54C907/MM74C907
Hex Open Drain P-Channel Buffers
General Description
Features
Wide supply voltage range
Guaranteed noise margin
High noise immunity
Y
Y
Y
Y
3V to 15V
1V
These buffers employ monolithic CMOS technology in
achieving open drain outputs. The MM54C906/MM74C906
consists of six inverters driving six N-channel devices; and
the MM54C907/MM74C907 consists of six inverters driving
six P-channel devices. The open drain feature of these buff-
ers makes level shifting or wire AND and wire OR functions
by just the addition of pull-up or pull-down resistors. All in-
puts are protected from static discharge by diode clamps to
0.45 V
CC
(typ.)
High current sourcing and sinking
open drain outputs
V
CC
and to ground.
Connection and Logic Diagrams
Dual-In-Line Package
TL/F/5911–1
Top View
Order Number MM54C906, MM54C907, MM74C906 or MM74C907
MM54C906/MM74C906
MM54C907/MM74C907
TL/F/5911–2
TL/F/5911–3
C
1995 National Semiconductor Corporation
TL/F/5911
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b
a
65 C to 150 C
Storage Temperature Range
§
§
Power Dissipation
Dual-In-Line
Small Outline
700 mW
500 mW
b
a
0.3V
Voltage at Any Input Pin
0.3V to V
CC
Voltage at Any Output Pin
MM54C906/MM74C906
MM54C907/MM74C907
Operating V Range
CC
3V to 15V
18V
b
18 to V
a
0.3V to 18V
Absolute Maximum V
CC
b
a
V
0.3V
CC
CC
Lead Temperature (T )
L
(Soldering, 10 seconds)
Operating Temperature Range
MM54C906/MM54C907
MM74C906/MM74C907
260 C
§
b
a
55 C to 125 C
§ §
40 C to 85 C
b
a
§
§
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
e
e
V
IN(1)
Logical ‘‘1’’ Input Voltage
V
V
5V
3.5
8.0
V
V
CC
10V
CC
e
e
V
IN(0)
Logical ‘‘0’’ Input Voltage
V
V
5V
1.5
2
V
V
CC
10V
CC
e
e
e
e
e
I
I
I
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Supply Current
V
CC
V
CC
V
CC
15V, V
15V, V
15V
0V
0.005
1
mA
mA
mA
IN(1)
IN(0)
CC
IN
b
b
1.0
0.005
IN
15V, Output Open
0.05
15
Output Leakage
MM54C906
e
e
e
b
1.5V
CC
18V
V
V
4.5V, V
4.5V, V
V
e
CC
IN
OUT
0.005
0.005
0.005
0.005
5
5
5
5
mA
mA
mA
mA
CC
e
e
e
b
V 1.5V
CC
MM74C906
MM54C907
MM74C907
V
V
4.75V, V
4.75V, V
CC
IN
e
18V
CC
OUT
e
e
e
a
1V 0.1 V
CC
V
V
4.5V, V
4.5V, V
CC
IN
e
b
18V
V
CC
CC
OUT
e
e
e
a
1V 0.1 V
V
V
4.75V, V
4.75V, V
CC
IN
CC
b
18V
e
V
CC
CC
OUT
CMOS/LPTTL INTERFACE
e
e
b
b
V
IN(1)
Logical ‘‘1’’ Input Voltage
54C, V
74C, V
4.5V
V
V
1.5V
1.5V
V
V
CC
CC
4.75V
CC
CC
e
e
V
IN(0)
Logical ‘‘0’’ Input Voltage
54C, V
74C, V
4.5V
0.8
0.8
V
V
CC
4.75V
CC
OUTPUT DRIVE CURRENT
e
e
e
e
IN
a
0.5V
1.0V
MM54C906
V
CC
V
CC
V
CC
4.5V, V
4.5V, V
4.5V, V
1V 0.1 V
CC
e
e
2.1
4.2
8.0
mA
mA
OUT
OUT
12.0
e
e
e
e
IN
a
0.5V
1.0V
MM74C906
MM54C907
MM74C907
V
V
V
4.75V, V
4.75V, V
4.75V, V
1V 0.1 V
CC
e
e
CC
CC
CC
2.1
4.2
8.0
mA
mA
OUT
OUT
e
12.0
e
e
e
b
1.5V
V
CC
V
CC
V
CC
4.5V, V
4.5V, V
4.5V, V
V
CC
IN
e
e
b
b
b
b
b
V
V
0.5V
1V
1.05
1.5
3.0
mA
mA
OUT
OUT
CC
CC
b
2.1
e
e
e
e
b
1.5V
CC
V
CC
V
CC
V
CC
4.75V, V
4.75V, V
4.75V, V
V
IN
e
e
b
b
b
b
b
V
CC
V
CC
0.5V
1V
1.05
1.5
3.0
mA
mA
OUT
OUT
b
2.1
e
e
e
e
2V
MM54C906/MM74C906
V
CC
V
CC
V
CC
10V, V
10V, V
10V, V
IN
e
e
b
b
0.5V
1V
4.2
8.4
20
30
mA
mA
OUT
OUT
e
e
e
e
8V
MM54C907/MM74C907
V
CC
V
CC
V
CC
10V, V
10V, V
10V, V
IN
e
e
b
b
b
b
9.5V
9V
2.1
4.2
4.0
8.0
mA
mA
OUT
OUT
2
e
e
50 pF, unless otherwise specified
AC Electrical Characteristics* T
25 C, C
§
A
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd
Propagation Delay Time
to a Logical ‘‘0’’
e
e
e
e
e
10k
MM54C906/MM74C906
V
CC
V
CC
V
CC
V
CC
5.0V, R
150
75
ns
ns
ns
ns
e
10V, R
10k
a
MM54C907/MM74C907
5.0V (Note 4)
10V (Note 4)
150
75
0.7 RC
0.7 RC
a
t
pd
Propagation Delay Time
to a Logical ‘‘1’’
e
e
e
e
a
a
MM54C906/MM74C906
V
CC
V
CC
V
CC
V
CC
5.0V (Note 4)
10V (Note 4)
150
75
0.7 RC
0.7 RC
ns
ns
ns
ns
e
MM54C907/MM74C907
5.0V, R
10V, R
10k
10k
150
75
e
C
C
C
Input Capacitance
(Note 2)
(Note 2)
5.0
20
30
pF
pF
pF
IN
Output Capacity
OUT
PD
Power Dissipation Capacity
(Note 3) Per Buffer
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note,
PD
AN-90. (Assumes outputs are open).
Note 4: ‘‘C’’ used in calculating propagation includes output load capacity (C ) plus device output capacity (C
L
).
OUT
Typical Applications
Wire OR Gate
Wire AND Gate
TL/F/5911–5
TL/F/5911–4
Note: Can be extended to more than 2 inputs.
Note: Can be extended to more than 2 inputs.
CMOS or TTL to PMOS Interface
CMOS or TTL to CMOS at a Higher V
CC
s
V
15V
TL/F/5911–7
CC
TL/F/5911–6
3
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C906J, MM54C907J, MM74C906J, MM74C907J
NS Package Number J14A
Molded Dual-In-Line Package (N)
Order Number MM54C906N, MM54C907N, MM74C906N or MM74C907N
NS Package Number N14A
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to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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effectiveness.
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