MM54HC161E [NSC]
IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CQCC20, CERAMIC, LCC-20, Counter;
| 型号： | MM54HC161E |
| 厂家： | 
National Semiconductor |
| 描述： | IC HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CQCC20, CERAMIC, LCC-20, Counter 计数器 |
| 文件： | 总6页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1992
MM74HC160 Synchronous
Decade Counter with Asynchronous Clear
MM54HC161/MM74HC161 Synchronous
Binary Counter with Asynchronous Clear
MM54HC162/MM74HC162 Synchronous
Decade Counter with Synchronous Clear
MM54HC163/MM74HC163 Synchronous
Binary Counter with Synchronous Clear
General Description
T h e M M 5 4 H C 1 6 0 / M M 7 4 H C 1 6 0 , M M 5 4 H C 1 6 1 /
M M 7 4 H C 1 6 1 , M M 5 4 H C 1 6 2 / M M 7 4 H C 1 6 2 , a n d
MM54HC163/MM74HC163 synchronous presettable count-
ers utilize advanced silicon-gate CMOS technology and in-
ternal look-ahead carry logic for use in high speed counting
applications. They offer the high noise immunity and low
power consumption inherent to CMOS with speeds similar
to low power Schottky TTL. The ’HC160 and the ’HC162 are
4 bit decade counters, and the ’HC161 and the ’HC163 are
4 bit binary counters. All flip-flops are clocked simultaneous-
ly on the low to high transition (positive edge) of the CLOCK
input waveform.
The MM54HC160/MM74HC160 and MM54HC161/
MM74HC161 counters are cleared asynchronously. When
the CLEAR is taken low the counter is cleared immediately
regardless of the CLOCK.
Two active high enable inputs (ENP and ENT) and a RIP-
PLE CARRY (RC) output are provided to enable easy cas-
cading of counters. Both ENABLE inputs must be high to
count. The ENT input also enables the RC output. When
enabled, the RC outputs a positive pulse when the counter
overflows. This pulse is approximately equal in duration to
the high level portion of the Q output. The RC output is fed
A
to successive cascaded stages to facilitate easy implemen-
tation of N-bit counters.
These counters may be preset using the LOAD input. Pre-
setting of all four flip-flops is synchronous to the rising edge
of CLOCK. When LOAD is held low counting is disabled and
the data on the A, B, C, and D inputs is loaded into the
counter on the rising edge of CLOCK. If the load input is
taken high before the positive edge of CLOCK the count
operation will be unaffected.
All inputs are protected from damage due to static dis-
and ground.
charge by diodes to V
CC
Features
Y
Typical operating frequency: 40 MHz
Y
Y
Y
Y
Typical propagation delay; clock to Q: 18 ns
Low quiescent current: 80 mA maximum (74HC Series)
Low input current: 1 mA maximum
All of these counters may be cleared by utilizing the CLEAR
input. The clear function on the MM54HC162/MM74HC162
and MM54HC163/MM74HC163 counters are synchronous
to the clock. That is, the counters are cleared on the posi-
tive edge of CLOCK while the clear input is held low.
Wide power supply range: 2–6V
Connection Diagram
Truth Tables
’HC160/HC161
CLK CLR ENP ENT Load
Function
X
X
X
L
X
H
L
L
X
H
X
L
H
L
X
H
X
H
H
H
L
Clear
H
H
H
H
H
Count & RC disabled
Count disabled
Count & RC disabled
Load
X
u
H
Increment Counter
u
e
e
e
low level
H
X
high level, L
don’t care,
e
low to high transition
u
’HC162/HC163
CLK CLR ENP ENT Load
Function
L
X
H
L
L
X
H
X
L
H
L
X
H
X
H
H
H
L
Clear
u
X
X
H
H
H
H
H
Count & RC disabled
Count disabled
Count & RC disabled
Load
TL/F/5008–1
Order Number MM54HC161/162/163
or MM74HC160/161/162/163
X
u
u
H
Increment Counter
C
1995 National Semiconductor Corporation
TL/F/5008
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
Units
Supply Voltage (V
)
2
0
6
V
CC
DC Input or Output Voltage
(V , V
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
0.5V
IN
CC
CC
Operating Temp. Range (T )
A
DC Output Voltage (V
)
0.5 to V
b
b
a
85
a
125
MM74HC
MM54HC
40
55
C
OUT
§
C
g
g
g
Clamp Diode Current (I , I
)
20 mA
25 mA
50 mA
§
IK OK
DC Output Current, per pin (I
)
Input Rise or Fall Times
OUT
e
e
e
(t , t )
r f
V
V
V
2.0V
4.5V
6.0V
1000
500
ns
ns
ns
DC V or GND Current, per pin (I
CC
)
CC
CC
CC
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
400
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temp. (T ) (Soldering 10 seconds)
L
260 C
§
DC Electrical Characteristics (Note 4)
74HC
eb
54HC
e
T
A
25 C
§
eb
A
T
A
40 to 85 C
§
T
55 to 125 C
§
Symbol
Parameter
Conditions
V
CC
Units
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
IH
Maximum Low Level
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
IL
Input Voltage**
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
s
20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
4.0 mA
5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
l
l
OUT
OUT
l
l
I
e
V or V
IH IL
V
OL
Maximum Low Level
Output Voltage
V
IN
s
I
20 mA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
4.0 mA
5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
l
l
OUT
OUT
l
l
I
e
g
g
g
1.0
I
I
Maximum Input
Current
V
V
or GND 6.0V
0.1
1.0
mA
IN
IN
CC
e
Maximum Quiescent
Supply Current
V
IN
V
CC
or GND 6.0V
8.0
80
160
mA
CC
e
I
0 mA
OUT
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
IL CC IL CC
2
e
e
e
e e
15 pF, t t 6 ns
r f
AC Electrical Characteristics V
5V, T
25 C, C
§
CC
A
L
Symbol
Parameter
Conditions
Typ
43
30
29
18
27
10
Guaranteed Limit
Units
MHz
ns
f
t
t
t
t
t
t
Maximum Operating Frequency
30
35
34
32
38
20
30
MAX
, t
PHL PLH
Maximum Propagation Delay, Clock to RC
Maximum Propagation Delay, Clock to Q
Maximum Propagation Delay, ENT to RC
, t
PHL PLH
ns
, t
PHL PLH
ns
Maximum Propagation Delay, Clear to Q or RC
Minimum Removal Time, Clear to Clock
ns
PHL
REM
S
ns
Minimum Set Up Time Clear, Load,
Enable or Data to Clock
ns
t
t
Minimum Hold Time, Data from Clock
5
ns
ns
H
Minimum Pulse Width Clock,
Clear, or Load
16
W
e
e
t
f
e
e
AC Electrical Characteristics C 50 pF, t
6 ns (unless otherwise specified)
L
r
74HC
40 to 85 C
54HC
55 to 125 C
T
A
25 C
§
eb
eb
T
A
T
§
Guaranteed Limits
§
Symbol
Parameter
Conditions
V
CC
Units
A
Typ
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Maximum Operating
Frequency
2.0V
4.5V
6.0V
10
40
45
5
27
32
4
21
25
4
18
21
MHz
MHz
MHz
MAX
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PHL
REM
S
Maximum Propagation
Delay, Clock to RC
2.0V
4.5V
6.0V
100
32
28
215
43
37
271
54
46
320
64
54
ns
ns
ns
Maximum Propagation
Delay, Clock to RC
2.0V
4.5V
6.0V
88
18
15
175
35
30
220
44
37
260
52
44
ns
ns
ns
Maximum Propagation
Delay, Clock to Q
2.0V
4.5V
6.0V
95
30
26
205
41
35
258
52
44
305
61
52
ns
ns
ns
Maximum Propagation
Delay, Clock to Q
2.0V
4.5V
6.0V
85
17
14
170
34
29
214
43
36
253
51
43
ns
ns
ns
Maximum Propagation
Delay, ENT to RC
2.0V
4.5V
6.0V
90
28
24
195
39
33
246
49
42
291
58
49
ns
ns
ns
Maximum Propagation
Delay, ENT to RC
2.0V
4.5V
6.0V
80
16
14
160
32
27
202
40
34
238
48
41
ns
ns
ns
Maximum Propagation
Delay, Clear to RC
2.0V
4.5V
6.0V
100
32
28
220
44
37
275
55
47
325
66
55
ns
ns
ns
Maximum Propagation
Delay, Clear to Q
2.0V
4.5V
6.0V
100
32
28
210
42
36
260
52
45
315
63
54
ns
ns
ns
Minimum Removal Time
Clear to Clock
2.0V
4.5V
6.0V
125
25
21
158
32
27
186
37
32
ns
ns
ns
Minimum Setup
Time Clear or Data
to Clock
2.0V
4.5V
6.0V
150
30
26
190
38
32
225
45
38
ns
ns
ns
Minimum Setup
Time Load
to Clock
2.0V
4.5V
6.0V
135
27
23
170
34
29
200
41
35
ns
ns
ns
S
Minimum Setup
Time Enable
to Clock
2.0V
4.5V
6.0V
175
35
30
220
44
37
260
52
44
ns
ns
ns
S
Minimum Hold Time
Data from Clock
2.0V
4.5V
6.0V
50
10
9
63
13
11
75
15
13
ns
ns
ns
H
3
e
e e
t
f
AC Electrical Characteristics (Continued) C 50 pF, t
6 ns (unless otherwise specified)
74HC 54HC
L
r
e
T
25 C
§
A
eb
eb
T
40 to 85 C
T
55 to 125 C
§
§
Guaranteed Limits
Symbol
Parameter
Conditions
V
Units
A
A
CC
Typ
t
t
t
Minimum Hold Time
Enable, Load or Clear
to Clock
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
H
Minimum Pulse Width
Clock, Clear, or
Load
2.0V
4.5V
6.0V
80
16
14
100
20
17
120
24
20
ns
ns
ns
W
, t
TLH THL
Maximum
Output Rise and
Fall Time
2.0V 40
4.5V
6.0V
75
15
13
95
19
16
110
22
19
ns
ns
ns
8
7
t , t
r f
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
C
C
Power Dissipation
Capacitance (Note 5)
(per package)
90
5
pF
PD
Maximum Input Capacitance
10
10
10
pF
IN
2
V
CC
e
a
I
CC
Note 5:
e
C
determines the no load dynamic power consumption,
P
C
f
V
CC
, and the no load dynamic current consumption,
PD
f
D
PD
a
I
CC
I
C
V
PD CC
.
S
Logic Diagrams
MM54HC160/MM74HC160 or MM54HC162/MM74HC162
TL/F/5008–2
MM54HC161/MM74HC161 or MM54HC163/MM74HC163
TL/F/5008–3
4
Logic Waveforms
160, 162 Synchronous Decade Counters Typical Clear, Preset, Count and Inhibit Sequences
Sequence:
TL/F/5008–4
(1) Clear outputs to zero
(2) Preset to BCD seven
(3) Count to eight, nine, zero, one, two, and three
(4) Inhibit
161, 163 Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences
Sequence:
TL/F/5008–5
(1) Clear outputs to zero
(2) Preset to binary twelve
(3) Count to thirteen, fourteen, fifteen, zero, one and two
(4) Inhibit
5
Physical Dimensions inches (millimeters)
Order Number MM54HC160J, MM54HC161J, MM54HC162J, MM54HC163J,
MM74HC160J, MM74HC161J, MM74HC162J, MM74HC163J
NS Package J16A
Order Number MM74HC160N, MM74HC161N, MM74HC162N, MM74HC163N
NS Package N16E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
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Fax:
(
49) 0-180-530 85 86
@
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(
49) 0-180-530 85 85
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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