MM54HC173J [NSC]
TRI - STATE-R QUAD D FLIP-FLOP; TRI - 州-R QUAD D触发器
| 型号： | MM54HC173J |
| 厂家： | 
National Semiconductor |
| 描述： | TRI - STATE-R QUAD D FLIP-FLOP |
| 文件： | 总6页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1988
MM54HC173/MM74HC173
TRI-STATE Quad D Flip-Flop
É
General Description
The MM54HC173/MM74HC173 is a high speed TRI-STATE
QUAD D TYPE FLIP-FLOP that utilizes advanced silicon-
gate CMOS technology. It possesses the low power con-
sumption and high noise immunity of standard CMOS inte-
grated circuits, and can operate at speeds comparable to
the equivalent low power Schottky device. The outputs are
buffered, allowing this circuit to drive 15 LS-TTL loads. The
large output drive capability and TRI-STATE feature make
this part ideally suited for interfacing with bus lines in a bus
oriented system.
the inputs, forcing the flip flops to remain in the same state.
Clearing is enabled by taking the CLEAR input to a logic ‘‘1’’
level. The data outputs change state on the positive going
edge of the clock.
The 54HC/74HC logic family is functionally as well as pin-
out compatible with the standard 54LS/74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
and ground.
CC
Features
Y
The four D TYPE FLIP-FLOPS operate synchronously from
a common clock. The TRI-STATE outputs allow the device
to be used in bus organized systems. The outputs are
placed in the TRI-STATE mode when either of the two out-
put disable pins are in the logic ‘‘1’’ level. The input disable
allows the flip-flops to remain in their present states without
having to disrupt the clock. If either of the 2 input disables
are taken to a logic ‘‘1’’ level, the Q outputs are fed back to
Typical propagation delay: 18 ns
Y
Wide operating supply voltage range: 2–6V
TRI-STATE outputs
Y
Y
Y
Y
Low input current: 1 mA maximum
Low quiescent supply current: 80 mA maximum (74HC)
High output drive current: 6 mA minimum
Connection Diagram
Truth Table
Inputs
Dual-In-Line Package
Output
Q
Data Enable
Data
D
Clear Clock
G1
G2
H
L
L
L
L
L
X
X
X
H
X
L
X
X
X
H
L
X
X
X
X
L
L
L
Q
0
Q
0
Q
0
u
u
u
u
L
L
L
H
H
When either M or N (or both) is (are) high the out-
put is disabled to the high-impedance state: how-
ever, sequential operation of the flip-flops is not
affected.
e
e
e
e
H
L
high level (steady state)
low level (steady state)
low-to-high level transition
u
X
don’t care (any input including transitions)
e
tions were established
Q
the level of Q before the indicated steady state input condi-
O
TL/F/5317–1
Top View
Order Number MM54HC173 or MM74HC173
TRI-STATE is a registered trademark of National Semiconductor Corp.
É
C
1995 National Semiconductor Corporation
TL/F/5317
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
6
Units
V
Supply Voltage (V
)
CC
2
DC Input or Output Voltage
(V , V
0
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
0.5V
Operating Temp. Range (T )
A
MM74HC
MM54HC
IN
CC
CC
b
b
a
40
55
85
C
C
§
§
DC Output Voltage (V
)
0.5 to V
OUT
a
125
g
g
g
Clamp Diode Current (I , I
)
20 mA
35 mA
70 mA
IK OK
Input Rise or Fall Times
DC Output Current, per pin (I
)
OUT
e
e
e
(t , t )
V
V
V
2.0V
4.5V
6.0V
1000
500
400
ns
ns
ns
r
f
CC
CC
CC
DC V or GND Current, per pin (I
CC
)
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temperature (T )
L
(Soldering 10 seconds)
260 C
§
DC Electrical Characteristics (Note 4)
74HC
54HC
e
T
A
25 C
§
eb
eb
T
A
40 to 85 C
§
T
A
55 to 125 C
§
Symbol
Parameter
Conditions
V
Units
CC
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
IH
Maximum Low Level
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
IL
Input Voltage**
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
s
20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
6.0 mA
7.8 mA
4.5V
6.0V
3.98
5.48
3.84
5.34
3.7
5.2
V
V
l
l
OUT
OUT
l
l
I
e
V or V
IH IL
V
OL
Maximum Low Level
Output Voltage
V
IN
s
I
20 mA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
6.0 mA
7.8 mA
4.5V
6.0V
0.26
0.26
0.33
0.33
0.4
0.4
V
V
l
l
OUT
OUT
l
l
I
e
V or GND
CC
g
g
g
1.0
I
I
I
Maximum Input
Current
V
6.0V
0.1
1.0
mA
mA
mA
IN
IN
e
V or GND 6.0V
CC
g
g
g
10
Maximum TRI-STATE
Output Leakage
V
0.5
5.0
OZ
CC
OUT
e
Enable
V
IH
or GND
CC
e
Maximum Quiescent
Supply Current
V
IN
V
6.0V
8.0
80
160
e
I
0 mA
OUT
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
IL CC IL CC
2
e
e
e
e e
45 pF, t t 6 ns
r f
AC Electrical Characteristics V
5V, T
25 C, C
§
CC
A
L
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
Units
MHz
ns
f
t
Maximum Operating Frequency
45
30
31
MAX
, t
PHL PLH
Maximum Propagation
Delay: Clock to Q
t
Maximum Propagation
Delay: Clear to Q
18
27
ns
PHL
e
t
t
, t
PZH PZL
Maximum Output Enable Time
R
R
1 kX
18
16
28
25
ns
ns
L
e
e
, t
PHZ PLZ
Maximum Output Disable
Time
1 kX
5 pF
L
L
C
t
t
t
t
t
Minimum Data Setup Time
20
20
0
ns
ns
ns
ns
ns
S
Minimum Data Enable Setup Time
Minimum Data Hold Time
S
H
H
W
Minimum Data Enable Hold Time
Minimum Clock Pulse Width
0
16
e
e
e
e
t
f
AC Electrical Characteristics V
2.0V to 6.0V, C
50 pF, t
6 ns (unless otherwise specified)
CC
L
r
74HC 54HC
eb
A
e
T
25 C
§
A
eb
T
40 to 85 C
T
55 to 125 C
§
§
Guaranteed Limits
Symbol
Parameter
Conditions
V
Units
A
CC
Typ
e
f
t
Maximum Operating
Frequency
C
50 pF
2.0V
4.5V
6.0V
10
45
55
5
27
32
4
21
25
4
18
21
MHz
MHz
MHz
MAX
L
e
e
, t
PHL PLH
Maximum Propagation
Delay from Clock to Q
C
L
C
L
50 pF 175
150 pF 2.0V 110 225
2.0V
80
220
280
262
338
ns
ns
e
e
C
L
C
L
50 pF 4.5V
150 pF 4.5V
23
28
35
45
44
56
53
68
ns
ns
e
e
C
L
C
L
50 pF 6.0V
150 pF 6.0V
21
26
30
38
38
48
45
57
ns
ns
e
e
t
t
Maximum Propagation
Delay from Clear to Q
C
C
50 pF
2.0V
70
150
150 pF 2.0V 100 200
189
252
224
298
ns
ns
PHL
L
L
e
e
C
L
C
L
50 pF 4.5V
150 pF 4.5V
20
25
30
40
38
50
45
60
ns
ns
e
e
C
L
C
L
50 pF 6.0V
150 pF 6.0V
17
22
26
34
32
43
38
51
ns
ns
e
e
e
e
e
e
e
, t
PZH PZL
Maximum Output
Enable Time
R
1 kX
50 pF
L
L
L
L
L
L
L
C
C
C
C
C
C
2.0V
70
150
150 pF 2.0V 100 200
189
252
38
50
32
224
298
45
60
38
ns
ns
ns
ns
ns
ns
50 pF
150 pF 4.5V
50 pF 6.0V
150 pF 6.0V
4.5V
20
25
17
22
30
40
26
34
43
51
e
e
t
t
t
t
t
, t
PHZ PLZ
Maximum Output Disable
Time
R
C
1 kX
50 pF
2.0V
4.5V
6.0V
70
20
17
150
30
26
189
38
32
224
45
38
ns
ns
ns
L
L
Minimum Data or Data
Enable Setup Time
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
S
Minimum Removal
Time
2.0V
4.5V
6.0V
90
18
15
112
22
19
135
26
22
ns
ns
ns
REM
H
Minimum Data or Data Enable
Hold Time
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
Minimum Clear or Clock
Pulse Width
2.0V
4.5V
6.0V
30
9
8
80
16
14
100
20
17
120
24
20
ns
ns
ns
W
3
AC Electrical Characteristics (Continued)
e
e
e e
50 pF, t t 6 ns (unless otherwise specified)
r f
V
2.0V to 6.0V, C
CC
L
74HC
eb
54HC
e
T
A
25 C
§
eb
T
40 to 85 C
§
T
A
55 to 125 C
§
Symbol
Parameter
Conditions
V
CC
Units
A
Typ
Guaranteed Limits
t , t
THL TLH
Maximum Output
Rise and Fall Time
2.0V 25
60
12
10
75
15
13
90
18
15
ns
ns
ns
4.5V
6.0V
7
5
t , t
r f
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
1000
500
1000
500
ns
ns
ns
400
400
400
C
C
C
Power Dissipation Capacitance (per flop)
Maximum Input Capacitance
80
5
pF
pF
pF
PD
10
20
10
20
10
20
IN
Maximum Output
Capacitance
10
OUT
2
e
a
e
, and the no load dynamic current consumption, I C
S PD CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
I V
CC CC
V
D
a
f
I
.
CC
4
Physical Dimensions inches (millimeters)
Dual-In-Line Package
Order Number MM54HC173J or MM74HC173J
NS Package J16A
5
Physical Dimensions inches (millimeters) (Continued)
Dual-In-Line Package
Order Number MM74HC173N
NS Package N16E
LIFE SUPPORT POLICY
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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